Lines Matching refs:lane
304 int lane;
306 for (lane = 0; lane < lane_count; lane++) {
307 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
308 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
310 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
311 lane,
331 for (lane = 0; lane < 4; lane++)
332 train_set[lane] = v | p;
345 /* get the max pix clock supported by the link rate and lane num */
355 /* First get the min lane# when low rate is used according to pixel clock
356 * (prefer low rate), second check max lane# supported by DP panel,
357 * if the max lane# < low rate lane# then use max lane# instead.
659 /* set the lane count on the sink */