1285431Szbb/*- 2285431Szbb******************************************************************************** 3285431SzbbCopyright (C) 2015 Annapurna Labs Ltd. 4285431Szbb 5285431SzbbThis file may be licensed under the terms of the Annapurna Labs Commercial 6285431SzbbLicense Agreement. 7285431Szbb 8285431SzbbAlternatively, this file can be distributed under the terms of the GNU General 9285431SzbbPublic License V2 as published by the Free Software Foundation and can be 10285431Szbbfound at http://www.gnu.org/licenses/gpl-2.0.html 11285431Szbb 12285431SzbbAlternatively, redistribution and use in source and binary forms, with or 13285431Szbbwithout modification, are permitted provided that the following conditions are 14285431Szbbmet: 15285431Szbb 16285431Szbb * Redistributions of source code must retain the above copyright notice, 17285431Szbbthis list of conditions and the following disclaimer. 18285431Szbb 19285431Szbb * Redistributions in binary form must reproduce the above copyright 20285431Szbbnotice, this list of conditions and the following disclaimer in 21285431Szbbthe documentation and/or other materials provided with the 22285431Szbbdistribution. 23285431Szbb 24285431SzbbTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25285431SzbbANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26285431SzbbWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27285431SzbbDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28285431SzbbANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29285431Szbb(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30285431SzbbLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31285431SzbbANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32285431Szbb(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33285431SzbbSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34285431Szbb 35285431Szbb*******************************************************************************/ 36285431Szbb 37285431Szbb/** 38285431Szbb * @defgroup grouppcie PCI Express Controller 39285431Szbb * @{ 40285431Szbb * @section overview Overview 41285431Szbb * This header file provide API for the HAL driver of the pcie port, the driver 42285431Szbb * provides the following functionalities: 43285431Szbb * - Port initialization 44285431Szbb * - Link operation 45285431Szbb * - Interrupts transactions generation (Endpoint mode). 46285431Szbb * - Configuration Access management functions 47285431Szbb * - Internal Translation Unit programming 48285431Szbb * 49285431Szbb * This API does not provide the following: 50285431Szbb * - PCIe transactions generation and reception (except interrupts as mentioned 51285431Szbb * above) as this functionality is done by the port without need for sw 52285431Szbb * intervention. 53285431Szbb * - Configuration Access: those transactions are generated automatically by 54285431Szbb * the port (ECAM or ATU mode) when the CPU issues memory transaction 55285431Szbb * through the fabric toward the PCIe port. This API provides management 56285431Szbb * function for controlling the Configuration Access type and bus destination 57285431Szbb * - Interrupt Handling. 58285431Szbb * - Message Generation: common used messages are automatically generated, also, 59285431Szbb * the ATU generic mechanism for generating various kind of messages. 60285431Szbb * - PCIe Port Management: both link and port power management features can be 61285431Szbb * managed using the PCI/PCIe standard power management and PCIe capabilities 62285431Szbb * registers. 63285431Szbb * - PCIe link and protocol error handling: the feature can be managed using 64285431Szbb * the Advanced Error Handling PCIe capability registers. 65285431Szbb * 66285431Szbb * @section flows Software Flows 67285431Szbb * @subsection init Initialization 68285431Szbb * - allocation and set zeros al_pcie_port and al_pcie_pf structures handles 69285431Szbb * - call al_pcie_port_handle_init() with pointer to the allocated 70285431Szbb * al_pcie_port handle, address of the port internal registers space, and 71285431Szbb * port id. 72285431Szbb * - call al_pcie_pf_handle_init() with pointer to the al_pcie_port handle 73285431Szbb * and pf_number. 74285431Szbb * - set the port mode, End-Point or Root-Compex (default). 75285431Szbb * - set number of lanes connected to the controller. 76285431Szbb * - enable the controller using the al_pcie_port_enable(). note that this 77285431Szbb * function expect the virtual address of the PBS Functional Registers. 78285431Szbb * - wait for 2000 South-bridge cycles. 79285431Szbb * - prepare al_pcie_port_config_params and al_pcie_pf_config_params 80285431Szbb * structures depending on chip, board and system configuration. 81285431Szbb * for example, when using the port as root complex, the operating_mode 82285431Szbb * field should be set to AL_PCIE_OPERATING_MODE_RC. In this example we 83285431Szbb * prepare the following configuration: 84285431Szbb * For port configuration 85285431Szbb * - Root Complex mode 86285431Szbb * - Set the Max Link Speed to Gen2 87285431Szbb * - Set the max lanes width to 2 (x2) 88285431Szbb * - Disable reversal mode 89285431Szbb * - Enable Snoops to support I/O Hardware cache coherency 90285431Szbb * - Enable pcie core RAM parity 91285431Szbb * - Enable pcie core AXI parity 92285431Szbb * - Keep transaction layer default credits 93285431Szbb * For pf configuration 94285431Szbb * - No EP parameters 95285431Szbb * - No SR-IOV parameters 96285431Szbb * so the structures we prepare: 97285431Szbb * @code 98285431Szbb * - struct al_pcie_link_params link_params = { 99285431Szbb * AL_PCIE_LINK_SPEED_GEN2, 100285431Szbb * AL_FALSE, // disable reversal mode 101285431Szbb * AL_PCIE_MPS_DEFAULT}; 102285431Szbb * 103285431Szbb * - struct al_pcie_port_config_params config_params = { 104285431Szbb * &link_params, 105285431Szbb * AL_TRUE, // enable Snoop for inbound memory transactions 106285431Szbb * AL_TRUE, // enable pcie port RAM parity 107285431Szbb * AL_TRUE, // enable pcie port AXI parity 108285431Szbb * NULL, // use default latency/replay timers 109285431Szbb * NULL, // use default gen2 pipe params 110285431Szbb * NULL, // gen3_params not needed when max speed set to Gen2 111285431Szbb * NULL, // don't change TL credits 112285431Szbb * NULL, // end point params not needed 113285431Szbb * AL_FALSE, //no fast link 114285431Szbb * AL_FALSE}; //return 0xFFFFFFFF for read transactions with 115285431Szbb * //pci target error 116285431Szbb * @endcode 117285431Szbb * - now call al_pcie_port_config() with pcie_port and port_config_params 118285431Szbb * @subsection link-init Link Initialization 119285431Szbb * - once the port configured, we can start PCIe link: 120285431Szbb * - call al_pcie_link_start() 121285431Szbb * - call al_pcie_link_up_wait() 122285431Szbb * - allocate al_pcie_link_status struct and call al_pcie_link_status() and 123285431Szbb * check the link is established. 124285431Szbb * 125285431Szbb * @subsection cap Configuration Access Preparation 126285431Szbb * - Once the link is established, we can prepare the port for pci 127285431Szbb * configuration access, this stage requires system knowledge about the PCI 128285431Szbb * buses enumeration. For example, if 5 buses were discovered on previously 129285431Szbb * scanned root complex port, then we should start enumeration from bus 5 (PCI 130285431Szbb * secondary bus), the sub-ordinary bus will be temporarily set to maximum 131285431Szbb * value (255) until the scan process under this bus is finished, then it will 132285431Szbb * updated to the maximum bus value found. So we use the following sequence: 133285431Szbb * - call al_pcie_secondary_bus_set() with sec-bus = 5 134285431Szbb * - call al_pcie_subordinary_bus_set() with sub-bus = 255 135285431Szbb * 136285431Szbb * @subsection cfg Configuration (Cfg) Access Generation 137285431Szbb * - we assume using ECAM method, in this method, the software issues pcie Cfg 138285431Szbb * access by accessing the ECAM memory space of the pcie port. For example, to 139285431Szbb * issue 4 byte Cfg Read from bus B, Device D, Function F and register R, the 140285431Szbb * software issues 4 byte read access to the following physical address 141285431Szbb * ECAM base address of the port + (B << 20) + (D << 15) + (F << 12) + R. 142285431Szbb * But, as the default size of the ECAM address space is less than 143285431Szbb * needed full range (256MB), we modify the target_bus value prior to Cfg 144285431Szbb * access in order make the port generate Cfg access with bus value set to the 145285431Szbb * value of the target_bus rather than bits 27:20 of the physical address. 146285431Szbb * - call al_pcie_target_bus_set() with target_bus set to the required bus of 147285431Szbb * the next Cfg access to be issued, mask_target_bus will be set to 0xff. 148285431Szbb * no need to call that function if the next Cfg access bus equals to the last 149285431Szbb * value set to target_bus. 150285431Szbb * 151285431Szbb * @file al_hal_pcie.h 152285431Szbb * @brief HAL Driver Header for the Annapurna Labs PCI Express port. 153285431Szbb */ 154285431Szbb 155285431Szbb#ifndef _AL_HAL_PCIE_H_ 156285431Szbb#define _AL_HAL_PCIE_H_ 157285431Szbb 158285431Szbb#include "al_hal_common.h" 159285431Szbb#include "al_hal_pcie_regs.h" 160285431Szbb 161285431Szbb/******************************************************************************/ 162285431Szbb/********************************* Constants **********************************/ 163285431Szbb/******************************************************************************/ 164285431Szbb 165285431Szbb/** Inbound header credits sum - rev 0/1/2 */ 166285431Szbb#define AL_PCIE_REV_1_2_IB_HCRD_SUM 97 167285431Szbb/** Inbound header credits sum - rev 3 */ 168285431Szbb#define AL_PCIE_REV3_IB_HCRD_SUM 259 169285431Szbb 170285431Szbb/** Number of extended registers */ 171285431Szbb#define AL_PCIE_EX_REGS_NUM 40 172285431Szbb 173285431Szbb/******************************************************************************* 174285431Szbb * PCIe AER uncorrectable error bits 175285431Szbb * To be used with the following functions: 176285431Szbb * - al_pcie_aer_config 177285431Szbb * - al_pcie_aer_uncorr_get_and_clear 178285431Szbb ******************************************************************************/ 179285431Szbb/** Data Link Protocol Error */ 180285431Szbb#define AL_PCIE_AER_UNCORR_DLP_ERR AL_BIT(4) 181285431Szbb/** Poisoned TLP */ 182285431Szbb#define AL_PCIE_AER_UNCORR_POISIONED_TLP AL_BIT(12) 183285431Szbb/** Flow Control Protocol Error */ 184285431Szbb#define AL_PCIE_AER_UNCORR_FLOW_CTRL_ERR AL_BIT(13) 185285431Szbb/** Completion Timeout */ 186285431Szbb#define AL_PCIE_AER_UNCORR_COMPL_TO AL_BIT(14) 187285431Szbb/** Completer Abort */ 188285431Szbb#define AL_PCIE_AER_UNCORR_COMPL_ABT AL_BIT(15) 189285431Szbb/** Unexpected Completion */ 190285431Szbb#define AL_PCIE_AER_UNCORR_UNEXPCTED_COMPL AL_BIT(16) 191285431Szbb/** Receiver Overflow */ 192285431Szbb#define AL_PCIE_AER_UNCORR_RCV_OVRFLW AL_BIT(17) 193285431Szbb/** Malformed TLP */ 194285431Szbb#define AL_PCIE_AER_UNCORR_MLFRM_TLP AL_BIT(18) 195285431Szbb/** ECRC Error */ 196285431Szbb#define AL_PCIE_AER_UNCORR_ECRC_ERR AL_BIT(19) 197285431Szbb/** Unsupported Request Error */ 198285431Szbb#define AL_PCIE_AER_UNCORR_UNSUPRT_REQ_ERR AL_BIT(20) 199285431Szbb/** Uncorrectable Internal Error */ 200285431Szbb#define AL_PCIE_AER_UNCORR_INT_ERR AL_BIT(22) 201285431Szbb/** AtomicOp Egress Blocked */ 202285431Szbb#define AL_PCIE_AER_UNCORR_ATOMIC_EGRESS_BLK AL_BIT(24) 203285431Szbb 204285431Szbb/******************************************************************************* 205285431Szbb * PCIe AER correctable error bits 206285431Szbb * To be used with the following functions: 207285431Szbb * - al_pcie_aer_config 208285431Szbb * - al_pcie_aer_corr_get_and_clear 209285431Szbb ******************************************************************************/ 210285431Szbb/** Receiver Error */ 211285431Szbb#define AL_PCIE_AER_CORR_RCV_ERR AL_BIT(0) 212285431Szbb/** Bad TLP */ 213285431Szbb#define AL_PCIE_AER_CORR_BAD_TLP AL_BIT(6) 214285431Szbb/** Bad DLLP */ 215285431Szbb#define AL_PCIE_AER_CORR_BAD_DLLP AL_BIT(7) 216285431Szbb/** REPLAY_NUM Rollover */ 217285431Szbb#define AL_PCIE_AER_CORR_RPLY_NUM_ROLL_OVR AL_BIT(8) 218285431Szbb/** Replay Timer Timeout */ 219285431Szbb#define AL_PCIE_AER_CORR_RPLY_TMR_TO AL_BIT(12) 220285431Szbb/** Advisory Non-Fatal Error */ 221285431Szbb#define AL_PCIE_AER_CORR_ADVISORY_NON_FTL_ERR AL_BIT(13) 222285431Szbb/** Corrected Internal Error */ 223285431Szbb#define AL_PCIE_AER_CORR_INT_ERR AL_BIT(14) 224285431Szbb 225285431Szbb/** The AER erroneous TLP header length [num DWORDs] */ 226285431Szbb#define AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS 4 227285431Szbb 228285431Szbb/******************************************************************************/ 229285431Szbb/************************* Data Structures and Types **************************/ 230285431Szbb/******************************************************************************/ 231285431Szbb 232285431Szbb/** 233285431Szbb * al_pcie_ib_hcrd_config: data structure internally used in order to config 234285431Szbb * inbound posted/non-posted parameters. 235285431Szbb * Note: it's required to have this structure in pcie_port handle since it has 236285431Szbb * a state (required/not-required) which is determined by outbound 237285431Szbb * outstanding configuration 238285431Szbb */ 239285431Szbbstruct al_pcie_ib_hcrd_config { 240285431Szbb /* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */ 241285431Szbb unsigned int nof_np_hdr; 242285431Szbb 243285431Szbb /* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */ 244285431Szbb unsigned int nof_p_hdr; 245285431Szbb}; 246285431Szbb 247285431Szbb/* The Max Payload Size. Measured in bytes. 248285431Szbb * DEFAULT: do not change the current MPS 249285431Szbb */ 250285431Szbbenum al_pcie_max_payload_size { 251285431Szbb AL_PCIE_MPS_DEFAULT, 252285431Szbb AL_PCIE_MPS_128 = 0, 253285431Szbb AL_PCIE_MPS_256 = 1, 254285431Szbb AL_PCIE_MPS_512 = 2, 255285431Szbb AL_PCIE_MPS_1024 = 3, 256285431Szbb AL_PCIE_MPS_2048 = 4, 257285431Szbb AL_PCIE_MPS_4096 = 5, 258285431Szbb}; 259285431Szbb 260285431Szbb/** 261285431Szbb * al_pcie_port: data structure used by the HAL to handle a specific pcie port. 262285431Szbb * this structure is allocated and set to zeros by the upper layer, then it is 263285431Szbb * initialized by the al_pcie_port_handle_init() that should be called before any 264285431Szbb * other function of this API. later, this handle passed to the API functions. 265285431Szbb */ 266285431Szbbstruct al_pcie_port { 267285431Szbb void __iomem *pcie_reg_base; 268285431Szbb struct al_pcie_regs regs_ptrs; 269285431Szbb struct al_pcie_regs *regs; 270285431Szbb uint32_t *ex_regs_ptrs[AL_PCIE_EX_REGS_NUM]; 271285431Szbb void *ex_regs; 272285431Szbb void __iomem *pbs_regs; 273285431Szbb 274285431Szbb /* Revision ID */ 275285431Szbb uint8_t rev_id; 276285431Szbb unsigned int port_id; 277285431Szbb uint8_t max_lanes; 278285431Szbb uint8_t max_num_of_pfs; 279285431Szbb 280285431Szbb /* Internally used */ 281285431Szbb struct al_pcie_ib_hcrd_config ib_hcrd_config; 282285431Szbb}; 283285431Szbb 284285431Szbb/** 285285431Szbb * al_pcie_pf: the pf handle, a data structure used to handle PF specific 286285431Szbb * functionality. Initialized using "al_pcie_pf_handle_init()" 287285431Szbb */ 288285431Szbbstruct al_pcie_pf { 289285431Szbb unsigned int pf_num; 290285431Szbb struct al_pcie_port *pcie_port; 291285431Szbb}; 292285431Szbb 293285431Szbb/** Operating mode (endpoint, root complex) */ 294285431Szbbenum al_pcie_operating_mode { 295285431Szbb AL_PCIE_OPERATING_MODE_EP, 296285431Szbb AL_PCIE_OPERATING_MODE_RC, 297285431Szbb AL_PCIE_OPERATING_MODE_UNKNOWN 298285431Szbb}; 299285431Szbb 300285431Szbb/* The maximum link speed, measured GT/s (Giga transfer / second) 301285431Szbb * DEFAULT: do not change the current speed 302285431Szbb * GEN1: 2.5 GT/s 303285431Szbb * GEN2: 5 GT/s 304285431Szbb * GEN3: 8GT/s 305285431Szbb * 306285431Szbb * Note: The values of this enumerator are important for proper behavior 307285431Szbb */ 308285431Szbbenum al_pcie_link_speed { 309285431Szbb AL_PCIE_LINK_SPEED_DEFAULT, 310285431Szbb AL_PCIE_LINK_SPEED_GEN1 = 1, 311285431Szbb AL_PCIE_LINK_SPEED_GEN2 = 2, 312285431Szbb AL_PCIE_LINK_SPEED_GEN3 = 3 313285431Szbb}; 314285431Szbb 315285431Szbb/** PCIe capabilities that supported by a specific port */ 316285431Szbbstruct al_pcie_max_capability { 317285431Szbb al_bool end_point_mode_supported; 318285431Szbb al_bool root_complex_mode_supported; 319285431Szbb enum al_pcie_link_speed max_speed; 320285431Szbb uint8_t max_lanes; 321285431Szbb al_bool reversal_supported; 322285431Szbb uint8_t atu_regions_num; 323285431Szbb uint32_t atu_min_size; 324285431Szbb}; 325285431Szbb 326285431Szbb/** PCIe link related parameters */ 327285431Szbbstruct al_pcie_link_params { 328285431Szbb enum al_pcie_link_speed max_speed; 329285431Szbb al_bool enable_reversal; 330285431Szbb enum al_pcie_max_payload_size max_payload_size; 331285431Szbb 332285431Szbb}; 333285431Szbb 334285431Szbb/** PCIe gen2 link parameters */ 335285431Szbbstruct al_pcie_gen2_params { 336285431Szbb al_bool tx_swing_low; /* set tx swing low when true, and tx swing full when false */ 337285431Szbb al_bool tx_compliance_receive_enable; 338285431Szbb al_bool set_deemphasis; 339285431Szbb}; 340285431Szbb 341285431Szbb/** PCIe gen 3 standard per lane equalization parameters */ 342285431Szbbstruct al_pcie_gen3_lane_eq_params { 343285431Szbb uint8_t downstream_port_transmitter_preset; 344285431Szbb uint8_t downstream_port_receiver_preset_hint; 345285431Szbb uint8_t upstream_port_transmitter_preset; 346285431Szbb uint8_t upstream_port_receiver_preset_hint; 347285431Szbb}; 348285431Szbb 349285431Szbb/** PCIe gen 3 equalization parameters */ 350285431Szbbstruct al_pcie_gen3_params { 351285431Szbb al_bool perform_eq; 352285431Szbb al_bool interrupt_enable_on_link_eq_request; 353285431Szbb struct al_pcie_gen3_lane_eq_params *eq_params; /* array of lanes params */ 354285431Szbb int eq_params_elements; /* number of elements in the eq_params array */ 355285431Szbb 356285431Szbb al_bool eq_disable; /* disables the equalization feature */ 357285431Szbb al_bool eq_phase2_3_disable; /* Equalization Phase 2 and Phase 3 */ 358285431Szbb /* Disable (RC mode only) */ 359285431Szbb uint8_t local_lf; /* Full Swing (FS) Value for Gen3 Transmit Equalization */ 360285431Szbb /* Value Range: 12 through 63 (decimal).*/ 361285431Szbb 362285431Szbb uint8_t local_fs; /* Low Frequency (LF) Value for Gen3 Transmit Equalization */ 363285431Szbb}; 364285431Szbb 365285431Szbb/** Transport Layer credits parameters */ 366285431Szbbstruct al_pcie_tl_credits_params { 367285431Szbb}; 368285431Szbb 369285431Szbb/** Various configuration features */ 370285431Szbbstruct al_pcie_features { 371285431Szbb /** 372285431Szbb * Enable MSI fix from the SATA to the PCIe EP 373285431Szbb * Only valid for port 0, when enabled as EP 374285431Szbb */ 375285431Szbb al_bool sata_ep_msi_fix; 376285431Szbb}; 377285431Szbb 378285431Szbb/** 379285431Szbb * Inbound posted/non-posted header credits and outstanding outbound reads 380285431Szbb * completion header configuration 381285431Szbb * 382285431Szbb * Constraints: 383285431Szbb * - nof_cpl_hdr + nof_np_hdr + nof_p_hdr == 384285431Szbb * AL_PCIE_REV_1_2_IB_HCRD_SUM/AL_PCIE_REV3_IB_HCRD_SUM 385285431Szbb * - nof_cpl_hdr > 0 386285431Szbb * - nof_p_hdr > 0 387285431Szbb * - nof_np_hdr > 0 388285431Szbb */ 389285431Szbbstruct al_pcie_ib_hcrd_os_ob_reads_config { 390285431Szbb /** Max number of outstanding outbound reads */ 391285431Szbb uint8_t nof_outstanding_ob_reads; 392285431Szbb 393285431Szbb /** 394285431Szbb * This value set the possible outstanding headers CMPLs , the core 395285431Szbb * can get (the core always advertise infinite credits for CMPLs). 396285431Szbb */ 397285431Szbb unsigned int nof_cpl_hdr; 398285431Szbb 399285431Szbb /** 400285431Szbb * This value set the possible outstanding headers reads (non-posted 401285431Szbb * transactions), the core can get (it set the value in the init FC 402285431Szbb * process). 403285431Szbb */ 404285431Szbb unsigned int nof_np_hdr; 405285431Szbb 406285431Szbb /** 407285431Szbb * This value set the possible outstanding headers writes (posted 408285431Szbb * transactions), the core can get (it set the value in the init FC 409285431Szbb * process). 410285431Szbb */ 411285431Szbb unsigned int nof_p_hdr; 412285431Szbb}; 413285431Szbb 414285431Szbb/** PCIe Ack/Nak Latency and Replay timers */ 415285431Szbbstruct al_pcie_latency_replay_timers { 416285431Szbb uint16_t round_trip_lat_limit; 417285431Szbb uint16_t replay_timer_limit; 418285431Szbb}; 419285431Szbb 420285431Szbb/* SRIS KP counter values */ 421285431Szbbstruct al_pcie_sris_params { 422285431Szbb /** set to AL_TRUE to use defaults and ignore the other parameters */ 423285431Szbb al_bool use_defaults; 424285431Szbb uint16_t kp_counter_gen3; /* only for Gen3 */ 425285431Szbb uint16_t kp_counter_gen21; 426285431Szbb}; 427285431Szbb 428285431Szbb/** Relaxed ordering params */ 429285431Szbbstruct al_pcie_relaxed_ordering_params { 430285431Szbb al_bool enable_tx_relaxed_ordering; 431285431Szbb al_bool enable_rx_relaxed_ordering; 432285431Szbb}; 433285431Szbb 434285431Szbb/** PCIe port configuration parameters 435285431Szbb * This structure includes the parameters that the HAL should apply to the port 436285431Szbb * (by al_pcie_port_config()). 437285431Szbb * The fields that are pointers (e.g. link_params) can be set to NULL, in that 438285431Szbb * case, the al_pcie_port_config() will keep the current HW settings. 439285431Szbb */ 440285431Szbbstruct al_pcie_port_config_params { 441285431Szbb struct al_pcie_link_params *link_params; 442285431Szbb al_bool enable_axi_snoop; 443285431Szbb al_bool enable_ram_parity_int; 444285431Szbb al_bool enable_axi_parity_int; 445285431Szbb struct al_pcie_latency_replay_timers *lat_rply_timers; 446285431Szbb struct al_pcie_gen2_params *gen2_params; 447285431Szbb struct al_pcie_gen3_params *gen3_params; 448285431Szbb struct al_pcie_tl_credits_params *tl_credits; 449285431Szbb struct al_pcie_features *features; 450285431Szbb /* Sets all internal timers to Fast Mode for speeding up simulation.*/ 451285431Szbb al_bool fast_link_mode; 452285431Szbb /* 453285431Szbb * when true, the PCI unit will return Slave Error/Decoding Error to the master unit in case 454285431Szbb * of error. when false, the value 0xFFFFFFFF will be returned without error indication. 455285431Szbb */ 456285431Szbb al_bool enable_axi_slave_err_resp; 457285431Szbb struct al_pcie_sris_params *sris_params; 458285431Szbb struct al_pcie_relaxed_ordering_params *relaxed_ordering_params; 459285431Szbb}; 460285431Szbb 461285431Szbb/** BAR register configuration parameters (Endpoint Mode only) */ 462285431Szbbstruct al_pcie_ep_bar_params { 463285431Szbb al_bool enable; 464285431Szbb al_bool memory_space; /**< memory or io */ 465285431Szbb al_bool memory_64_bit; /**< is memory space is 64 bit */ 466285431Szbb al_bool memory_is_prefetchable; 467285431Szbb uint64_t size; /* the bar size in bytes */ 468285431Szbb}; 469285431Szbb 470285431Szbb/** PF config params (EP mode only) */ 471285431Szbbstruct al_pcie_pf_config_params { 472285431Szbb al_bool cap_d1_d3hot_dis; 473285431Szbb al_bool cap_flr_dis; 474285431Szbb al_bool cap_aspm_dis; 475285431Szbb al_bool bar_params_valid; 476285431Szbb struct al_pcie_ep_bar_params bar_params[6]; 477285431Szbb struct al_pcie_ep_bar_params exp_bar_params;/* expansion ROM BAR*/ 478285431Szbb}; 479285431Szbb 480285431Szbb/** PCIe link status */ 481285431Szbbstruct al_pcie_link_status { 482285431Szbb al_bool link_up; 483285431Szbb enum al_pcie_link_speed speed; 484285431Szbb uint8_t lanes; 485285431Szbb uint8_t ltssm_state; 486285431Szbb}; 487285431Szbb 488285431Szbb/** PCIe lane status */ 489285431Szbbstruct al_pcie_lane_status { 490285431Szbb al_bool is_reset; 491285431Szbb enum al_pcie_link_speed requested_speed; 492285431Szbb}; 493285431Szbb 494285431Szbb/** PCIe MSIX capability configuration parameters */ 495285431Szbbstruct al_pcie_msix_params { 496285431Szbb uint16_t table_size; 497285431Szbb uint16_t table_offset; 498285431Szbb uint8_t table_bar; 499285431Szbb uint16_t pba_offset; 500285431Szbb uint16_t pba_bar; 501285431Szbb}; 502285431Szbb 503285431Szbb/** PCIE AER capability parameters */ 504285431Szbbstruct al_pcie_aer_params { 505285431Szbb /** ECRC Generation Enable */ 506285431Szbb al_bool ecrc_gen_en; 507285431Szbb /** ECRC Check Enable */ 508285431Szbb al_bool ecrc_chk_en; 509285431Szbb 510285431Szbb /** 511285431Szbb * Enabled reporting of correctable errors (bit mask) 512285431Szbb * See 'AL_PCIE_AER_CORR_*' for details 513285431Szbb * 0 - no reporting at all 514285431Szbb */ 515285431Szbb unsigned int enabled_corr_err; 516285431Szbb /** 517285431Szbb * Enabled reporting of non-fatal uncorrectable errors (bit mask) 518285431Szbb * See 'AL_PCIE_AER_UNCORR_*' for details 519285431Szbb * 0 - no reporting at all 520285431Szbb */ 521285431Szbb unsigned int enabled_uncorr_non_fatal_err; 522285431Szbb /** 523285431Szbb * Enabled reporting of fatal uncorrectable errors (bit mask) 524285431Szbb * See 'AL_PCIE_AER_UNCORR_*' for details 525285431Szbb * 0 - no reporting at all 526285431Szbb */ 527285431Szbb unsigned int enabled_uncorr_fatal_err; 528285431Szbb}; 529285431Szbb 530285431Szbb/******************************************************************************/ 531285431Szbb/********************************** PCIe API **********************************/ 532285431Szbb/******************************************************************************/ 533285431Szbb 534285431Szbb/*************************** PCIe Initialization API **************************/ 535285431Szbb 536285431Szbb/** 537285431Szbb * Initializes a PCIe port handle structure. 538285431Szbb * 539285431Szbb * @param pcie_port an allocated, non-initialized instance. 540285431Szbb * @param pcie_reg_base the virtual base address of the port internal 541285431Szbb * registers 542285431Szbb * @param pbs_reg_base the virtual base address of the pbs functional 543285431Szbb * registers 544285431Szbb * @param port_id the port id (used mainly for debug messages) 545285431Szbb * 546285431Szbb * @return 0 if no error found. 547285431Szbb */ 548285431Szbbint al_pcie_port_handle_init(struct al_pcie_port *pcie_port, 549285431Szbb void __iomem *pcie_reg_base, 550285431Szbb void __iomem *pbs_reg_base, 551285431Szbb unsigned int port_id); 552285431Szbb 553285431Szbb/** 554285431Szbb * Initializes a PCIe pf handle structure 555285431Szbb * @param pcie_pf an allocated, non-initialized instance of pf handle 556285431Szbb * @param pcie_port pcie port handle 557285431Szbb * @param pf_num physical function number 558285431Szbb * @return 0 if no error found 559285431Szbb */ 560285431Szbbint al_pcie_pf_handle_init( 561285431Szbb struct al_pcie_pf *pcie_pf, 562285431Szbb struct al_pcie_port *pcie_port, 563285431Szbb unsigned int pf_num); 564285431Szbb 565285431Szbb/************************** Pre PCIe Port Enable API **************************/ 566285431Szbb 567285431Szbb/** 568285431Szbb * @brief set current pcie operating mode (root complex or endpoint) 569285431Szbb * This function can be called only before enabling the controller using 570285431Szbb * al_pcie_port_enable(). 571285431Szbb * 572285431Szbb * @param pcie_port pcie port handle 573285431Szbb * @param mode pcie operating mode 574285431Szbb * 575285431Szbb * @return 0 if no error found. 576285431Szbb */ 577285431Szbbint al_pcie_port_operating_mode_config(struct al_pcie_port *pcie_port, 578285431Szbb enum al_pcie_operating_mode mode); 579285431Szbb 580285431Szbb/** 581285431Szbb * Configure number of lanes connected to this port. 582285431Szbb * This function can be called only before enabling the controller using al_pcie_port_enable(). 583285431Szbb * 584285431Szbb * @param pcie_port pcie port handle 585285431Szbb * @param lanes number of lanes 586285431Szbb * Note: this function must be called before any al_pcie_port_config() calls 587285431Szbb * 588285431Szbb * @return 0 if no error found. 589285431Szbb */ 590285431Szbbint al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes); 591285431Szbb 592285431Szbb/** 593285431Szbb * Set maximum physical function numbers 594285431Szbb * @param pcie_port pcie port handle 595285431Szbb * @param max_num_of_pfs number of physical functions 596285431Szbb * Note: this function must be called before any al_pcie_pf_config() calls 597285431Szbb */ 598285431Szbbint al_pcie_port_max_num_of_pfs_set( 599285431Szbb struct al_pcie_port *pcie_port, 600285431Szbb uint8_t max_num_of_pfs); 601285431Szbb 602285431Szbb/** 603285431Szbb * @brief Inbound posted/non-posted header credits and outstanding outbound 604285431Szbb * reads completion header configuration 605285431Szbb * 606285431Szbb * @param pcie_port pcie port handle 607285431Szbb * @param ib_hcrd_os_ob_reads_config 608285431Szbb * Inbound header credits and outstanding outbound reads 609285431Szbb * configuration 610285431Szbb */ 611285431Szbbint al_pcie_port_ib_hcrd_os_ob_reads_config( 612285431Szbb struct al_pcie_port *pcie_port, 613285431Szbb struct al_pcie_ib_hcrd_os_ob_reads_config *ib_hcrd_os_ob_reads_config); 614285431Szbb 615285431Szbb/** return PCIe operating mode 616285431Szbb * @param pcie_port pcie port handle 617285431Szbb * @return operating mode 618285431Szbb */ 619285431Szbbenum al_pcie_operating_mode al_pcie_operating_mode_get( 620285431Szbb struct al_pcie_port *pcie_port); 621285431Szbb 622285431Szbb/**************************** PCIe Port Enable API ****************************/ 623285431Szbb 624285431Szbb/** Enable PCIe unit (deassert reset) 625285431Szbb * 626285431Szbb * @param pcie_port pcie port handle 627285431Szbb * 628285431Szbb * @return 0 if no error found. 629285431Szbb */ 630285431Szbbint al_pcie_port_enable(struct al_pcie_port *pcie_port); 631285431Szbb 632285431Szbb/** Disable PCIe unit (assert reset) 633285431Szbb * 634285431Szbb * @param pcie_port pcie port handle 635285431Szbb */ 636285431Szbbvoid al_pcie_port_disable(struct al_pcie_port *pcie_port); 637285431Szbb 638285431Szbb/** 639285431Szbb * Port memory shutdown/up 640285431Szbb * Caution: This function can be called only when the controller is disabled 641285431Szbb * 642285431Szbb * @param pcie_port pcie port handle 643285431Szbb * @param enable memory shutdown enable or disable 644285431Szbb * 645285431Szbb */ 646285431Szbbint al_pcie_port_memory_shutdown_set( 647285431Szbb struct al_pcie_port *pcie_port, 648285431Szbb al_bool enable); 649285431Szbb 650285431Szbb/** 651285431Szbb * Check if port enabled or not 652285431Szbb * @param pcie_port pcie port handle 653285431Szbb * @return AL_TRUE of port enabled and AL_FALSE otherwise 654285431Szbb */ 655285431Szbbal_bool al_pcie_port_is_enabled(struct al_pcie_port *pcie_port); 656285431Szbb 657285431Szbb/*************************** PCIe Configuration API ***************************/ 658285431Szbb 659285431Szbb/** 660285431Szbb * @brief configure pcie port (mode, link params, etc..) 661285431Szbb * this function must be called before initializing the link 662285431Szbb * 663285431Szbb * @param pcie_port pcie port handle 664285431Szbb * @param params configuration structure. 665285431Szbb * 666285431Szbb * @return 0 if no error found 667285431Szbb */ 668285431Szbbint al_pcie_port_config(struct al_pcie_port *pcie_port, 669285431Szbb const struct al_pcie_port_config_params *params); 670285431Szbb 671285431Szbb/** 672285431Szbb * @brief Configure a specific PF (EP params, sriov params, ...) 673285431Szbb * this function must be called before any datapath transactions 674285431Szbb * 675285431Szbb * @param pcie_pf pcie pf handle 676285431Szbb * @param params configuration structure. 677285431Szbb * 678285431Szbb * @return 0 if no error found 679285431Szbb */ 680285431Szbbint al_pcie_pf_config( 681285431Szbb struct al_pcie_pf *pcie_pf, 682285431Szbb const struct al_pcie_pf_config_params *params); 683285431Szbb 684285431Szbb/************************** PCIe Link Operations API **************************/ 685285431Szbb 686285431Szbb/** 687285431Szbb * @brief start pcie link 688285431Szbb * 689285431Szbb * @param pcie_port pcie port handle 690285431Szbb * 691285431Szbb * @return 0 if no error found 692285431Szbb */ 693285431Szbbint al_pcie_link_start(struct al_pcie_port *pcie_port); 694285431Szbb 695285431Szbb/** 696285431Szbb * @brief stop pcie link 697285431Szbb * 698285431Szbb * @param pcie_port pcie port handle 699285431Szbb * 700285431Szbb * @return 0 if no error found 701285431Szbb */ 702285431Szbbint al_pcie_link_stop(struct al_pcie_port *pcie_port); 703285431Szbb 704285431Szbb/** 705285431Szbb * @brief trigger link-disable 706285431Szbb * 707285431Szbb * @param pcie_port pcie port handle 708285431Szbb * @param disable AL_TRUE to disable the link and AL_FALSE to enable it 709285431Szbb * 710285431Szbb * Note: this functionality differs from "al_pcie_link_stop" as it's a spec 711285431Szbb * functionality where both sides of the PCIe agrees to disable the link 712285431Szbb * @return 0 if no error found 713285431Szbb */ 714285431Szbbint al_pcie_link_disable(struct al_pcie_port *pcie_port, al_bool disable); 715285431Szbb 716285431Szbb/** 717285431Szbb * @brief wait for link up indication 718285431Szbb * this function waits for link up indication, it polls LTSSM state until link is ready 719285431Szbb * 720285431Szbb * @param pcie_port pcie port handle 721285431Szbb * @param timeout_ms maximum timeout in milli-seconds to wait for link up 722285431Szbb * 723285431Szbb * @return 0 if link up indication detected 724285431Szbb * -ETIME if not. 725285431Szbb */ 726285431Szbbint al_pcie_link_up_wait(struct al_pcie_port *pcie_port, uint32_t timeout_ms); 727285431Szbb 728285431Szbb/** 729285431Szbb * @brief get link status 730285431Szbb * 731285431Szbb * @param pcie_port pcie port handle 732285431Szbb * @param status structure for link status 733285431Szbb * 734285431Szbb * @return 0 if no error found 735285431Szbb */ 736285431Szbbint al_pcie_link_status(struct al_pcie_port *pcie_port, struct al_pcie_link_status *status); 737285431Szbb 738285431Szbb/** 739285431Szbb * @brief get lane status 740285431Szbb * 741285431Szbb * @param pcie_port 742285431Szbb * pcie port handle 743285431Szbb * @param lane 744285431Szbb * PCIe lane 745285431Szbb * @param status 746285431Szbb * Pointer to returned structure for lane status 747285431Szbb * 748285431Szbb */ 749285431Szbbvoid al_pcie_lane_status_get( 750285431Szbb struct al_pcie_port *pcie_port, 751285431Szbb unsigned int lane, 752285431Szbb struct al_pcie_lane_status *status); 753285431Szbb 754285431Szbb/** 755285431Szbb * @brief trigger hot reset 756285431Szbb * 757285431Szbb * @param pcie_port pcie port handle 758285431Szbb * @param enable AL_TRUE to enable hot-reset and AL_FALSE to disable it 759285431Szbb * 760285431Szbb * @return 0 if no error found 761285431Szbb */ 762285431Szbbint al_pcie_link_hot_reset(struct al_pcie_port *pcie_port, al_bool enable); 763285431Szbb 764285431Szbb/** 765285431Szbb * @brief trigger link-retain 766285431Szbb * this function initiates Link retraining by directing the Physical Layer LTSSM 767285431Szbb * to the Recovery state. If the LTSSM is already in Recovery or Configuration, 768285431Szbb * re-entering Recovery is permitted but not required. 769285431Szbb 770285431Szbb * @param pcie_port pcie port handle 771285431Szbb * 772285431Szbb * Note: there's no need to disable initiating link-retrain 773285431Szbb * @return 0 if no error found 774285431Szbb */ 775285431Szbbint al_pcie_link_retrain(struct al_pcie_port *pcie_port); 776285431Szbb 777285431Szbb/** 778285431Szbb * @brief change port speed 779285431Szbb * this function changes the port speed, it doesn't wait for link re-establishment 780285431Szbb * 781285431Szbb * @param pcie_port pcie port handle 782285431Szbb * @param new_speed the new speed gen to set 783285431Szbb * 784285431Szbb * @return 0 if no error found 785285431Szbb */ 786285431Szbbint al_pcie_link_change_speed(struct al_pcie_port *pcie_port, enum al_pcie_link_speed new_speed); 787285431Szbb 788285431Szbb/* TODO: check if this function needed */ 789285431Szbbint al_pcie_link_change_width(struct al_pcie_port *pcie_port, uint8_t width); 790285431Szbb 791285431Szbb/**************************** Post Link Start API *****************************/ 792285431Szbb 793285431Szbb/************************** Snoop Configuration API ***************************/ 794285431Szbb 795285431Szbb/** 796285431Szbb * @brief configure pcie port axi snoop 797285431Szbb * 798285431Szbb * @param pcie_port pcie port handle 799285431Szbb * @param enable_axi_snoop enable snoop. 800285431Szbb * 801285431Szbb * @return 0 if no error found 802285431Szbb */ 803285431Szbb/* TODO: Can this API be called after port enable? */ 804285431Szbbint al_pcie_port_snoop_config(struct al_pcie_port *pcie_port, 805285431Szbb al_bool enable_axi_snoop); 806285431Szbb 807285431Szbb/************************** Configuration Space API ***************************/ 808285431Szbb 809285431Szbb/** 810285431Szbb * Configuration Space Access Through PCI-E_ECAM_Ext PASW (RC mode only) 811285431Szbb */ 812285431Szbb 813285431Szbb/** 814285431Szbb * @brief get base address of pci configuration space header 815285431Szbb * @param pcie_pf pcie pf handle 816285431Szbb * @param addr pointer for returned address; 817285431Szbb * @return 0 if no error found 818285431Szbb */ 819285431Szbbint al_pcie_config_space_get( 820285431Szbb struct al_pcie_pf *pcie_pf, 821285431Szbb uint8_t __iomem **addr); 822285431Szbb 823285431Szbb/** 824285431Szbb * Read data from the local configuration space 825285431Szbb * 826285431Szbb * @param pcie_pf pcie pf handle 827285431Szbb * @param reg_offset Configuration space register offset 828285431Szbb * @return Read data 829285431Szbb */ 830285431Szbbuint32_t al_pcie_local_cfg_space_read( 831285431Szbb struct al_pcie_pf *pcie_pf, 832285431Szbb unsigned int reg_offset); 833285431Szbb 834285431Szbb/** 835285431Szbb * Write data to the local configuration space 836285431Szbb * 837285431Szbb * @param pcie_pf PCIe pf handle 838285431Szbb * @param reg_offset Configuration space register offset 839285431Szbb * @param data Data to write 840285431Szbb * @param cs2 Should be AL_TRUE if dbi_cs2 must be asserted 841285431Szbb * to enable writing to this register, according to 842285431Szbb * the PCIe Core specifications 843285431Szbb * @param allow_ro_wr AL_TRUE to allow writing into read-only regs 844285431Szbb * 845285431Szbb */ 846285431Szbbvoid al_pcie_local_cfg_space_write( 847285431Szbb struct al_pcie_pf *pcie_pf, 848285431Szbb unsigned int reg_offset, 849285431Szbb uint32_t data, 850285431Szbb al_bool cs2, 851285431Szbb al_bool allow_ro_wr); 852285431Szbb 853285431Szbb/** 854285431Szbb * @brief set target_bus and mask_target_bus 855285431Szbb * @param pcie_port pcie port handle 856285431Szbb * @param target_bus 857285431Szbb * @param mask_target_bus 858285431Szbb * @return 0 if no error found 859285431Szbb */ 860285431Szbbint al_pcie_target_bus_set(struct al_pcie_port *pcie_port, 861285431Szbb uint8_t target_bus, 862285431Szbb uint8_t mask_target_bus); 863285431Szbb 864285431Szbb/** 865285431Szbb * @brief get target_bus and mask_target_bus 866285431Szbb * @param pcie_port pcie port handle 867285431Szbb * @param target_bus 868285431Szbb * @param mask_target_bus 869285431Szbb * @return 0 if no error found 870285431Szbb */ 871285431Szbbint al_pcie_target_bus_get(struct al_pcie_port *pcie_port, 872285431Szbb uint8_t *target_bus, 873285431Szbb uint8_t *mask_target_bus); 874285431Szbb 875285431Szbb/** 876285431Szbb * Set secondary bus number 877285431Szbb * 878285431Szbb * @param pcie_port pcie port handle 879285431Szbb * @param secbus pci secondary bus number 880285431Szbb * 881285431Szbb * @return 0 if no error found. 882285431Szbb */ 883285431Szbbint al_pcie_secondary_bus_set(struct al_pcie_port *pcie_port, uint8_t secbus); 884285431Szbb 885285431Szbb/** 886285431Szbb * Set subordinary bus number 887285431Szbb * 888285431Szbb * @param pcie_port pcie port handle 889285431Szbb * @param subbus the highest bus number of all of the buses that can be reached 890285431Szbb * downstream of the PCIE instance. 891285431Szbb * 892285431Szbb * @return 0 if no error found. 893285431Szbb */ 894285431Szbbint al_pcie_subordinary_bus_set(struct al_pcie_port *pcie_port,uint8_t subbus); 895285431Szbb 896285431Szbb/** 897285431Szbb * @brief Enable/disable deferring incoming configuration requests until 898285431Szbb * initialization is complete. When enabled, the core completes incoming 899285431Szbb * configuration requests with a Configuration Request Retry Status. 900285431Szbb * Other incoming Requests complete with Unsupported Request status. 901285431Szbb * 902285431Szbb * @param pcie_port pcie port handle 903285431Szbb * @param en enable/disable 904285431Szbb */ 905285431Szbbvoid al_pcie_app_req_retry_set(struct al_pcie_port *pcie_port, al_bool en); 906285431Szbb 907285431Szbb/*************** Internal Address Translation Unit (ATU) API ******************/ 908285431Szbb 909285431Szbbenum al_pcie_atu_dir { 910285431Szbb AL_PCIE_ATU_DIR_OUTBOUND = 0, 911285431Szbb AL_PCIE_ATU_DIR_INBOUND = 1, 912285431Szbb}; 913285431Szbb 914285431Szbbenum al_pcie_atu_tlp { 915285431Szbb AL_PCIE_TLP_TYPE_MEM = 0, 916285431Szbb AL_PCIE_TLP_TYPE_IO = 2, 917285431Szbb AL_PCIE_TLP_TYPE_CFG0 = 4, 918285431Szbb AL_PCIE_TLP_TYPE_CFG1 = 5, 919285431Szbb AL_PCIE_TLP_TYPE_MSG = 0x10, 920285431Szbb AL_PCIE_TLP_TYPE_RESERVED = 0x1f 921285431Szbb}; 922285431Szbb 923285431Szbbenum al_pcie_atu_response { 924285431Szbb AL_PCIE_RESPONSE_NORMAL = 0, 925285431Szbb AL_PCIE_RESPONSE_UR = 1, 926285431Szbb AL_PCIE_RESPONSE_CA = 2 927285431Szbb}; 928285431Szbb 929285431Szbbstruct al_pcie_atu_region { 930285431Szbb al_bool enable; 931285431Szbb /* outbound or inbound */ 932285431Szbb enum al_pcie_atu_dir direction; 933285431Szbb /* region index */ 934285431Szbb uint8_t index; 935285431Szbb uint64_t base_addr; 936285431Szbb /** limit marks the region's end address. only bits [39:0] are valid 937285431Szbb * given the Alpine PoC maximum physical address space 938285431Szbb */ 939285431Szbb uint64_t limit; 940285431Szbb /** the address that matches will be translated to this address + offset 941285431Szbb */ 942285431Szbb uint64_t target_addr; 943285431Szbb al_bool invert_matching; 944285431Szbb /* pcie tlp type*/ 945285431Szbb enum al_pcie_atu_tlp tlp_type; 946285431Szbb /* pcie frame header attr field*/ 947285431Szbb uint8_t attr; 948285431Szbb /** 949285431Szbb * outbound specific params 950285431Szbb */ 951285431Szbb /* pcie message code */ 952285431Szbb uint8_t msg_code; 953285431Szbb al_bool cfg_shift_mode; 954285431Szbb /** 955285431Szbb * inbound specific params 956285431Szbb */ 957285431Szbb uint8_t bar_number; 958285431Szbb /* BAR match mode, used in EP for MEM and IO tlps*/ 959285431Szbb uint8_t match_mode; 960285431Szbb /** 961285431Szbb * For outbound: enables taking the function number of the translated 962285431Szbb * TLP from the PCIe core. For inbound: enables ATU function match mode 963285431Szbb * Note: this boolean is ignored in RC mode 964285431Szbb */ 965285431Szbb al_bool function_match_bypass_mode; 966285431Szbb /** 967285431Szbb * The function number to match/bypass (see previous parameter) 968285431Szbb * Note: this parameter is ignored when previous param is FALSE 969285431Szbb */ 970285431Szbb uint8_t function_match_bypass_mode_number; 971285431Szbb /* response code */ 972285431Szbb enum al_pcie_atu_response response; 973285431Szbb al_bool enable_attr_match_mode; 974285431Szbb al_bool enable_msg_match_mode; 975285431Szbb /** 976285431Szbb * USE WITH CAUTION: setting this boolean to AL_TRUE allows setting the 977285431Szbb * outbound ATU even after link is already started. DO NOT SET this 978285431Szbb * boolean to AL_TRUE unless there have been NO traffic before calling 979285431Szbb * al_pcie_atu_region_set function 980285431Szbb */ 981285431Szbb al_bool enforce_ob_atu_region_set; 982285431Szbb}; 983285431Szbb 984285431Szbb/** 985285431Szbb * @brief program internal ATU region entry 986285431Szbb * @param pcie_port pcie port handle 987285431Szbb * @param atu_region data structure that contains the region index and the 988285431Szbb * translation parameters 989285431Szbb * @return 0 if no error 990285431Szbb */ 991285431Szbbint al_pcie_atu_region_set( 992285431Szbb struct al_pcie_port *pcie_port, 993285431Szbb struct al_pcie_atu_region *atu_region); 994285431Szbb 995285431Szbb/** 996285431Szbb * @brief get internal ATU is enabled and base/target addresses 997285431Szbb * @param pcie_port pcie port handle 998285431Szbb * @param direction input: iATU direction (IB/OB) 999285431Szbb * @param index input: iATU index 1000285431Szbb * @param enable output: AL_TRUE if the iATU is enabled 1001285431Szbb * @param base_addr output: the iATU base address 1002285431Szbb * @param target_addr output: the iATU target address 1003285431Szbb */ 1004285431Szbbvoid al_pcie_atu_region_get_fields( 1005285431Szbb struct al_pcie_port *pcie_port, 1006285431Szbb enum al_pcie_atu_dir direction, uint8_t index, 1007285431Szbb al_bool *enable, uint64_t *base_addr, uint64_t *target_addr); 1008285431Szbb 1009285431Szbb/** 1010285431Szbb * @brief Configure axi io bar. 1011285431Szbb * every hit to this bar will override size to 4 bytes. 1012285431Szbb * @param pcie_port pcie port handle 1013285431Szbb * @param start the first address of the memory 1014285431Szbb * @param end the last address of the memory 1015285431Szbb * @return 1016285431Szbb */ 1017285431Szbbvoid al_pcie_axi_io_config( 1018285431Szbb struct al_pcie_port *pcie_port, 1019285431Szbb al_phys_addr_t start, 1020285431Szbb al_phys_addr_t end); 1021285431Szbb 1022285431Szbb/************** Interrupt generation (Endpoint mode Only) API *****************/ 1023285431Szbb 1024285431Szbbenum al_pcie_legacy_int_type{ 1025285431Szbb AL_PCIE_LEGACY_INTA = 0, 1026285431Szbb AL_PCIE_LEGACY_INTB, 1027285431Szbb AL_PCIE_LEGACY_INTC, 1028285431Szbb AL_PCIE_LEGACY_INTD 1029285431Szbb}; 1030285431Szbb 1031285431Szbb/** 1032285431Szbb * @brief generate INTx Assert/DeAssert Message 1033285431Szbb * @param pcie_pf pcie pf handle 1034285431Szbb * @param assert when true, Assert Message is sent 1035285431Szbb * @param type type of message (INTA, INTB, etc) 1036285431Szbb * @return 0 if no error found 1037285431Szbb */ 1038285431Szbbint al_pcie_legacy_int_gen( 1039285431Szbb struct al_pcie_pf *pcie_pf, 1040285431Szbb al_bool assert, 1041285431Szbb enum al_pcie_legacy_int_type type); 1042285431Szbb 1043285431Szbb/** 1044285431Szbb * @brief generate MSI interrupt 1045285431Szbb * @param pcie_pf pcie pf handle 1046285431Szbb * @param vector the vector index to send interrupt for. 1047285431Szbb * @return 0 if no error found 1048285431Szbb */ 1049285431Szbbint al_pcie_msi_int_gen(struct al_pcie_pf *pcie_pf, uint8_t vector); 1050285431Szbb 1051285431Szbb/** 1052285431Szbb * @brief configure MSIX capability 1053285431Szbb * @param pcie_pf pcie pf handle 1054285431Szbb * @param msix_params MSIX capability configuration parameters 1055285431Szbb * @return 0 if no error found 1056285431Szbb */ 1057285431Szbbint al_pcie_msix_config( 1058285431Szbb struct al_pcie_pf *pcie_pf, 1059285431Szbb struct al_pcie_msix_params *msix_params); 1060285431Szbb 1061285431Szbb/** 1062285431Szbb * @brief check whether MSIX capability is enabled 1063285431Szbb * @param pcie_pf pcie pf handle 1064285431Szbb * @return AL_TRUE if MSIX capability is enabled, AL_FALSE otherwise 1065285431Szbb */ 1066285431Szbbal_bool al_pcie_msix_enabled(struct al_pcie_pf *pcie_pf); 1067285431Szbb 1068285431Szbb/** 1069285431Szbb * @brief check whether MSIX capability is masked 1070285431Szbb * @param pcie_pf pcie pf handle 1071285431Szbb * @return AL_TRUE if MSIX capability is masked, AL_FALSE otherwise 1072285431Szbb */ 1073285431Szbbal_bool al_pcie_msix_masked(struct al_pcie_pf *pcie_pf); 1074285431Szbb 1075285431Szbb/******************** Advanced Error Reporting (AER) API **********************/ 1076285431Szbb 1077285431Szbb/** 1078285431Szbb * @brief configure AER capability 1079285431Szbb * @param pcie_pf pcie pf handle 1080285431Szbb * @param params AER capability configuration parameters 1081285431Szbb * @return 0 if no error found 1082285431Szbb */ 1083285431Szbbint al_pcie_aer_config( 1084285431Szbb struct al_pcie_pf *pcie_pf, 1085285431Szbb struct al_pcie_aer_params *params); 1086285431Szbb 1087285431Szbb/** 1088285431Szbb * @brief AER uncorretable errors get and clear 1089285431Szbb * @param pcie_pf pcie pf handle 1090285431Szbb * @return bit mask of uncorrectable errors - see 'AL_PCIE_AER_UNCORR_*' for 1091285431Szbb * details 1092285431Szbb */ 1093285431Szbbunsigned int al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf *pcie_pf); 1094285431Szbb 1095285431Szbb/** 1096285431Szbb * @brief AER corretable errors get and clear 1097285431Szbb * @param pcie_pf pcie pf handle 1098285431Szbb * @return bit mask of correctable errors - see 'AL_PCIE_AER_CORR_*' for 1099285431Szbb * details 1100285431Szbb */ 1101285431Szbbunsigned int al_pcie_aer_corr_get_and_clear(struct al_pcie_pf *pcie_pf); 1102285431Szbb 1103285431Szbb/** 1104285431Szbb * @brief AER get the header for the TLP corresponding to a detected error 1105285431Szbb * @param pcie_pf pcie pf handle 1106285431Szbb * @param hdr pointer to an array for getting the header 1107285431Szbb */ 1108285431Szbbvoid al_pcie_aer_err_tlp_hdr_get( 1109285431Szbb struct al_pcie_pf *pcie_pf, 1110285431Szbb uint32_t hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS]); 1111285431Szbb 1112285431Szbb/******************** Loop-Back mode (RC and Endpoint modes) ******************/ 1113285431Szbb 1114285431Szbb/** 1115285431Szbb * @brief enter local pipe loop-back mode 1116285431Szbb * This mode will connect the pipe RX signals to TX. 1117285431Szbb * no need to start link when using this mode. 1118285431Szbb * Gen3 equalization must be disabled before enabling this mode 1119285431Szbb * The caller must make sure the port is ready to accept the TLPs it sends to 1120285431Szbb * itself. for example, BARs should be initialized before sending memory TLPs. 1121285431Szbb * 1122285431Szbb * @param pcie_port pcie port handle 1123285431Szbb * @return 0 if no error found 1124285431Szbb */ 1125285431Szbbint al_pcie_local_pipe_loopback_enter(struct al_pcie_port *pcie_port); 1126285431Szbb 1127285431Szbb/** 1128285431Szbb * @brief exit local pipe loopback mode 1129285431Szbb * 1130285431Szbb * @param pcie_port pcie port handle 1131285431Szbb * @return 0 if no error found 1132285431Szbb */ 1133285431Szbbint al_pcie_local_pipe_loopback_exit(struct al_pcie_port *pcie_port); 1134285431Szbb 1135285431Szbb/** 1136285431Szbb * @brief enter master remote loopback mode 1137285431Szbb * No need to configure the link partner to enter slave remote loopback mode 1138285431Szbb * as this should be done as response to special training sequence directives 1139285431Szbb * when master works in remote loopback mode. 1140285431Szbb * The caller must make sure the port is ready to accept the TLPs it sends to 1141285431Szbb * itself. for example, BARs should be initialized before sending memory TLPs. 1142285431Szbb * 1143285431Szbb * @param pcie_port pcie port handle 1144285431Szbb * @return 0 if no error found 1145285431Szbb */ 1146285431Szbbint al_pcie_remote_loopback_enter(struct al_pcie_port *pcie_port); 1147285431Szbb 1148285431Szbb/** 1149285431Szbb * @brief exit remote loopback mode 1150285431Szbb * 1151285431Szbb * @param pcie_port pcie port handle 1152285431Szbb * @return 0 if no error found 1153285431Szbb */ 1154285431Szbbint al_pcie_remote_loopback_exit(struct al_pcie_port *pcie_port); 1155285431Szbb 1156285431Szbb#endif 1157285431Szbb/** @} end of grouppcie group */ 1158