Lines Matching refs:lane
4389 * In Valleyview PLL and program lane counter registers are exposed
4438 /* Now program lane control registers */
5348 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5365 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5382 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5423 int target_clock, pixel_multiplier, lane, link_bw;
5442 lane = 0;
5446 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5452 * Hence the bw of each lane in terms of the mode signal
5466 if (!lane)
5467 lane = ironlake_get_lanes_required(target_clock, link_bw,
5470 intel_crtc->fdi_lanes = lane;
5474 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,