Searched refs:Reg1 (Results 1 - 25 of 30) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp371 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); variable
388 Reg1 = getXRegFromWReg(Reg1);
391 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
394 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
397 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
400 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
403 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
407 Reg1 = getDRegFromBReg(Reg1);
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
H A DMipsAsmPrinter.cpp791 unsigned Opcode, unsigned Reg1,
800 unsigned Temp = Reg1;
801 Reg1 = Reg2;
805 I.addOperand(MCOperand::createReg(Reg1));
811 unsigned Opcode, unsigned Reg1,
815 I.addOperand(MCOperand::createReg(Reg1));
822 unsigned MovOpc, unsigned Reg1,
826 unsigned temp = Reg1;
827 Reg1 = Reg2;
830 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg
790 EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2) argument
810 EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) argument
821 EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) argument
[all...]
H A DMips16InstrInfo.h117 unsigned Reg1, unsigned Reg2) const;
H A DMips16InstrInfo.cpp265 unsigned Reg1, unsigned Reg2) const {
274 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
278 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
279 MIB3.addReg(Reg1);
283 MIB4.addReg(Reg1, RegState::Kill);
262 adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Reg1, unsigned Reg2) const argument
H A DMipsSEFrameLowering.cpp442 unsigned Reg1 = local
446 std::swap(Reg0, Reg1);
454 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
459 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; local
462 std::swap(Reg0, Reg1);
470 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
/freebsd-11.0-release/contrib/llvm/include/llvm/MC/
H A DMCRegisterInfo.h76 bool contains(unsigned Reg1, unsigned Reg2) const { argument
77 return contains(Reg1) && contains(Reg2);
600 uint16_t Reg1; member in class:llvm::MCRegUnitRootIterator
602 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
606 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
622 Reg0 = Reg1;
623 Reg1 = 0;
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/
H A DX86InstrBuilder.h116 unsigned Reg1, bool isKill1,
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
115 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp750 unsigned Reg1 = CSI[idx].getReg(); local
772 if (AArch64::GPR64RegClass.contains(Reg1)) {
780 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
790 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", "
802 MBB.addLiveIn(Reg1);
805 .addReg(Reg1, getPrologueDeath(MF, Reg1))
827 unsigned Reg1 = CSI[i].getReg(); local
845 if (AArch64::GPR64RegClass.contains(Reg1)) {
852 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
[all...]
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h98 // Union Reg1's and Reg2's groups to form a new group.
100 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
H A DTargetInstrInfo.cpp140 unsigned Reg1 = MI->getOperand(Idx1).getReg(); local
153 if (HasDef && Reg0 == Reg1 &&
161 Reg0 = Reg1;
175 MI->getOperand(Idx2).setReg(Reg1);
H A DAggressiveAntiDepBreaker.cpp79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) argument
85 unsigned Group1 = GetGroup(Reg1);
H A DRegisterCoalescer.cpp1897 unsigned Reg1; local
1898 std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
1904 return Orig0->def == Orig1->def && Reg0 == Reg1;
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp227 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); local
251 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
266 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp89 unsigned Reg1, unsigned Reg2);
469 unsigned Reg1, unsigned Reg2) {
475 .addReg(Reg1)
466 createRegSequence(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg1, unsigned Reg2) argument
H A DThumb2SizeReduction.cpp659 unsigned Reg1 = MI->getOperand(1).getReg(); local
664 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
670 if (Reg1 != Reg0)
677 } else if (Reg0 != Reg1) {
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp488 unsigned Reg1 = Reg; local
493 .addReg(Reg1, RegState::Kill)
533 unsigned Reg1 = Reg; local
539 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
577 unsigned Reg1 = Reg; local
582 .addReg(Reg1, RegState::Kill)
H A DPPCVSXSwapRemoval.cpp835 unsigned Reg1 = MI->getOperand(1).getReg(); local
838 MI->getOperand(2).setReg(Reg1);
H A DPPCInstrInfo.cpp349 unsigned Reg1 = MI->getOperand(1).getReg(); local
358 if (Reg0 == Reg1) {
383 .addReg(Reg1, getKillRegState(Reg1IsKill))
392 MI->getOperand(2).setReg(Reg1);
/freebsd-11.0-release/contrib/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h100 bool contains(unsigned Reg1, unsigned Reg2) const { argument
101 return MC->contains(Reg1, Reg2);
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp1461 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1465 printRegName(O, Reg1);
1474 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1478 printRegName(O, Reg1);
1529 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1533 printRegName(O, Reg1);
1576 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1580 printRegName(O, Reg1);
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1617 StringRef Reg1(R1);
1618 MO.setReg(MatchRegisterName(Reg1));
1632 StringRef Reg1(R1);
1633 MO.setReg(MatchRegisterName(Reg1));
1648 StringRef Reg1(R1);
1649 MO.setReg(MatchRegisterName(Reg1));
1969 StringRef Reg1(R1);
1970 Rss.setReg(MatchRegisterName(Reg1));
2119 StringRef Reg1(R1);
2120 Rss.setReg(MatchRegisterName(Reg1));
[all...]
/freebsd-11.0-release/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1122 for (const auto &Reg1 : Registers) {
1124 if (TopoSigs.test(Reg1.getTopoSig()))
1126 TopoSigs.set(Reg1.getTopoSig());
1128 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
1134 if (&Reg1 == Reg2)
1145 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
1146 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3);
/freebsd-11.0-release/contrib/llvm/lib/MC/
H A DMCDwarf.cpp1038 unsigned Reg1 = Instr.getRegister(); local
1041 Reg1 = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg1, true), false);
1045 Streamer.EmitULEB128IntValue(Reg1);
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1453 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, argument
1455 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, Instructions);
1477 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, argument
1482 tmpInst.addOperand(MCOperand::createReg(Reg1));
1488 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, argument
1490 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc,
1494 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, argument
1496 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc,

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