Lines Matching refs:Reg1
750 unsigned Reg1 = CSI[idx].getReg();
772 if (AArch64::GPR64RegClass.contains(Reg1)) {
780 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
790 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", "
802 MBB.addLiveIn(Reg1);
805 .addReg(Reg1, getPrologueDeath(MF, Reg1))
827 unsigned Reg1 = CSI[i].getReg();
845 if (AArch64::GPR64RegClass.contains(Reg1)) {
852 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
861 DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", "
875 .addReg(Reg1, getDefRegState(true))