Searched refs:Pred1 (Results 1 - 16 of 16) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/Transforms/Utils/
H A DBasicBlockUtils.cpp796 BasicBlock *Pred1 = nullptr; local
802 Pred1 = SomePHI->getIncomingBlock(0);
808 Pred1 = *PI++;
818 BranchInst *Pred1Br = dyn_cast<BranchInst>(Pred1->getTerminator());
833 std::swap(Pred1, Pred2);
848 IfTrue = Pred1;
853 IfFalse = Pred1;
866 BasicBlock *CommonPred = Pred1->getSinglePredecessor();
875 if (BI->getSuccessor(0) == Pred1) {
876 IfTrue = Pred1;
[all...]
H A DSimplifyCFG.cpp1251 BasicBlock *Pred1 = *PI++;
1254 BasicBlock *BB2 = (Pred0 == BB1) ? Pred1 : Pred0;
/freebsd-11.0-release/contrib/llvm/lib/Transforms/Scalar/
H A DMergedLoadStoreMotion.cpp517 BasicBlock *Pred1 = *PI; local
520 if (Pred0 == Pred1)
526 int Size1 = Pred1->size();
545 if (StoreInst *S1 = canSinkFromBlock(Pred1, S0)) {
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h126 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
H A DR600InstrInfo.h193 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
H A DAMDGPUInstrInfo.cpp233 bool AMDGPUInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, argument
H A DR600InstrInfo.cpp997 R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, argument
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h240 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
H A DPPCInstrInfo.cpp1416 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, argument
1418 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1421 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1427 if (Pred1[1].getReg() != Pred2[1].getReg())
1430 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
/freebsd-11.0-release/contrib/llvm/lib/Analysis/
H A DInstructionSimplify.cpp1507 ICmpInst::Predicate Pred0, Pred1; local
1518 if (!match(Op1, m_ICmp(Pred1, m_Specific(V), m_Specific(CI1))))
1532 if (Pred0 == ICmpInst::ICMP_ULT && Pred1 == ICmpInst::ICMP_SGT)
1534 if (Pred0 == ICmpInst::ICMP_SLT && Pred1 == ICmpInst::ICMP_SGT && isNSW)
1538 if (Pred0 == ICmpInst::ICMP_ULE && Pred1 == ICmpInst::ICMP_SGT)
1540 if (Pred0 == ICmpInst::ICMP_SLE && Pred1 == ICmpInst::ICMP_SGT && isNSW)
1546 if (Pred0 == ICmpInst::ICMP_ULT && Pred1 == ICmpInst::ICMP_UGT)
1549 if (Pred0 == ICmpInst::ICMP_ULE && Pred1 == ICmpInst::ICMP_UGT)
1666 ICmpInst::Predicate Pred0, Pred1; local
1677 if (!match(Op1, m_ICmp(Pred1, m_Specifi
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h195 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
H A DHexagonInstrInfo.cpp1096 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, argument
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h149 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
H A DARMBaseInstrInfo.cpp478 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, argument
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
/freebsd-11.0-release/contrib/llvm/include/llvm/Target/
H A DTargetInstrInfo.h1032 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, argument
/freebsd-11.0-release/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp844 ICmpInst::Predicate Pred1 = (Inverted ? Cmp1->getInversePredicate() :
855 Pred1 = ICmpInst::getSwappedPredicate(Pred1);
862 switch (Pred1) {

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