/freebsd-11-stable/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/ |
H A D | tst.signedkeyspos.d | 98 @i64["cat", (long long)-2] = sum(-2); 99 @i64["bear", (long long)-2] = sum(-22); 100 @i64["dog", (long long)-2] = sum(-222); 101 @i64["cat", (long long)-1] = sum(-1); 102 @i64["bear", (long long)-1] = sum(-11); 103 @i64["dog", (long long)-1] = sum(-111); 104 @i64["cat", (long long)0] = sum(0); 105 @i64["bear", (long long)0] = sum(10); 106 @i64["dog", (long long)0] = sum(100); 107 @i64["ca [all...] |
H A D | tst.signedkeys.d | 113 @i64[(long long)-2] = sum(-2); 114 @i64[(long long)-1] = sum(-1); 115 @i64[(long long)0] = sum(0); 116 @i64[(long long)1] = sum(1); 117 @i64[(long long)2] = sum(2);
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/freebsd-11-stable/crypto/heimdal/lib/roken/ |
H A D | gettimeofday.c | 52 ull -= 116444736000000000i64; 53 ull /= 10i64; /* ull is now in microseconds */ 55 tp->tv_usec = (ull % 1000000i64); 56 tp->tv_sec = (ull / 1000000i64);
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/freebsd-11-stable/stand/ficl/ |
H A D | math64.h | 58 void i64Push(FICL_STACK *pStack, DPINT i64); 75 #define i64Extend(i64) (i64).hi = ((i64).lo < 0) ? -1L : 0 76 #define m64CastIU(i64) (*(DPUNS *)(&(i64)))
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/freebsd-11-stable/secure/lib/libcrypto/arm/ |
H A D | sha512-armv4.S | 463 vadd.i64 d16,d30 @ h+=Maj from the past 478 vadd.i64 d27,d29,d23 481 vadd.i64 d27,d26 483 vadd.i64 d28,d0 488 vadd.i64 d27,d28 491 vadd.i64 d19,d27 492 vadd.i64 d30,d27 493 @ vadd.i64 d23,d30 500 vadd.i64 d23,d30 @ h+=Maj from the past 515 vadd.i64 d2 [all...] |
H A D | ghash-armv4.S | 327 vshl.i64 d17,#57 332 vshl.i64 q3,q3,#1 347 vmov.i64 d29,#0x0000ffffffffffff 349 vmov.i64 d30,#0x00000000ffffffff 353 vmov.i64 d31,#0x000000000000ffff 365 vmov.i64 d29,#0x0000ffffffffffff 367 vmov.i64 d30,#0x00000000ffffffff 371 vmov.i64 d31,#0x000000000000ffff 409 vmov.i64 d23, #0 447 vmov.i64 d2 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFSelectionDAGInfo.cpp | 38 DAG.getConstant(CopyLen, dl, MVT::i64), 39 DAG.getConstant(Align, dl, MVT::i64));
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H A D | BPFISelLowering.cpp | 62 addRegisterClass(MVT::i64, &BPF::GPRRegClass); 71 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 76 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 78 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 82 for (auto VT : { MVT::i32, MVT::i64 }) { 112 setOperationAction(ISD::CTTZ, MVT::i64, Custom); 113 setOperationAction(ISD::CTLZ, MVT::i64, Custom); 114 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); 115 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 238 case MVT::i64 [all...] |
H A D | BPFISelDAGToDAG.cpp | 104 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64); 105 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64); 121 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64); 125 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); 131 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64); 149 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64); 153 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); 217 SDValue R6Reg = CurDAG->getRegister(BPF::R6, MVT::i64);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SelectionDAGInfo.cpp | 72 Ptr = DAG.getTargetFrameIndex(FI, MVT::i64); 75 TagSrc = DAG.getRegister(AArch64::SP, MVT::i64); 131 {MVT::i64, MVT::Other}, 132 {Addr, Addr, DAG.getTargetConstant(1, dl, MVT::i64), Chain}); 139 const EVT ResTys[] = {MVT::i64, MVT::i64, MVT::Other}; 140 SDValue Ops[] = {DAG.getConstant(ObjSize, dl, MVT::i64), Addr, Chain};
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H A D | AArch64ISelDAGToDAG.cpp | 318 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64); 502 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); 514 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); 595 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64); 632 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64); 762 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64); 782 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64); 797 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64); 808 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64); 823 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64); [all...] |
H A D | AArch64FastISel.cpp | 340 case MVT::i64: // fall-through 357 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i64 && 381 if (VT > MVT::i64) 388 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass 390 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; 535 assert(VT == MVT::i64 && "Expected 64-bit pointers"); 1071 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(), 1076 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(), 1082 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), 1086 ResultReg = emitLSL_ri(MVT::i64, MV [all...] |
H A D | AArch64ISelLowering.cpp | 136 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); 207 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 208 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 210 setOperationAction(ISD::SETCC, MVT::i64, Custom); 221 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); 224 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 229 setOperationAction(ISD::SELECT, MVT::i64, Custom); 234 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 239 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 241 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custo [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 120 clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), 127 "Only i64 comparisons with zext result."), 132 "Only i64 comparisons with sext result."))); 178 /// i64. 180 return CurDAG->getTargetConstant(Imm, dl, MVT::i64); 496 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 590 // Don't even go down this path for i64, since different logic will be 657 case MVT::i64: { 699 case MVT::i64 [all...] |
H A D | PPCFastISel.cpp | 446 IndexReg = PPCMaterializeInt(Offset, MVT::i64); 473 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass : 494 case MVT::i64: 645 case MVT::i64: 844 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || 925 case MVT::i64: 1012 // Move an i32 or i64 value in a GPR to an f64 value in an FPR. 1025 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) 1036 if (!PPCEmitStore(MVT::i64, SrcReg, Addr)) 1081 SrcVT != MVT::i32 && SrcVT != MVT::i64) [all...] |
/freebsd-11-stable/crypto/openssl/crypto/modes/asm/ |
H A D | ghash-armv4.pl | 359 vmov.i64 $t3#hi, #0 384 vshl.i64 $t0#hi,#57 389 vshl.i64 $IN,$IN,#1 404 vmov.i64 $k48,#0x0000ffffffffffff 406 vmov.i64 $k32,#0x00000000ffffffff 410 vmov.i64 $k16,#0x000000000000ffff 422 vmov.i64 $k48,#0x0000ffffffffffff 424 vmov.i64 $k32,#0x00000000ffffffff 428 vmov.i64 $k16,#0x000000000000ffff 453 vshl.i64 [all...] |
/freebsd-11-stable/crypto/openssl/crypto/modes/ |
H A D | modes_lcl.h | 11 typedef __int64 i64; typedef 15 typedef long i64; typedef 19 typedef long long i64; typedef
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 111 addRegisterClass(MVT::i64, &VE::I64RegClass); 136 return MVT::i64;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 748 MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32; 774 Mips::ZERO_64, MVT::i64); 810 DL, MVT::i64); 816 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); 819 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 820 CurDAG->getRegister(Mips::ZERO_64, MVT::i64), 826 MVT::i64); 827 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 895 if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64) 916 if (ResTy != MVT::i32 && ResTy != MVT::i64) [all...] |
/freebsd-11-stable/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-armv4.pl | 482 vadd.i64 $a,$Maj @ h+=Maj from the past 499 vadd.i64 $T1,$Ch,$h 502 vadd.i64 $T1,$t2 504 vadd.i64 $K,@X[$i%16] 509 vadd.i64 $T1,$K 512 vadd.i64 $d,$T1 513 vadd.i64 $Maj,$T1 514 @ vadd.i64 $h,$Maj 532 vadd.i64 @_[0],d30 @ h+=Maj from the past 541 vadd.i64 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVSubtarget.cpp | 41 XLenVT = MVT::i64;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 119 if (LocVT == MVT::i64 && Offset < 6*8) 167 LocVT = MVT::i64; 340 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, 346 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); 347 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); 443 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 499 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 597 // All integer register arguments are promoted by the caller to i64. 672 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 1072 // Full register, just bitconvert into i64 [all...] |
/freebsd-11-stable/contrib/netbsd-tests/include/ |
H A D | t_inttypes.c | 43 int64_t i64 = 0; local 77 PRINT(PRId64, i64); 92 PRINT(PRIi64, i64); 168 SCAN(SCNd64, i64); 183 SCAN(SCNi64, i64);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 94 setOperationAction(ISD::LOAD, MVT::i64, Promote); 95 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32); 109 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); 110 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand); 111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); 115 if (VT == MVT::i64) 194 setOperationAction(ISD::STORE, MVT::i64, Promote); 195 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32); 206 setTruncStoreAction(MVT::i64, MVT::i1, Expand); 207 setTruncStoreAction(MVT::i64, MV [all...] |
/freebsd-11-stable/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/typedef/ |
H A D | tst.TypedefDataAssign.d | 87 new_int64 i64;
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