1326938Sdim//===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2326938Sdim//
3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4353358Sdim// See https://llvm.org/LICENSE.txt for license information.
5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6326938Sdim//
7326938Sdim//===----------------------------------------------------------------------===//
8326938Sdim//
9326938Sdim// This file implements the RISCV specific subclass of TargetSubtargetInfo.
10326938Sdim//
11326938Sdim//===----------------------------------------------------------------------===//
12326938Sdim
13326938Sdim#include "RISCVSubtarget.h"
14326938Sdim#include "RISCV.h"
15360784Sdim#include "RISCVCallLowering.h"
16326938Sdim#include "RISCVFrameLowering.h"
17360784Sdim#include "RISCVLegalizerInfo.h"
18360784Sdim#include "RISCVRegisterBankInfo.h"
19360784Sdim#include "RISCVTargetMachine.h"
20326938Sdim#include "llvm/Support/TargetRegistry.h"
21326938Sdim
22326938Sdimusing namespace llvm;
23326938Sdim
24326938Sdim#define DEBUG_TYPE "riscv-subtarget"
25326938Sdim
26326938Sdim#define GET_SUBTARGETINFO_TARGET_DESC
27326938Sdim#define GET_SUBTARGETINFO_CTOR
28326938Sdim#include "RISCVGenSubtargetInfo.inc"
29326938Sdim
30326938Sdimvoid RISCVSubtarget::anchor() {}
31326938Sdim
32353358SdimRISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
33353358Sdim    const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
34326938Sdim  // Determine default and user-specified characteristics
35353358Sdim  bool Is64Bit = TT.isArch64Bit();
36326938Sdim  std::string CPUName = CPU;
37326938Sdim  if (CPUName.empty())
38326938Sdim    CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
39326938Sdim  ParseSubtargetFeatures(CPUName, FS);
40326938Sdim  if (Is64Bit) {
41326938Sdim    XLenVT = MVT::i64;
42326938Sdim    XLen = 64;
43326938Sdim  }
44353358Sdim
45353358Sdim  TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
46353358Sdim  RISCVFeatures::validate(TT, getFeatureBits());
47326938Sdim  return *this;
48326938Sdim}
49326938Sdim
50353358SdimRISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
51353358Sdim                               StringRef ABIName, const TargetMachine &TM)
52326938Sdim    : RISCVGenSubtargetInfo(TT, CPU, FS),
53360784Sdim      UserReservedRegister(RISCV::NUM_TARGET_REGS),
54353358Sdim      FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
55360784Sdim      InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
56360784Sdim  CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
57360784Sdim  Legalizer.reset(new RISCVLegalizerInfo(*this));
58360784Sdim
59360784Sdim  auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
60360784Sdim  RegBankInfo.reset(RBI);
61360784Sdim  InstSelector.reset(createRISCVInstructionSelector(
62360784Sdim      *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
63360784Sdim}
64360784Sdim
65360784Sdimconst CallLowering *RISCVSubtarget::getCallLowering() const {
66360784Sdim  return CallLoweringInfo.get();
67360784Sdim}
68360784Sdim
69360784SdimInstructionSelector *RISCVSubtarget::getInstructionSelector() const {
70360784Sdim  return InstSelector.get();
71360784Sdim}
72360784Sdim
73360784Sdimconst LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
74360784Sdim  return Legalizer.get();
75360784Sdim}
76360784Sdim
77360784Sdimconst RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
78360784Sdim  return RegBankInfo.get();
79360784Sdim}
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