Lines Matching refs:i64
94 setOperationAction(ISD::LOAD, MVT::i64, Promote);
95 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
109 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
110 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
115 if (VT == MVT::i64)
194 setOperationAction(ISD::STORE, MVT::i64, Promote);
195 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
206 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
207 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
208 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
209 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
238 setOperationAction(ISD::Constant, MVT::i64, Legal);
305 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
334 setOperationAction(ISD::ROTL, MVT::i64, Expand);
335 setOperationAction(ISD::ROTR, MVT::i64, Expand);
337 setOperationAction(ISD::MUL, MVT::i64, Expand);
338 setOperationAction(ISD::MULHU, MVT::i64, Expand);
339 setOperationAction(ISD::MULHS, MVT::i64, Expand);
340 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
341 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
342 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
343 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
344 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
351 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
352 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
353 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
811 return Dest == MVT::i32 ||Dest == MVT::i64 ;
813 return Src == MVT::i32 && Dest == MVT::i64;
1641 assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64");
1666 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1667 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1671 if (isTypeLegal(MVT::i64)) {
1812 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1843 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1853 if (VT == MVT::i64) {
1979 if (VT == MVT::i64 &&
2104 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2106 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2108 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
2110 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2111 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2112 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2122 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2123 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2201 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2217 MVT::i64);
2219 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2220 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2222 MVT::i64),
2225 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2227 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2230 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2231 D, DAG.getConstant(0, SL, MVT::i64));
2232 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2234 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2380 // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
2383 // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
2393 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
2423 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2424 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
2426 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
2427 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
2435 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
2436 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2445 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2446 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2447 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
2449 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2450 DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
2452 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2453 U, DAG.getConstant(40, SL, MVT::i64));
2459 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
2521 assert(SrcVT == MVT::i64 && "operation should be legal");
2558 assert(SrcVT == MVT::i64 && "operation should be legal");
2607 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2631 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2632 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2633 DAG.getConstant(32, DL, MVT::i64));
2637 DAG.getConstant(20, DL, MVT::i64));
2721 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2726 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2744 DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2749 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
3042 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3079 if (VT != MVT::i64)
3091 if (VT != MVT::i64)
3094 // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
3110 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3115 if (N->getValueType(0) != MVT::i64)
3126 // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
3133 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3136 // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
3142 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3174 if (VT != MVT::i64)
3180 // srl i64:x, C for C >= 32
3194 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
3245 // i16 (trunc (srl i64:x, K)), K <= 16 ->
3282 // We need to specifically handle i64 mul here to avoid unnecessary conversion
3283 // instructions. If we only match on the legalized i64 mul expansion,
3302 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64,
3944 // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
3948 if (Src.getValueType() == MVT::i64) {