Searched refs:crtc_offset (Results 1 - 16 of 16) sorted by relevance

/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_cursor.c44 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
49 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
51 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
56 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
58 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
63 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
73 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
77 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
101 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
106 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
[all...]
H A Dradeon_display.c47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
69 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
80 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset,
[all...]
H A Datombios_crtc.c1209 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1211 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1213 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1215 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1217 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1218 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1220 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1221 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1222 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1223 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset,
[all...]
H A Dradeon_legacy_crtc.c44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
383 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; local
520 crtc_offset = (u32)base;
522 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
530 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
531 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
532 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitc
[all...]
H A Drs600.c133 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
138 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
141 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
143 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
148 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
156 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
159 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
267 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
269 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
285 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
[all...]
H A Drv770.c52 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
57 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
67 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
69 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
74 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
82 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
85 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
H A Drv515.c699 int index_reg = 0x6578 + crtc->crtc_offset;
700 int data_reg = 0x657c + crtc->crtc_offset;
702 WREG32(0x659C + crtc->crtc_offset, 0x0);
703 WREG32(0x6594 + crtc->crtc_offset, 0x705);
704 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
705 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
706 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
707 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
708 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
H A Devergreen.c220 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
225 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
228 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
230 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
233 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
235 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
240 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
248 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
251 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
485 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
[all...]
H A Dsi.c488 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
871 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
875 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
876 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
880 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
883 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
884 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
888 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
891 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
892 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cn
[all...]
H A Datombios_encoders.c1960 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1963 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1966 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1969 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
H A Dradeon_mode.h305 uint32_t crtc_offset; member in struct:radeon_crtc
H A Dr100.c196 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
200 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
208 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
211 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
H A Devergreen_cs.c1227 header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
1229 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
/freebsd-11-stable/usr.sbin/bhyve/
H A Dvga.c111 uint8_t crtc_offset; member in struct:vga_softc::__anon8715
788 *val = sc->vga_crtc.crtc_offset;
1024 sc->vga_crtc.crtc_offset = val;
/freebsd-11-stable/sys/dev/drm/
H A Dr128_drv.h100 u32 crtc_offset; member in struct:drm_r128_private
H A Dr128_state.c1276 dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1295 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);

Completed in 174 milliseconds