1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell/* RS600 / Radeon X1250/X1270 integrated GPU 29254885Sdumbbell * 30254885Sdumbbell * This file gather function specific to RS600 which is the IGP of 31254885Sdumbbell * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32254885Sdumbbell * is the X1250/X1270 supporting AMD CPU). The display engine are 33254885Sdumbbell * the avivo one, bios is an atombios, 3D block are the one of the 34254885Sdumbbell * R4XX family. The GART is different from the RS400 one and is very 35254885Sdumbbell * close to the one of the R600 family (R600 likely being an evolution 36254885Sdumbbell * of the RS600 GART block). 37254885Sdumbbell */ 38254885Sdumbbell 39254885Sdumbbell#include <sys/cdefs.h> 40254885Sdumbbell__FBSDID("$FreeBSD$"); 41254885Sdumbbell 42254885Sdumbbell#include <dev/drm2/drmP.h> 43254885Sdumbbell#include "radeon.h" 44254885Sdumbbell#include "radeon_asic.h" 45254885Sdumbbell#include "atom.h" 46254885Sdumbbell#include "rs600d.h" 47254885Sdumbbell 48254885Sdumbbell#include "rs600_reg_safe.h" 49254885Sdumbbell 50254885Sdumbbellstatic void rs600_gpu_init(struct radeon_device *rdev); 51280183Sdumbbell#ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */ 52280183Sdumbbellint rs600_mc_wait_for_idle(struct radeon_device *rdev); 53280183Sdumbbell#endif 54254885Sdumbbell 55254885Sdumbbellstatic const u32 crtc_offsets[2] = 56254885Sdumbbell{ 57254885Sdumbbell 0, 58254885Sdumbbell AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 59254885Sdumbbell}; 60254885Sdumbbell 61280183Sdumbbellstatic bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) 62280183Sdumbbell{ 63280183Sdumbbell if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 64280183Sdumbbell return true; 65280183Sdumbbell else 66280183Sdumbbell return false; 67280183Sdumbbell} 68280183Sdumbbell 69280183Sdumbbellstatic bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) 70280183Sdumbbell{ 71280183Sdumbbell u32 pos1, pos2; 72280183Sdumbbell 73280183Sdumbbell pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 74280183Sdumbbell pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 75280183Sdumbbell 76280183Sdumbbell if (pos1 != pos2) 77280183Sdumbbell return true; 78280183Sdumbbell else 79280183Sdumbbell return false; 80280183Sdumbbell} 81280183Sdumbbell 82280183Sdumbbell/** 83280183Sdumbbell * avivo_wait_for_vblank - vblank wait asic callback. 84280183Sdumbbell * 85280183Sdumbbell * @rdev: radeon_device pointer 86280183Sdumbbell * @crtc: crtc to wait for vblank on 87280183Sdumbbell * 88280183Sdumbbell * Wait for vblank on the requested crtc (r5xx-r7xx). 89280183Sdumbbell */ 90254885Sdumbbellvoid avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 91254885Sdumbbell{ 92280183Sdumbbell unsigned i = 0; 93254885Sdumbbell 94254885Sdumbbell if (crtc >= rdev->num_crtc) 95254885Sdumbbell return; 96254885Sdumbbell 97280183Sdumbbell if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) 98280183Sdumbbell return; 99280183Sdumbbell 100280183Sdumbbell /* depending on when we hit vblank, we may be close to active; if so, 101280183Sdumbbell * wait for another frame. 102280183Sdumbbell */ 103280183Sdumbbell while (avivo_is_in_vblank(rdev, crtc)) { 104280183Sdumbbell if (i++ % 100 == 0) { 105280183Sdumbbell if (!avivo_is_counter_moving(rdev, crtc)) 106254885Sdumbbell break; 107254885Sdumbbell } 108280183Sdumbbell } 109280183Sdumbbell 110280183Sdumbbell while (!avivo_is_in_vblank(rdev, crtc)) { 111280183Sdumbbell if (i++ % 100 == 0) { 112280183Sdumbbell if (!avivo_is_counter_moving(rdev, crtc)) 113254885Sdumbbell break; 114254885Sdumbbell } 115254885Sdumbbell } 116254885Sdumbbell} 117254885Sdumbbell 118254885Sdumbbellvoid rs600_pre_page_flip(struct radeon_device *rdev, int crtc) 119254885Sdumbbell{ 120254885Sdumbbell /* enable the pflip int */ 121254885Sdumbbell radeon_irq_kms_pflip_irq_get(rdev, crtc); 122254885Sdumbbell} 123254885Sdumbbell 124254885Sdumbbellvoid rs600_post_page_flip(struct radeon_device *rdev, int crtc) 125254885Sdumbbell{ 126254885Sdumbbell /* disable the pflip int */ 127254885Sdumbbell radeon_irq_kms_pflip_irq_put(rdev, crtc); 128254885Sdumbbell} 129254885Sdumbbell 130254885Sdumbbellu32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 131254885Sdumbbell{ 132254885Sdumbbell struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 133254885Sdumbbell u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 134254885Sdumbbell int i; 135254885Sdumbbell 136254885Sdumbbell /* Lock the graphics update lock */ 137254885Sdumbbell tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 138254885Sdumbbell WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 139254885Sdumbbell 140254885Sdumbbell /* update the scanout addresses */ 141254885Sdumbbell WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 142254885Sdumbbell (u32)crtc_base); 143254885Sdumbbell WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 144254885Sdumbbell (u32)crtc_base); 145254885Sdumbbell 146254885Sdumbbell /* Wait for update_pending to go high. */ 147254885Sdumbbell for (i = 0; i < rdev->usec_timeout; i++) { 148254885Sdumbbell if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 149254885Sdumbbell break; 150280183Sdumbbell udelay(1); 151254885Sdumbbell } 152254885Sdumbbell DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 153254885Sdumbbell 154254885Sdumbbell /* Unlock the lock, so double-buffering can take place inside vblank */ 155254885Sdumbbell tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 156254885Sdumbbell WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 157254885Sdumbbell 158254885Sdumbbell /* Return current update_pending status: */ 159254885Sdumbbell return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; 160254885Sdumbbell} 161254885Sdumbbell 162254885Sdumbbellvoid rs600_pm_misc(struct radeon_device *rdev) 163254885Sdumbbell{ 164254885Sdumbbell int requested_index = rdev->pm.requested_power_state_index; 165254885Sdumbbell struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 166254885Sdumbbell struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 167254885Sdumbbell u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 168254885Sdumbbell u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 169254885Sdumbbell 170254885Sdumbbell if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 171254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 172254885Sdumbbell tmp = RREG32(voltage->gpio.reg); 173254885Sdumbbell if (voltage->active_high) 174254885Sdumbbell tmp |= voltage->gpio.mask; 175254885Sdumbbell else 176254885Sdumbbell tmp &= ~(voltage->gpio.mask); 177254885Sdumbbell WREG32(voltage->gpio.reg, tmp); 178254885Sdumbbell if (voltage->delay) 179280183Sdumbbell udelay(voltage->delay); 180254885Sdumbbell } else { 181254885Sdumbbell tmp = RREG32(voltage->gpio.reg); 182254885Sdumbbell if (voltage->active_high) 183254885Sdumbbell tmp &= ~voltage->gpio.mask; 184254885Sdumbbell else 185254885Sdumbbell tmp |= voltage->gpio.mask; 186254885Sdumbbell WREG32(voltage->gpio.reg, tmp); 187254885Sdumbbell if (voltage->delay) 188280183Sdumbbell udelay(voltage->delay); 189254885Sdumbbell } 190254885Sdumbbell } else if (voltage->type == VOLTAGE_VDDC) 191254885Sdumbbell radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 192254885Sdumbbell 193254885Sdumbbell dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 194254885Sdumbbell dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 195254885Sdumbbell dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 196254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 197254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 198254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 199254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 200254885Sdumbbell } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 201254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 202254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 203254885Sdumbbell } 204254885Sdumbbell } else { 205254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 206254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 207254885Sdumbbell } 208254885Sdumbbell WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 209254885Sdumbbell 210254885Sdumbbell dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 211254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 212254885Sdumbbell dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 213254885Sdumbbell if (voltage->delay) { 214254885Sdumbbell dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 215254885Sdumbbell dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 216254885Sdumbbell } else 217254885Sdumbbell dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 218254885Sdumbbell } else 219254885Sdumbbell dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 220254885Sdumbbell WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 221254885Sdumbbell 222254885Sdumbbell hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 223254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 224254885Sdumbbell hdp_dyn_cntl &= ~HDP_FORCEON; 225254885Sdumbbell else 226254885Sdumbbell hdp_dyn_cntl |= HDP_FORCEON; 227254885Sdumbbell WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 228254885Sdumbbell#if 0 229254885Sdumbbell /* mc_host_dyn seems to cause hangs from time to time */ 230254885Sdumbbell mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 231254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 232254885Sdumbbell mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 233254885Sdumbbell else 234254885Sdumbbell mc_host_dyn_cntl |= MC_HOST_FORCEON; 235254885Sdumbbell WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 236254885Sdumbbell#endif 237254885Sdumbbell dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 238254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 239254885Sdumbbell dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 240254885Sdumbbell else 241254885Sdumbbell dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 242254885Sdumbbell WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 243254885Sdumbbell 244254885Sdumbbell /* set pcie lanes */ 245254885Sdumbbell if ((rdev->flags & RADEON_IS_PCIE) && 246254885Sdumbbell !(rdev->flags & RADEON_IS_IGP) && 247254885Sdumbbell rdev->asic->pm.set_pcie_lanes && 248254885Sdumbbell (ps->pcie_lanes != 249254885Sdumbbell rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 250254885Sdumbbell radeon_set_pcie_lanes(rdev, 251254885Sdumbbell ps->pcie_lanes); 252254885Sdumbbell DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 253254885Sdumbbell } 254254885Sdumbbell} 255254885Sdumbbell 256254885Sdumbbellvoid rs600_pm_prepare(struct radeon_device *rdev) 257254885Sdumbbell{ 258254885Sdumbbell struct drm_device *ddev = rdev->ddev; 259254885Sdumbbell struct drm_crtc *crtc; 260254885Sdumbbell struct radeon_crtc *radeon_crtc; 261254885Sdumbbell u32 tmp; 262254885Sdumbbell 263254885Sdumbbell /* disable any active CRTCs */ 264254885Sdumbbell list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 265254885Sdumbbell radeon_crtc = to_radeon_crtc(crtc); 266254885Sdumbbell if (radeon_crtc->enabled) { 267254885Sdumbbell tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 268254885Sdumbbell tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 269254885Sdumbbell WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 270254885Sdumbbell } 271254885Sdumbbell } 272254885Sdumbbell} 273254885Sdumbbell 274254885Sdumbbellvoid rs600_pm_finish(struct radeon_device *rdev) 275254885Sdumbbell{ 276254885Sdumbbell struct drm_device *ddev = rdev->ddev; 277254885Sdumbbell struct drm_crtc *crtc; 278254885Sdumbbell struct radeon_crtc *radeon_crtc; 279254885Sdumbbell u32 tmp; 280254885Sdumbbell 281254885Sdumbbell /* enable any active CRTCs */ 282254885Sdumbbell list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 283254885Sdumbbell radeon_crtc = to_radeon_crtc(crtc); 284254885Sdumbbell if (radeon_crtc->enabled) { 285254885Sdumbbell tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 286254885Sdumbbell tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 287254885Sdumbbell WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 288254885Sdumbbell } 289254885Sdumbbell } 290254885Sdumbbell} 291254885Sdumbbell 292254885Sdumbbell/* hpd for digital panel detect/disconnect */ 293254885Sdumbbellbool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 294254885Sdumbbell{ 295254885Sdumbbell u32 tmp; 296254885Sdumbbell bool connected = false; 297254885Sdumbbell 298254885Sdumbbell switch (hpd) { 299254885Sdumbbell case RADEON_HPD_1: 300254885Sdumbbell tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 301254885Sdumbbell if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 302254885Sdumbbell connected = true; 303254885Sdumbbell break; 304254885Sdumbbell case RADEON_HPD_2: 305254885Sdumbbell tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 306254885Sdumbbell if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 307254885Sdumbbell connected = true; 308254885Sdumbbell break; 309254885Sdumbbell default: 310254885Sdumbbell break; 311254885Sdumbbell } 312254885Sdumbbell return connected; 313254885Sdumbbell} 314254885Sdumbbell 315254885Sdumbbellvoid rs600_hpd_set_polarity(struct radeon_device *rdev, 316254885Sdumbbell enum radeon_hpd_id hpd) 317254885Sdumbbell{ 318254885Sdumbbell u32 tmp; 319254885Sdumbbell bool connected = rs600_hpd_sense(rdev, hpd); 320254885Sdumbbell 321254885Sdumbbell switch (hpd) { 322254885Sdumbbell case RADEON_HPD_1: 323254885Sdumbbell tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 324254885Sdumbbell if (connected) 325254885Sdumbbell tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 326254885Sdumbbell else 327254885Sdumbbell tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 328254885Sdumbbell WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 329254885Sdumbbell break; 330254885Sdumbbell case RADEON_HPD_2: 331254885Sdumbbell tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 332254885Sdumbbell if (connected) 333254885Sdumbbell tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 334254885Sdumbbell else 335254885Sdumbbell tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 336254885Sdumbbell WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 337254885Sdumbbell break; 338254885Sdumbbell default: 339254885Sdumbbell break; 340254885Sdumbbell } 341254885Sdumbbell} 342254885Sdumbbell 343254885Sdumbbellvoid rs600_hpd_init(struct radeon_device *rdev) 344254885Sdumbbell{ 345254885Sdumbbell struct drm_device *dev = rdev->ddev; 346254885Sdumbbell struct drm_connector *connector; 347254885Sdumbbell unsigned enable = 0; 348254885Sdumbbell 349254885Sdumbbell list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 350254885Sdumbbell struct radeon_connector *radeon_connector = to_radeon_connector(connector); 351254885Sdumbbell switch (radeon_connector->hpd.hpd) { 352254885Sdumbbell case RADEON_HPD_1: 353254885Sdumbbell WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 354254885Sdumbbell S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 355254885Sdumbbell break; 356254885Sdumbbell case RADEON_HPD_2: 357254885Sdumbbell WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 358254885Sdumbbell S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 359254885Sdumbbell break; 360254885Sdumbbell default: 361254885Sdumbbell break; 362254885Sdumbbell } 363254885Sdumbbell enable |= 1 << radeon_connector->hpd.hpd; 364254885Sdumbbell radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 365254885Sdumbbell } 366254885Sdumbbell radeon_irq_kms_enable_hpd(rdev, enable); 367254885Sdumbbell} 368254885Sdumbbell 369254885Sdumbbellvoid rs600_hpd_fini(struct radeon_device *rdev) 370254885Sdumbbell{ 371254885Sdumbbell struct drm_device *dev = rdev->ddev; 372254885Sdumbbell struct drm_connector *connector; 373254885Sdumbbell unsigned disable = 0; 374254885Sdumbbell 375254885Sdumbbell list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 376254885Sdumbbell struct radeon_connector *radeon_connector = to_radeon_connector(connector); 377254885Sdumbbell switch (radeon_connector->hpd.hpd) { 378254885Sdumbbell case RADEON_HPD_1: 379254885Sdumbbell WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 380254885Sdumbbell S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 381254885Sdumbbell break; 382254885Sdumbbell case RADEON_HPD_2: 383254885Sdumbbell WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 384254885Sdumbbell S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 385254885Sdumbbell break; 386254885Sdumbbell default: 387254885Sdumbbell break; 388254885Sdumbbell } 389254885Sdumbbell disable |= 1 << radeon_connector->hpd.hpd; 390254885Sdumbbell } 391254885Sdumbbell radeon_irq_kms_disable_hpd(rdev, disable); 392254885Sdumbbell} 393254885Sdumbbell 394254885Sdumbbellint rs600_asic_reset(struct radeon_device *rdev) 395254885Sdumbbell{ 396254885Sdumbbell struct rv515_mc_save save; 397254885Sdumbbell u32 status, tmp; 398254885Sdumbbell int ret = 0; 399254885Sdumbbell 400254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 401254885Sdumbbell if (!G_000E40_GUI_ACTIVE(status)) { 402254885Sdumbbell return 0; 403254885Sdumbbell } 404254885Sdumbbell /* Stops all mc clients */ 405254885Sdumbbell rv515_mc_stop(rdev, &save); 406254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 407254885Sdumbbell dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 408254885Sdumbbell /* stop CP */ 409254885Sdumbbell WREG32(RADEON_CP_CSQ_CNTL, 0); 410254885Sdumbbell tmp = RREG32(RADEON_CP_RB_CNTL); 411254885Sdumbbell WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 412254885Sdumbbell WREG32(RADEON_CP_RB_RPTR_WR, 0); 413254885Sdumbbell WREG32(RADEON_CP_RB_WPTR, 0); 414254885Sdumbbell WREG32(RADEON_CP_RB_CNTL, tmp); 415255573Sdumbbell pci_save_state(device_get_parent(rdev->dev)); 416254885Sdumbbell /* disable bus mastering */ 417254885Sdumbbell pci_disable_busmaster(rdev->dev); 418280183Sdumbbell mdelay(1); 419254885Sdumbbell /* reset GA+VAP */ 420254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 421254885Sdumbbell S_0000F0_SOFT_RESET_GA(1)); 422254885Sdumbbell RREG32(R_0000F0_RBBM_SOFT_RESET); 423280183Sdumbbell mdelay(500); 424254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 425280183Sdumbbell mdelay(1); 426254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 427254885Sdumbbell dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 428254885Sdumbbell /* reset CP */ 429254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 430254885Sdumbbell RREG32(R_0000F0_RBBM_SOFT_RESET); 431280183Sdumbbell mdelay(500); 432254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 433280183Sdumbbell mdelay(1); 434254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 435254885Sdumbbell dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 436254885Sdumbbell /* reset MC */ 437254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 438254885Sdumbbell RREG32(R_0000F0_RBBM_SOFT_RESET); 439280183Sdumbbell mdelay(500); 440254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 441280183Sdumbbell mdelay(1); 442254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 443254885Sdumbbell dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 444254885Sdumbbell /* restore PCI & busmastering */ 445255573Sdumbbell pci_restore_state(device_get_parent(rdev->dev)); 446254885Sdumbbell /* Check if GPU is idle */ 447254885Sdumbbell if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 448254885Sdumbbell dev_err(rdev->dev, "failed to reset GPU\n"); 449254885Sdumbbell ret = -1; 450254885Sdumbbell } else 451254885Sdumbbell dev_info(rdev->dev, "GPU reset succeed\n"); 452254885Sdumbbell rv515_mc_resume(rdev, &save); 453254885Sdumbbell return ret; 454254885Sdumbbell} 455254885Sdumbbell 456254885Sdumbbell/* 457254885Sdumbbell * GART. 458254885Sdumbbell */ 459254885Sdumbbellvoid rs600_gart_tlb_flush(struct radeon_device *rdev) 460254885Sdumbbell{ 461254885Sdumbbell uint32_t tmp; 462254885Sdumbbell 463254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 464254885Sdumbbell tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 465254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 466254885Sdumbbell 467254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 468254885Sdumbbell tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 469254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 470254885Sdumbbell 471254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 472254885Sdumbbell tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 473254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 474254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 475254885Sdumbbell} 476254885Sdumbbell 477254885Sdumbbellstatic int rs600_gart_init(struct radeon_device *rdev) 478254885Sdumbbell{ 479254885Sdumbbell int r; 480254885Sdumbbell 481254885Sdumbbell if (rdev->gart.robj) { 482254885Sdumbbell DRM_ERROR("RS600 GART already initialized\n"); 483254885Sdumbbell return 0; 484254885Sdumbbell } 485254885Sdumbbell /* Initialize common gart structure */ 486254885Sdumbbell r = radeon_gart_init(rdev); 487254885Sdumbbell if (r) { 488254885Sdumbbell return r; 489254885Sdumbbell } 490254885Sdumbbell rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 491254885Sdumbbell return radeon_gart_table_vram_alloc(rdev); 492254885Sdumbbell} 493254885Sdumbbell 494254885Sdumbbellstatic int rs600_gart_enable(struct radeon_device *rdev) 495254885Sdumbbell{ 496254885Sdumbbell u32 tmp; 497254885Sdumbbell int r, i; 498254885Sdumbbell 499254885Sdumbbell if (rdev->gart.robj == NULL) { 500254885Sdumbbell dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 501254885Sdumbbell return -EINVAL; 502254885Sdumbbell } 503254885Sdumbbell r = radeon_gart_table_vram_pin(rdev); 504254885Sdumbbell if (r) 505254885Sdumbbell return r; 506254885Sdumbbell radeon_gart_restore(rdev); 507254885Sdumbbell /* Enable bus master */ 508254885Sdumbbell tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 509254885Sdumbbell WREG32(RADEON_BUS_CNTL, tmp); 510254885Sdumbbell /* FIXME: setup default page */ 511254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, 512254885Sdumbbell (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 513254885Sdumbbell S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 514254885Sdumbbell 515254885Sdumbbell for (i = 0; i < 19; i++) { 516254885Sdumbbell WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 517254885Sdumbbell S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 518254885Sdumbbell S_00016C_SYSTEM_ACCESS_MODE_MASK( 519254885Sdumbbell V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 520254885Sdumbbell S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 521254885Sdumbbell V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 522254885Sdumbbell S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 523254885Sdumbbell S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 524254885Sdumbbell S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 525254885Sdumbbell } 526254885Sdumbbell /* enable first context */ 527254885Sdumbbell WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 528254885Sdumbbell S_000102_ENABLE_PAGE_TABLE(1) | 529254885Sdumbbell S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 530254885Sdumbbell 531254885Sdumbbell /* disable all other contexts */ 532254885Sdumbbell for (i = 1; i < 8; i++) 533254885Sdumbbell WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 534254885Sdumbbell 535254885Sdumbbell /* setup the page table */ 536254885Sdumbbell WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 537254885Sdumbbell rdev->gart.table_addr); 538254885Sdumbbell WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 539254885Sdumbbell WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 540254885Sdumbbell WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 541254885Sdumbbell 542254885Sdumbbell /* System context maps to VRAM space */ 543254885Sdumbbell WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 544254885Sdumbbell WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 545254885Sdumbbell 546254885Sdumbbell /* enable page tables */ 547254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 548254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 549254885Sdumbbell tmp = RREG32_MC(R_000009_MC_CNTL1); 550254885Sdumbbell WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 551254885Sdumbbell rs600_gart_tlb_flush(rdev); 552254885Sdumbbell DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 553254885Sdumbbell (unsigned)(rdev->mc.gtt_size >> 20), 554254885Sdumbbell (unsigned long long)rdev->gart.table_addr); 555254885Sdumbbell rdev->gart.ready = true; 556254885Sdumbbell return 0; 557254885Sdumbbell} 558254885Sdumbbell 559254885Sdumbbellstatic void rs600_gart_disable(struct radeon_device *rdev) 560254885Sdumbbell{ 561254885Sdumbbell u32 tmp; 562254885Sdumbbell 563254885Sdumbbell /* FIXME: disable out of gart access */ 564254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, 0); 565254885Sdumbbell tmp = RREG32_MC(R_000009_MC_CNTL1); 566254885Sdumbbell WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 567254885Sdumbbell radeon_gart_table_vram_unpin(rdev); 568254885Sdumbbell} 569254885Sdumbbell 570254885Sdumbbellstatic void rs600_gart_fini(struct radeon_device *rdev) 571254885Sdumbbell{ 572254885Sdumbbell radeon_gart_fini(rdev); 573254885Sdumbbell rs600_gart_disable(rdev); 574254885Sdumbbell radeon_gart_table_vram_free(rdev); 575254885Sdumbbell} 576254885Sdumbbell 577254885Sdumbbell#define R600_PTE_VALID (1 << 0) 578254885Sdumbbell#define R600_PTE_SYSTEM (1 << 1) 579254885Sdumbbell#define R600_PTE_SNOOPED (1 << 2) 580254885Sdumbbell#define R600_PTE_READABLE (1 << 5) 581254885Sdumbbell#define R600_PTE_WRITEABLE (1 << 6) 582254885Sdumbbell 583254885Sdumbbellint rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 584254885Sdumbbell{ 585254885Sdumbbell uint64_t *ptr = rdev->gart.ptr; 586254885Sdumbbell 587254885Sdumbbell if (i < 0 || i > rdev->gart.num_gpu_pages) { 588254885Sdumbbell return -EINVAL; 589254885Sdumbbell } 590254885Sdumbbell addr = addr & 0xFFFFFFFFFFFFF000ULL; 591254885Sdumbbell addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 592254885Sdumbbell addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 593254885Sdumbbell ptr[i] = addr; 594254885Sdumbbell return 0; 595254885Sdumbbell} 596254885Sdumbbell 597254885Sdumbbellint rs600_irq_set(struct radeon_device *rdev) 598254885Sdumbbell{ 599254885Sdumbbell uint32_t tmp = 0; 600254885Sdumbbell uint32_t mode_int = 0; 601254885Sdumbbell u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 602254885Sdumbbell ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 603254885Sdumbbell u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 604254885Sdumbbell ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 605254885Sdumbbell u32 hdmi0; 606254885Sdumbbell if (ASIC_IS_DCE2(rdev)) 607254885Sdumbbell hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 608254885Sdumbbell ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 609254885Sdumbbell else 610254885Sdumbbell hdmi0 = 0; 611254885Sdumbbell 612254885Sdumbbell if (!rdev->irq.installed) { 613254885Sdumbbell DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n"); 614254885Sdumbbell WREG32(R_000040_GEN_INT_CNTL, 0); 615254885Sdumbbell return -EINVAL; 616254885Sdumbbell } 617254885Sdumbbell if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 618254885Sdumbbell tmp |= S_000040_SW_INT_EN(1); 619254885Sdumbbell } 620254885Sdumbbell if (rdev->irq.crtc_vblank_int[0] || 621254885Sdumbbell atomic_read(&rdev->irq.pflip[0])) { 622254885Sdumbbell mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 623254885Sdumbbell } 624254885Sdumbbell if (rdev->irq.crtc_vblank_int[1] || 625254885Sdumbbell atomic_read(&rdev->irq.pflip[1])) { 626254885Sdumbbell mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 627254885Sdumbbell } 628254885Sdumbbell if (rdev->irq.hpd[0]) { 629254885Sdumbbell hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 630254885Sdumbbell } 631254885Sdumbbell if (rdev->irq.hpd[1]) { 632254885Sdumbbell hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 633254885Sdumbbell } 634254885Sdumbbell if (rdev->irq.afmt[0]) { 635254885Sdumbbell hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 636254885Sdumbbell } 637254885Sdumbbell WREG32(R_000040_GEN_INT_CNTL, tmp); 638254885Sdumbbell WREG32(R_006540_DxMODE_INT_MASK, mode_int); 639254885Sdumbbell WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 640254885Sdumbbell WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 641254885Sdumbbell if (ASIC_IS_DCE2(rdev)) 642254885Sdumbbell WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 643254885Sdumbbell return 0; 644254885Sdumbbell} 645254885Sdumbbell 646254885Sdumbbellstatic inline u32 rs600_irq_ack(struct radeon_device *rdev) 647254885Sdumbbell{ 648254885Sdumbbell uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 649254885Sdumbbell uint32_t irq_mask = S_000044_SW_INT(1); 650254885Sdumbbell u32 tmp; 651254885Sdumbbell 652254885Sdumbbell if (G_000044_DISPLAY_INT_STAT(irqs)) { 653254885Sdumbbell rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 654254885Sdumbbell if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 655254885Sdumbbell WREG32(R_006534_D1MODE_VBLANK_STATUS, 656254885Sdumbbell S_006534_D1MODE_VBLANK_ACK(1)); 657254885Sdumbbell } 658254885Sdumbbell if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 659254885Sdumbbell WREG32(R_006D34_D2MODE_VBLANK_STATUS, 660254885Sdumbbell S_006D34_D2MODE_VBLANK_ACK(1)); 661254885Sdumbbell } 662254885Sdumbbell if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 663254885Sdumbbell tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 664254885Sdumbbell tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 665254885Sdumbbell WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 666254885Sdumbbell } 667254885Sdumbbell if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 668254885Sdumbbell tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 669254885Sdumbbell tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 670254885Sdumbbell WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 671254885Sdumbbell } 672254885Sdumbbell } else { 673254885Sdumbbell rdev->irq.stat_regs.r500.disp_int = 0; 674254885Sdumbbell } 675254885Sdumbbell 676254885Sdumbbell if (ASIC_IS_DCE2(rdev)) { 677254885Sdumbbell rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & 678254885Sdumbbell S_007404_HDMI0_AZ_FORMAT_WTRIG(1); 679254885Sdumbbell if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 680254885Sdumbbell tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); 681254885Sdumbbell tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); 682254885Sdumbbell WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); 683254885Sdumbbell } 684254885Sdumbbell } else 685254885Sdumbbell rdev->irq.stat_regs.r500.hdmi0_status = 0; 686254885Sdumbbell 687254885Sdumbbell if (irqs) { 688254885Sdumbbell WREG32(R_000044_GEN_INT_STATUS, irqs); 689254885Sdumbbell } 690254885Sdumbbell return irqs & irq_mask; 691254885Sdumbbell} 692254885Sdumbbell 693254885Sdumbbellvoid rs600_irq_disable(struct radeon_device *rdev) 694254885Sdumbbell{ 695254885Sdumbbell u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 696254885Sdumbbell ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 697254885Sdumbbell WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 698254885Sdumbbell WREG32(R_000040_GEN_INT_CNTL, 0); 699254885Sdumbbell WREG32(R_006540_DxMODE_INT_MASK, 0); 700254885Sdumbbell /* Wait and acknowledge irq */ 701280183Sdumbbell mdelay(1); 702254885Sdumbbell rs600_irq_ack(rdev); 703254885Sdumbbell} 704254885Sdumbbell 705254885Sdumbbellirqreturn_t rs600_irq_process(struct radeon_device *rdev) 706254885Sdumbbell{ 707254885Sdumbbell u32 status, msi_rearm; 708254885Sdumbbell bool queue_hotplug = false; 709254885Sdumbbell bool queue_hdmi = false; 710254885Sdumbbell 711254885Sdumbbell status = rs600_irq_ack(rdev); 712254885Sdumbbell if (!status && 713254885Sdumbbell !rdev->irq.stat_regs.r500.disp_int && 714254885Sdumbbell !rdev->irq.stat_regs.r500.hdmi0_status) { 715254885Sdumbbell return IRQ_NONE; 716254885Sdumbbell } 717254885Sdumbbell while (status || 718254885Sdumbbell rdev->irq.stat_regs.r500.disp_int || 719254885Sdumbbell rdev->irq.stat_regs.r500.hdmi0_status) { 720254885Sdumbbell /* SW interrupt */ 721254885Sdumbbell if (G_000044_SW_INT(status)) { 722254885Sdumbbell radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 723254885Sdumbbell } 724254885Sdumbbell /* Vertical blank interrupts */ 725254885Sdumbbell if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 726254885Sdumbbell if (rdev->irq.crtc_vblank_int[0]) { 727254885Sdumbbell drm_handle_vblank(rdev->ddev, 0); 728254885Sdumbbell rdev->pm.vblank_sync = true; 729254885Sdumbbell DRM_WAKEUP(&rdev->irq.vblank_queue); 730254885Sdumbbell } 731254885Sdumbbell if (atomic_read(&rdev->irq.pflip[0])) 732254885Sdumbbell radeon_crtc_handle_flip(rdev, 0); 733254885Sdumbbell } 734254885Sdumbbell if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 735254885Sdumbbell if (rdev->irq.crtc_vblank_int[1]) { 736254885Sdumbbell drm_handle_vblank(rdev->ddev, 1); 737254885Sdumbbell rdev->pm.vblank_sync = true; 738254885Sdumbbell DRM_WAKEUP(&rdev->irq.vblank_queue); 739254885Sdumbbell } 740254885Sdumbbell if (atomic_read(&rdev->irq.pflip[1])) 741254885Sdumbbell radeon_crtc_handle_flip(rdev, 1); 742254885Sdumbbell } 743254885Sdumbbell if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 744254885Sdumbbell queue_hotplug = true; 745254885Sdumbbell DRM_DEBUG("HPD1\n"); 746254885Sdumbbell } 747254885Sdumbbell if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 748254885Sdumbbell queue_hotplug = true; 749254885Sdumbbell DRM_DEBUG("HPD2\n"); 750254885Sdumbbell } 751254885Sdumbbell if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 752254885Sdumbbell queue_hdmi = true; 753254885Sdumbbell DRM_DEBUG("HDMI0\n"); 754254885Sdumbbell } 755254885Sdumbbell status = rs600_irq_ack(rdev); 756254885Sdumbbell } 757254885Sdumbbell if (queue_hotplug) 758254885Sdumbbell taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 759254885Sdumbbell if (queue_hdmi) 760254885Sdumbbell taskqueue_enqueue(rdev->tq, &rdev->audio_work); 761254885Sdumbbell if (rdev->msi_enabled) { 762254885Sdumbbell switch (rdev->family) { 763254885Sdumbbell case CHIP_RS600: 764254885Sdumbbell case CHIP_RS690: 765254885Sdumbbell case CHIP_RS740: 766254885Sdumbbell msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 767254885Sdumbbell WREG32(RADEON_BUS_CNTL, msi_rearm); 768254885Sdumbbell WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 769254885Sdumbbell break; 770254885Sdumbbell default: 771254885Sdumbbell WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 772254885Sdumbbell break; 773254885Sdumbbell } 774254885Sdumbbell } 775254885Sdumbbell return IRQ_HANDLED; 776254885Sdumbbell} 777254885Sdumbbell 778254885Sdumbbellu32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 779254885Sdumbbell{ 780254885Sdumbbell if (crtc == 0) 781254885Sdumbbell return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 782254885Sdumbbell else 783254885Sdumbbell return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 784254885Sdumbbell} 785254885Sdumbbell 786254885Sdumbbellint rs600_mc_wait_for_idle(struct radeon_device *rdev) 787254885Sdumbbell{ 788254885Sdumbbell unsigned i; 789254885Sdumbbell 790254885Sdumbbell for (i = 0; i < rdev->usec_timeout; i++) { 791254885Sdumbbell if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 792254885Sdumbbell return 0; 793280183Sdumbbell udelay(1); 794254885Sdumbbell } 795254885Sdumbbell return -1; 796254885Sdumbbell} 797254885Sdumbbell 798254885Sdumbbellstatic void rs600_gpu_init(struct radeon_device *rdev) 799254885Sdumbbell{ 800254885Sdumbbell r420_pipes_init(rdev); 801254885Sdumbbell /* Wait for mc idle */ 802254885Sdumbbell if (rs600_mc_wait_for_idle(rdev)) 803254885Sdumbbell dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 804254885Sdumbbell} 805254885Sdumbbell 806254885Sdumbbellstatic void rs600_mc_init(struct radeon_device *rdev) 807254885Sdumbbell{ 808254885Sdumbbell u64 base; 809254885Sdumbbell 810254885Sdumbbell rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 811254885Sdumbbell rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 812254885Sdumbbell rdev->mc.vram_is_ddr = true; 813254885Sdumbbell rdev->mc.vram_width = 128; 814254885Sdumbbell rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 815254885Sdumbbell rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 816254885Sdumbbell rdev->mc.visible_vram_size = rdev->mc.aper_size; 817254885Sdumbbell rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 818254885Sdumbbell base = RREG32_MC(R_000004_MC_FB_LOCATION); 819254885Sdumbbell base = G_000004_MC_FB_START(base) << 16; 820254885Sdumbbell radeon_vram_location(rdev, &rdev->mc, base); 821254885Sdumbbell rdev->mc.gtt_base_align = 0; 822254885Sdumbbell radeon_gtt_location(rdev, &rdev->mc); 823254885Sdumbbell radeon_update_bandwidth_info(rdev); 824254885Sdumbbell} 825254885Sdumbbell 826254885Sdumbbellvoid rs600_bandwidth_update(struct radeon_device *rdev) 827254885Sdumbbell{ 828254885Sdumbbell struct drm_display_mode *mode0 = NULL; 829254885Sdumbbell struct drm_display_mode *mode1 = NULL; 830254885Sdumbbell u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 831254885Sdumbbell /* FIXME: implement full support */ 832254885Sdumbbell 833254885Sdumbbell radeon_update_display_priority(rdev); 834254885Sdumbbell 835254885Sdumbbell if (rdev->mode_info.crtcs[0]->base.enabled) 836254885Sdumbbell mode0 = &rdev->mode_info.crtcs[0]->base.mode; 837254885Sdumbbell if (rdev->mode_info.crtcs[1]->base.enabled) 838254885Sdumbbell mode1 = &rdev->mode_info.crtcs[1]->base.mode; 839254885Sdumbbell 840254885Sdumbbell rs690_line_buffer_adjust(rdev, mode0, mode1); 841254885Sdumbbell 842254885Sdumbbell if (rdev->disp_priority == 2) { 843254885Sdumbbell d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 844254885Sdumbbell d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 845254885Sdumbbell d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 846254885Sdumbbell d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 847254885Sdumbbell WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 848254885Sdumbbell WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 849254885Sdumbbell WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 850254885Sdumbbell WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 851254885Sdumbbell } 852254885Sdumbbell} 853254885Sdumbbell 854254885Sdumbbelluint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 855254885Sdumbbell{ 856254885Sdumbbell WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 857254885Sdumbbell S_000070_MC_IND_CITF_ARB0(1)); 858254885Sdumbbell return RREG32(R_000074_MC_IND_DATA); 859254885Sdumbbell} 860254885Sdumbbell 861254885Sdumbbellvoid rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 862254885Sdumbbell{ 863254885Sdumbbell WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 864254885Sdumbbell S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 865254885Sdumbbell WREG32(R_000074_MC_IND_DATA, v); 866254885Sdumbbell} 867254885Sdumbbell 868254885Sdumbbellstatic void rs600_debugfs(struct radeon_device *rdev) 869254885Sdumbbell{ 870254885Sdumbbell if (r100_debugfs_rbbm_init(rdev)) 871254885Sdumbbell DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 872254885Sdumbbell} 873254885Sdumbbell 874254885Sdumbbellvoid rs600_set_safe_registers(struct radeon_device *rdev) 875254885Sdumbbell{ 876254885Sdumbbell rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 877280183Sdumbbell rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 878254885Sdumbbell} 879254885Sdumbbell 880254885Sdumbbellstatic void rs600_mc_program(struct radeon_device *rdev) 881254885Sdumbbell{ 882254885Sdumbbell struct rv515_mc_save save; 883254885Sdumbbell 884254885Sdumbbell /* Stops all mc clients */ 885254885Sdumbbell rv515_mc_stop(rdev, &save); 886254885Sdumbbell 887254885Sdumbbell /* Wait for mc idle */ 888254885Sdumbbell if (rs600_mc_wait_for_idle(rdev)) 889254885Sdumbbell dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 890254885Sdumbbell 891254885Sdumbbell /* FIXME: What does AGP means for such chipset ? */ 892254885Sdumbbell WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 893254885Sdumbbell WREG32_MC(R_000006_AGP_BASE, 0); 894254885Sdumbbell WREG32_MC(R_000007_AGP_BASE_2, 0); 895254885Sdumbbell /* Program MC */ 896254885Sdumbbell WREG32_MC(R_000004_MC_FB_LOCATION, 897254885Sdumbbell S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 898254885Sdumbbell S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 899254885Sdumbbell WREG32(R_000134_HDP_FB_LOCATION, 900254885Sdumbbell S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 901254885Sdumbbell 902254885Sdumbbell rv515_mc_resume(rdev, &save); 903254885Sdumbbell} 904254885Sdumbbell 905254885Sdumbbellstatic int rs600_startup(struct radeon_device *rdev) 906254885Sdumbbell{ 907254885Sdumbbell int r; 908254885Sdumbbell 909254885Sdumbbell rs600_mc_program(rdev); 910254885Sdumbbell /* Resume clock */ 911254885Sdumbbell rv515_clock_startup(rdev); 912254885Sdumbbell /* Initialize GPU configuration (# pipes, ...) */ 913254885Sdumbbell rs600_gpu_init(rdev); 914254885Sdumbbell /* Initialize GART (initialize after TTM so we can allocate 915254885Sdumbbell * memory through TTM but finalize after TTM) */ 916254885Sdumbbell r = rs600_gart_enable(rdev); 917254885Sdumbbell if (r) 918254885Sdumbbell return r; 919254885Sdumbbell 920254885Sdumbbell /* allocate wb buffer */ 921254885Sdumbbell r = radeon_wb_init(rdev); 922254885Sdumbbell if (r) 923254885Sdumbbell return r; 924254885Sdumbbell 925254885Sdumbbell r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 926254885Sdumbbell if (r) { 927254885Sdumbbell dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 928254885Sdumbbell return r; 929254885Sdumbbell } 930254885Sdumbbell 931254885Sdumbbell /* Enable IRQ */ 932254885Sdumbbell rs600_irq_set(rdev); 933254885Sdumbbell rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 934254885Sdumbbell /* 1M ring buffer */ 935254885Sdumbbell r = r100_cp_init(rdev, 1024 * 1024); 936254885Sdumbbell if (r) { 937254885Sdumbbell dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 938254885Sdumbbell return r; 939254885Sdumbbell } 940254885Sdumbbell 941254885Sdumbbell r = radeon_ib_pool_init(rdev); 942254885Sdumbbell if (r) { 943254885Sdumbbell dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 944254885Sdumbbell return r; 945254885Sdumbbell } 946254885Sdumbbell 947254885Sdumbbell r = r600_audio_init(rdev); 948254885Sdumbbell if (r) { 949254885Sdumbbell dev_err(rdev->dev, "failed initializing audio\n"); 950254885Sdumbbell return r; 951254885Sdumbbell } 952254885Sdumbbell 953254885Sdumbbell return 0; 954254885Sdumbbell} 955254885Sdumbbell 956254885Sdumbbellint rs600_resume(struct radeon_device *rdev) 957254885Sdumbbell{ 958254885Sdumbbell int r; 959254885Sdumbbell 960254885Sdumbbell /* Make sur GART are not working */ 961254885Sdumbbell rs600_gart_disable(rdev); 962254885Sdumbbell /* Resume clock before doing reset */ 963254885Sdumbbell rv515_clock_startup(rdev); 964254885Sdumbbell /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 965254885Sdumbbell if (radeon_asic_reset(rdev)) { 966254885Sdumbbell dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 967254885Sdumbbell RREG32(R_000E40_RBBM_STATUS), 968254885Sdumbbell RREG32(R_0007C0_CP_STAT)); 969254885Sdumbbell } 970254885Sdumbbell /* post */ 971254885Sdumbbell atom_asic_init(rdev->mode_info.atom_context); 972254885Sdumbbell /* Resume clock after posting */ 973254885Sdumbbell rv515_clock_startup(rdev); 974254885Sdumbbell /* Initialize surface registers */ 975254885Sdumbbell radeon_surface_init(rdev); 976254885Sdumbbell 977254885Sdumbbell rdev->accel_working = true; 978254885Sdumbbell r = rs600_startup(rdev); 979254885Sdumbbell if (r) { 980254885Sdumbbell rdev->accel_working = false; 981254885Sdumbbell } 982254885Sdumbbell return r; 983254885Sdumbbell} 984254885Sdumbbell 985254885Sdumbbellint rs600_suspend(struct radeon_device *rdev) 986254885Sdumbbell{ 987254885Sdumbbell r600_audio_fini(rdev); 988254885Sdumbbell r100_cp_disable(rdev); 989254885Sdumbbell radeon_wb_disable(rdev); 990254885Sdumbbell rs600_irq_disable(rdev); 991254885Sdumbbell rs600_gart_disable(rdev); 992254885Sdumbbell return 0; 993254885Sdumbbell} 994254885Sdumbbell 995254885Sdumbbellvoid rs600_fini(struct radeon_device *rdev) 996254885Sdumbbell{ 997254885Sdumbbell r600_audio_fini(rdev); 998254885Sdumbbell r100_cp_fini(rdev); 999254885Sdumbbell radeon_wb_fini(rdev); 1000254885Sdumbbell radeon_ib_pool_fini(rdev); 1001254885Sdumbbell radeon_gem_fini(rdev); 1002254885Sdumbbell rs600_gart_fini(rdev); 1003254885Sdumbbell radeon_irq_kms_fini(rdev); 1004254885Sdumbbell radeon_fence_driver_fini(rdev); 1005254885Sdumbbell radeon_bo_fini(rdev); 1006254885Sdumbbell radeon_atombios_fini(rdev); 1007254885Sdumbbell free(rdev->bios, DRM_MEM_DRIVER); 1008254885Sdumbbell rdev->bios = NULL; 1009254885Sdumbbell} 1010254885Sdumbbell 1011254885Sdumbbellint rs600_init(struct radeon_device *rdev) 1012254885Sdumbbell{ 1013254885Sdumbbell int r; 1014254885Sdumbbell 1015254885Sdumbbell /* Disable VGA */ 1016254885Sdumbbell rv515_vga_render_disable(rdev); 1017254885Sdumbbell /* Initialize scratch registers */ 1018254885Sdumbbell radeon_scratch_init(rdev); 1019254885Sdumbbell /* Initialize surface registers */ 1020254885Sdumbbell radeon_surface_init(rdev); 1021254885Sdumbbell /* restore some register to sane defaults */ 1022254885Sdumbbell r100_restore_sanity(rdev); 1023254885Sdumbbell /* BIOS */ 1024254885Sdumbbell if (!radeon_get_bios(rdev)) { 1025254885Sdumbbell if (ASIC_IS_AVIVO(rdev)) 1026254885Sdumbbell return -EINVAL; 1027254885Sdumbbell } 1028254885Sdumbbell if (rdev->is_atom_bios) { 1029254885Sdumbbell r = radeon_atombios_init(rdev); 1030254885Sdumbbell if (r) 1031254885Sdumbbell return r; 1032254885Sdumbbell } else { 1033254885Sdumbbell dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 1034254885Sdumbbell return -EINVAL; 1035254885Sdumbbell } 1036254885Sdumbbell /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1037254885Sdumbbell if (radeon_asic_reset(rdev)) { 1038254885Sdumbbell dev_warn(rdev->dev, 1039254885Sdumbbell "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1040254885Sdumbbell RREG32(R_000E40_RBBM_STATUS), 1041254885Sdumbbell RREG32(R_0007C0_CP_STAT)); 1042254885Sdumbbell } 1043254885Sdumbbell /* check if cards are posted or not */ 1044254885Sdumbbell if (radeon_boot_test_post_card(rdev) == false) 1045254885Sdumbbell return -EINVAL; 1046254885Sdumbbell 1047254885Sdumbbell /* Initialize clocks */ 1048254885Sdumbbell radeon_get_clock_info(rdev->ddev); 1049254885Sdumbbell /* initialize memory controller */ 1050254885Sdumbbell rs600_mc_init(rdev); 1051254885Sdumbbell rs600_debugfs(rdev); 1052254885Sdumbbell /* Fence driver */ 1053254885Sdumbbell r = radeon_fence_driver_init(rdev); 1054254885Sdumbbell if (r) 1055254885Sdumbbell return r; 1056254885Sdumbbell r = radeon_irq_kms_init(rdev); 1057254885Sdumbbell if (r) 1058254885Sdumbbell return r; 1059254885Sdumbbell /* Memory manager */ 1060254885Sdumbbell r = radeon_bo_init(rdev); 1061254885Sdumbbell if (r) 1062254885Sdumbbell return r; 1063254885Sdumbbell r = rs600_gart_init(rdev); 1064254885Sdumbbell if (r) 1065254885Sdumbbell return r; 1066254885Sdumbbell rs600_set_safe_registers(rdev); 1067254885Sdumbbell 1068254885Sdumbbell rdev->accel_working = true; 1069254885Sdumbbell r = rs600_startup(rdev); 1070254885Sdumbbell if (r) { 1071254885Sdumbbell /* Somethings want wront with the accel init stop accel */ 1072254885Sdumbbell dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1073254885Sdumbbell r100_cp_fini(rdev); 1074254885Sdumbbell radeon_wb_fini(rdev); 1075254885Sdumbbell radeon_ib_pool_fini(rdev); 1076254885Sdumbbell rs600_gart_fini(rdev); 1077254885Sdumbbell radeon_irq_kms_fini(rdev); 1078254885Sdumbbell rdev->accel_working = false; 1079254885Sdumbbell } 1080254885Sdumbbell return 0; 1081254885Sdumbbell} 1082