Searched refs:cache_line_size (Results 1 - 21 of 21) sorted by relevance

/freebsd-11-stable/sys/compat/linuxkpi/common/include/linux/
H A Dcache.h34 #define cache_line_size() CACHE_LINE_SIZE macro
/freebsd-11-stable/sys/dev/isci/scil/
H A Dintel_pci.h83 U8 cache_line_size; member in struct:sci_pci_common_header
/freebsd-11-stable/contrib/ofed/libmlx5/
H A Ddbrec.c57 pp = ps / context->cache_line_size;
108 db = page->buf.buf + (i * 8 * sizeof(long) + j) * context->cache_line_size;
131 i = ((void *) db - page->buf.buf) / context->cache_line_size;
H A Dmlx5-abi.h87 __u32 cache_line_size; member in struct:mlx5_alloc_ucontext_resp
H A Dmlx5.c815 context->cache_line_size = resp.cache_line_size;
H A Dmlx5.h242 int cache_line_size; member in struct:mlx5_context
/freebsd-11-stable/sys/ofed/include/uapi/rdma/
H A Dmlx5-abi.h100 __u32 cache_line_size; member in struct:mlx5_ib_alloc_ucontext_resp
/freebsd-11-stable/contrib/llvm-project/lldb/source/Host/common/
H A DNativeProcessProtocol.cpp671 static const size_t cache_line_size = local
683 cache_line_size - (curr_addr % cache_line_size);
/freebsd-11-stable/sys/dev/mly/
H A Dmlyreg.h185 u_int8_t cache_line_size; /* see 8.4 */ member in struct:mly_param_controller
690 u_int8_t cache_line_size; /* see 8.4 */ member in struct:mly_ioctl_getlogdevinfovalid
916 u_int8_t cache_line_size; /* see 8.4 */ member in struct:mly_ldd
/freebsd-11-stable/sys/dev/nxge/include/
H A Dxgehal-regs.h1191 u8 cache_line_size; // 0x0c member in struct:xge_hal_pci_config_le_t
1258 u8 cache_line_size; // 0x0c member in struct:xge_hal_pci_config_t
1314 u8 cache_line_size; // 0x0c
/freebsd-11-stable/sys/dev/vxge/vxgehal/
H A Dvxgehal-regs.h50 u8 cache_line_size; /* 0x0c */ member in struct:vxge_hal_pci_config_le_t
96 u8 cache_line_size; /* 0x0c */ member in struct:vxge_hal_pci_config_t
131 u8 cache_line_size; /* 0x0c */
H A Dvxgehal-mgmtaux.c210 __HAL_AUX_ENTRY("cache_line_size",
211 pci_config->cache_line_size, "0x%02X");
/freebsd-11-stable/sys/dev/pms/freebsd/driver/ini/src/
H A Dagtiapi.c105 #define cache_line_size() CACHE_LINE_SIZE macro
5052 ccb_sz = roundup2(AGTIAPI_CCB_SIZE, cache_line_size());
5053 hdr_sz = roundup2(sizeof(*hdr), cache_line_size());
5177 ccb_sz = roundup2(AGTIAPI_CCB_SIZE, cache_line_size());
5178 hdr_sz = roundup2(sizeof(*hdr), cache_line_size());
5856 hdr_sz = roundup2(sizeof(*hdr), cache_line_size());
/freebsd-11-stable/contrib/llvm-project/lldb/source/Target/
H A DProcess.cpp1991 const size_t cache_line_size = m_memory_cache.GetMemoryCacheLineSize();
1997 cache_line_size - (curr_addr % cache_line_size);
2039 const size_t cache_line_size = m_memory_cache.GetMemoryCacheLineSize();
2045 cache_line_size - (curr_addr % cache_line_size);
H A DTarget.cpp1843 const size_t cache_line_size = 512; local
1850 cache_line_size - (curr_addr % cache_line_size);
/freebsd-11-stable/sys/dev/mlx4/mlx4_core/
H A Dmlx4_main.c269 if (cache_line_size() == 128 || cache_line_size() == 256) {
278 if (cache_line_size() != 32 && cache_line_size() != 64)
H A Dmlx4_fw.c1883 (ilog2(cache_line_size()) - 4) << 5;
1934 dev->caps.eqe_size = cache_line_size();
1935 dev->caps.cqe_size = cache_line_size();
/freebsd-11-stable/sys/dev/nxge/xgehal/
H A Dxgehal-mgmtaux.c1164 __HAL_AUX_ENTRY("cache_line_size",
1165 pci_config.cache_line_size, "0x%02X");
/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Decore_dev.c2910 u32 val, wr_mbs, cache_line_size; local
2930 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
2931 switch (cache_line_size) {
2947 cache_line_size);
/freebsd-11-stable/sys/dev/mlx5/mlx5_ib/
H A Dmlx5_ib_cq.c949 cqe_size = cache_line_size() == 128 ? 128 : 64;
H A Dmlx5_ib_main.c1171 resp.cache_line_size = cache_line_size();

Completed in 273 milliseconds