1/*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c 369102 2021-01-22 12:50:12Z hselasky $ 26 */ 27 28#include <linux/module.h> 29#include <linux/errno.h> 30#include <linux/pci.h> 31#include <linux/dma-mapping.h> 32#include <linux/slab.h> 33#if defined(CONFIG_X86) 34#include <asm/pat.h> 35#endif 36#include <linux/sched.h> 37#include <linux/delay.h> 38#include <linux/fs.h> 39#undef inode 40#include <rdma/ib_user_verbs.h> 41#include <rdma/ib_addr.h> 42#include <rdma/ib_cache.h> 43#include <dev/mlx5/port.h> 44#include <dev/mlx5/vport.h> 45#include <linux/list.h> 46#include <rdma/ib_smi.h> 47#include <rdma/ib_umem.h> 48#include <linux/in.h> 49#include <linux/etherdevice.h> 50#include <dev/mlx5/fs.h> 51#include "mlx5_ib.h" 52 53#define DRIVER_NAME "mlx5ib" 54#ifndef DRIVER_VERSION 55#define DRIVER_VERSION "3.6.0" 56#endif 57#define DRIVER_RELDATE "December 2020" 58 59MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 60MODULE_LICENSE("Dual BSD/GPL"); 61MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1); 62MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1); 63MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1); 64MODULE_VERSION(mlx5ib, 1); 65 66static const char mlx5_version[] = 67 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver " 68 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 69 70enum { 71 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 72}; 73 74static enum rdma_link_layer 75mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 76{ 77 switch (port_type_cap) { 78 case MLX5_CAP_PORT_TYPE_IB: 79 return IB_LINK_LAYER_INFINIBAND; 80 case MLX5_CAP_PORT_TYPE_ETH: 81 return IB_LINK_LAYER_ETHERNET; 82 default: 83 return IB_LINK_LAYER_UNSPECIFIED; 84 } 85} 86 87static enum rdma_link_layer 88mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 89{ 90 struct mlx5_ib_dev *dev = to_mdev(device); 91 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 92 93 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 94} 95 96static bool mlx5_netdev_match(struct net_device *ndev, 97 struct mlx5_core_dev *mdev, 98 const char *dname) 99{ 100 return ndev->if_type == IFT_ETHER && 101 ndev->if_dname != NULL && 102 strcmp(ndev->if_dname, dname) == 0 && 103 ndev->if_softc != NULL && 104 *(struct mlx5_core_dev **)ndev->if_softc == mdev; 105} 106 107static int mlx5_netdev_event(struct notifier_block *this, 108 unsigned long event, void *ptr) 109{ 110 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 111 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 112 roce.nb); 113 114 switch (event) { 115 case NETDEV_REGISTER: 116 case NETDEV_UNREGISTER: 117 write_lock(&ibdev->roce.netdev_lock); 118 /* check if network interface belongs to mlx5en */ 119 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce")) 120 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 121 NULL : ndev; 122 write_unlock(&ibdev->roce.netdev_lock); 123 break; 124 125 case NETDEV_UP: 126 case NETDEV_DOWN: { 127 struct net_device *upper = NULL; 128 129 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 130 && ibdev->ib_active) { 131 struct ib_event ibev = {0}; 132 133 ibev.device = &ibdev->ib_dev; 134 ibev.event = (event == NETDEV_UP) ? 135 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 136 ibev.element.port_num = 1; 137 ib_dispatch_event(&ibev); 138 } 139 break; 140 } 141 142 default: 143 break; 144 } 145 146 return NOTIFY_DONE; 147} 148 149static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 150 u8 port_num) 151{ 152 struct mlx5_ib_dev *ibdev = to_mdev(device); 153 struct net_device *ndev; 154 155 /* Ensure ndev does not disappear before we invoke dev_hold() 156 */ 157 read_lock(&ibdev->roce.netdev_lock); 158 ndev = ibdev->roce.netdev; 159 if (ndev) 160 dev_hold(ndev); 161 read_unlock(&ibdev->roce.netdev_lock); 162 163 return ndev; 164} 165 166static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 167 u8 *active_width) 168{ 169 switch (eth_proto_oper) { 170 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 171 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 172 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 173 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 174 *active_width = IB_WIDTH_1X; 175 *active_speed = IB_SPEED_SDR; 176 break; 177 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 178 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 179 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 180 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 181 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 182 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 183 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR): 184 *active_width = IB_WIDTH_1X; 185 *active_speed = IB_SPEED_QDR; 186 break; 187 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 188 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 189 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 190 *active_width = IB_WIDTH_1X; 191 *active_speed = IB_SPEED_EDR; 192 break; 193 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 194 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 195 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 196 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4): 197 *active_width = IB_WIDTH_4X; 198 *active_speed = IB_SPEED_QDR; 199 break; 200 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 201 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 202 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 203 *active_width = IB_WIDTH_1X; 204 *active_speed = IB_SPEED_HDR; 205 break; 206 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 207 *active_width = IB_WIDTH_4X; 208 *active_speed = IB_SPEED_FDR; 209 break; 210 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 211 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 212 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 213 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 214 *active_width = IB_WIDTH_4X; 215 *active_speed = IB_SPEED_EDR; 216 break; 217 default: 218 *active_width = IB_WIDTH_4X; 219 *active_speed = IB_SPEED_QDR; 220 return -EINVAL; 221 } 222 223 return 0; 224} 225 226static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 227 u8 *active_width) 228{ 229 switch (eth_proto_oper) { 230 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 231 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 232 *active_width = IB_WIDTH_1X; 233 *active_speed = IB_SPEED_SDR; 234 break; 235 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 236 *active_width = IB_WIDTH_1X; 237 *active_speed = IB_SPEED_DDR; 238 break; 239 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 240 *active_width = IB_WIDTH_1X; 241 *active_speed = IB_SPEED_QDR; 242 break; 243 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 244 *active_width = IB_WIDTH_4X; 245 *active_speed = IB_SPEED_QDR; 246 break; 247 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 248 *active_width = IB_WIDTH_1X; 249 *active_speed = IB_SPEED_EDR; 250 break; 251 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 252 *active_width = IB_WIDTH_2X; 253 *active_speed = IB_SPEED_EDR; 254 break; 255 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 256 *active_width = IB_WIDTH_1X; 257 *active_speed = IB_SPEED_HDR; 258 break; 259 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 260 *active_width = IB_WIDTH_4X; 261 *active_speed = IB_SPEED_EDR; 262 break; 263 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 264 *active_width = IB_WIDTH_2X; 265 *active_speed = IB_SPEED_HDR; 266 break; 267 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 268 *active_width = IB_WIDTH_4X; 269 *active_speed = IB_SPEED_HDR; 270 break; 271 default: 272 *active_width = IB_WIDTH_4X; 273 *active_speed = IB_SPEED_QDR; 274 return -EINVAL; 275 } 276 277 return 0; 278} 279 280static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 281 struct ib_port_attr *props) 282{ 283 struct mlx5_ib_dev *dev = to_mdev(device); 284 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 285 struct net_device *ndev; 286 enum ib_mtu ndev_ib_mtu; 287 u16 qkey_viol_cntr; 288 u32 eth_prot_oper; 289 bool ext; 290 int err; 291 292 memset(props, 0, sizeof(*props)); 293 294 /* Possible bad flows are checked before filling out props so in case 295 * of an error it will still be zeroed out. 296 */ 297 err = mlx5_query_port_ptys(dev->mdev, out, sizeof(out), MLX5_PTYS_EN, 298 port_num); 299 if (err) 300 return err; 301 302 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 303 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 304 305 if (ext) 306 translate_eth_ext_proto_oper(eth_prot_oper, &props->active_speed, 307 &props->active_width); 308 else 309 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 310 &props->active_width); 311 312 props->port_cap_flags |= IB_PORT_CM_SUP; 313 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 314 315 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 316 roce_address_table_size); 317 props->max_mtu = IB_MTU_4096; 318 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 319 props->pkey_tbl_len = 1; 320 props->state = IB_PORT_DOWN; 321 props->phys_state = 3; 322 323 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 324 props->qkey_viol_cntr = qkey_viol_cntr; 325 326 ndev = mlx5_ib_get_netdev(device, port_num); 327 if (!ndev) 328 return 0; 329 330 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 331 props->state = IB_PORT_ACTIVE; 332 props->phys_state = 5; 333 } 334 335 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu); 336 337 dev_put(ndev); 338 339 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 340 return 0; 341} 342 343static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 344 const struct ib_gid_attr *attr, 345 void *mlx5_addr) 346{ 347#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 348 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 349 source_l3_address); 350 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 351 source_mac_47_32); 352 u16 vlan_id; 353 354 if (!gid) 355 return; 356 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev)); 357 358 vlan_id = rdma_vlan_dev_vlan_id(attr->ndev); 359 if (vlan_id != 0xffff) { 360 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 361 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id); 362 } 363 364 switch (attr->gid_type) { 365 case IB_GID_TYPE_IB: 366 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 367 break; 368 case IB_GID_TYPE_ROCE_UDP_ENCAP: 369 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 370 break; 371 372 default: 373 WARN_ON(true); 374 } 375 376 if (attr->gid_type != IB_GID_TYPE_IB) { 377 if (ipv6_addr_v4mapped((void *)gid)) 378 MLX5_SET_RA(mlx5_addr, roce_l3_type, 379 MLX5_ROCE_L3_TYPE_IPV4); 380 else 381 MLX5_SET_RA(mlx5_addr, roce_l3_type, 382 MLX5_ROCE_L3_TYPE_IPV6); 383 } 384 385 if ((attr->gid_type == IB_GID_TYPE_IB) || 386 !ipv6_addr_v4mapped((void *)gid)) 387 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 388 else 389 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 390} 391 392static int set_roce_addr(struct ib_device *device, u8 port_num, 393 unsigned int index, 394 const union ib_gid *gid, 395 const struct ib_gid_attr *attr) 396{ 397 struct mlx5_ib_dev *dev = to_mdev(device); 398 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 399 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 400 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 401 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 402 403 if (ll != IB_LINK_LAYER_ETHERNET) 404 return -EINVAL; 405 406 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 407 408 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 409 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 410 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 411} 412 413static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 414 unsigned int index, const union ib_gid *gid, 415 const struct ib_gid_attr *attr, 416 __always_unused void **context) 417{ 418 return set_roce_addr(device, port_num, index, gid, attr); 419} 420 421static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 422 unsigned int index, __always_unused void **context) 423{ 424 return set_roce_addr(device, port_num, index, NULL, NULL); 425} 426 427__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 428 int index) 429{ 430 struct ib_gid_attr attr; 431 union ib_gid gid; 432 433 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 434 return 0; 435 436 if (!attr.ndev) 437 return 0; 438 439 dev_put(attr.ndev); 440 441 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 442 return 0; 443 444 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 445} 446 447int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 448 int index, enum ib_gid_type *gid_type) 449{ 450 struct ib_gid_attr attr; 451 union ib_gid gid; 452 int ret; 453 454 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 455 if (ret) 456 return ret; 457 458 if (!attr.ndev) 459 return -ENODEV; 460 461 dev_put(attr.ndev); 462 463 *gid_type = attr.gid_type; 464 465 return 0; 466} 467 468static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 469{ 470 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 471 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 472 return 0; 473} 474 475enum { 476 MLX5_VPORT_ACCESS_METHOD_MAD, 477 MLX5_VPORT_ACCESS_METHOD_HCA, 478 MLX5_VPORT_ACCESS_METHOD_NIC, 479}; 480 481static int mlx5_get_vport_access_method(struct ib_device *ibdev) 482{ 483 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 484 return MLX5_VPORT_ACCESS_METHOD_MAD; 485 486 if (mlx5_ib_port_link_layer(ibdev, 1) == 487 IB_LINK_LAYER_ETHERNET) 488 return MLX5_VPORT_ACCESS_METHOD_NIC; 489 490 return MLX5_VPORT_ACCESS_METHOD_HCA; 491} 492 493static void get_atomic_caps(struct mlx5_ib_dev *dev, 494 struct ib_device_attr *props) 495{ 496 u8 tmp; 497 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 498 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 499 u8 atomic_req_8B_endianness_mode = 500 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 501 502 /* Check if HW supports 8 bytes standard atomic operations and capable 503 * of host endianness respond 504 */ 505 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 506 if (((atomic_operations & tmp) == tmp) && 507 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 508 (atomic_req_8B_endianness_mode)) { 509 props->atomic_cap = IB_ATOMIC_HCA; 510 } else { 511 props->atomic_cap = IB_ATOMIC_NONE; 512 } 513} 514 515static int mlx5_query_system_image_guid(struct ib_device *ibdev, 516 __be64 *sys_image_guid) 517{ 518 struct mlx5_ib_dev *dev = to_mdev(ibdev); 519 struct mlx5_core_dev *mdev = dev->mdev; 520 u64 tmp; 521 int err; 522 523 switch (mlx5_get_vport_access_method(ibdev)) { 524 case MLX5_VPORT_ACCESS_METHOD_MAD: 525 return mlx5_query_mad_ifc_system_image_guid(ibdev, 526 sys_image_guid); 527 528 case MLX5_VPORT_ACCESS_METHOD_HCA: 529 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 530 break; 531 532 case MLX5_VPORT_ACCESS_METHOD_NIC: 533 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 534 break; 535 536 default: 537 return -EINVAL; 538 } 539 540 if (!err) 541 *sys_image_guid = cpu_to_be64(tmp); 542 543 return err; 544 545} 546 547static int mlx5_query_max_pkeys(struct ib_device *ibdev, 548 u16 *max_pkeys) 549{ 550 struct mlx5_ib_dev *dev = to_mdev(ibdev); 551 struct mlx5_core_dev *mdev = dev->mdev; 552 553 switch (mlx5_get_vport_access_method(ibdev)) { 554 case MLX5_VPORT_ACCESS_METHOD_MAD: 555 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 556 557 case MLX5_VPORT_ACCESS_METHOD_HCA: 558 case MLX5_VPORT_ACCESS_METHOD_NIC: 559 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 560 pkey_table_size)); 561 return 0; 562 563 default: 564 return -EINVAL; 565 } 566} 567 568static int mlx5_query_vendor_id(struct ib_device *ibdev, 569 u32 *vendor_id) 570{ 571 struct mlx5_ib_dev *dev = to_mdev(ibdev); 572 573 switch (mlx5_get_vport_access_method(ibdev)) { 574 case MLX5_VPORT_ACCESS_METHOD_MAD: 575 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 576 577 case MLX5_VPORT_ACCESS_METHOD_HCA: 578 case MLX5_VPORT_ACCESS_METHOD_NIC: 579 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 580 581 default: 582 return -EINVAL; 583 } 584} 585 586static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 587 __be64 *node_guid) 588{ 589 u64 tmp; 590 int err; 591 592 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 593 case MLX5_VPORT_ACCESS_METHOD_MAD: 594 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 595 596 case MLX5_VPORT_ACCESS_METHOD_HCA: 597 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 598 break; 599 600 case MLX5_VPORT_ACCESS_METHOD_NIC: 601 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 602 break; 603 604 default: 605 return -EINVAL; 606 } 607 608 if (!err) 609 *node_guid = cpu_to_be64(tmp); 610 611 return err; 612} 613 614struct mlx5_reg_node_desc { 615 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 616}; 617 618static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 619{ 620 struct mlx5_reg_node_desc in; 621 622 if (mlx5_use_mad_ifc(dev)) 623 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 624 625 memset(&in, 0, sizeof(in)); 626 627 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 628 sizeof(struct mlx5_reg_node_desc), 629 MLX5_REG_NODE_DESC, 0, 0); 630} 631 632static int mlx5_ib_query_device(struct ib_device *ibdev, 633 struct ib_device_attr *props, 634 struct ib_udata *uhw) 635{ 636 struct mlx5_ib_dev *dev = to_mdev(ibdev); 637 struct mlx5_core_dev *mdev = dev->mdev; 638 int err = -ENOMEM; 639 int max_sq_desc; 640 int max_rq_sg; 641 int max_sq_sg; 642 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 643 struct mlx5_ib_query_device_resp resp = {}; 644 size_t resp_len; 645 u64 max_tso; 646 647 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 648 if (uhw->outlen && uhw->outlen < resp_len) 649 return -EINVAL; 650 else 651 resp.response_length = resp_len; 652 653 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 654 return -EINVAL; 655 656 memset(props, 0, sizeof(*props)); 657 err = mlx5_query_system_image_guid(ibdev, 658 &props->sys_image_guid); 659 if (err) 660 return err; 661 662 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 663 if (err) 664 return err; 665 666 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 667 if (err) 668 return err; 669 670 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 671 ((u32)fw_rev_min(dev->mdev) << 16) | 672 fw_rev_sub(dev->mdev); 673 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 674 IB_DEVICE_PORT_ACTIVE_EVENT | 675 IB_DEVICE_SYS_IMAGE_GUID | 676 IB_DEVICE_RC_RNR_NAK_GEN; 677 678 if (MLX5_CAP_GEN(mdev, pkv)) 679 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 680 if (MLX5_CAP_GEN(mdev, qkv)) 681 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 682 if (MLX5_CAP_GEN(mdev, apm)) 683 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 684 if (MLX5_CAP_GEN(mdev, xrc)) 685 props->device_cap_flags |= IB_DEVICE_XRC; 686 if (MLX5_CAP_GEN(mdev, imaicl)) { 687 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 688 IB_DEVICE_MEM_WINDOW_TYPE_2B; 689 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 690 /* We support 'Gappy' memory registration too */ 691 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 692 } 693 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 694 if (MLX5_CAP_GEN(mdev, sho)) { 695 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 696 /* At this stage no support for signature handover */ 697 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 698 IB_PROT_T10DIF_TYPE_2 | 699 IB_PROT_T10DIF_TYPE_3; 700 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 701 IB_GUARD_T10DIF_CSUM; 702 } 703 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 704 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 705 706 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 707 if (MLX5_CAP_ETH(mdev, csum_cap)) 708 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 709 710 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 711 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 712 if (max_tso) { 713 resp.tso_caps.max_tso = 1 << max_tso; 714 resp.tso_caps.supported_qpts |= 715 1 << IB_QPT_RAW_PACKET; 716 resp.response_length += sizeof(resp.tso_caps); 717 } 718 } 719 720 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 721 resp.rss_caps.rx_hash_function = 722 MLX5_RX_HASH_FUNC_TOEPLITZ; 723 resp.rss_caps.rx_hash_fields_mask = 724 MLX5_RX_HASH_SRC_IPV4 | 725 MLX5_RX_HASH_DST_IPV4 | 726 MLX5_RX_HASH_SRC_IPV6 | 727 MLX5_RX_HASH_DST_IPV6 | 728 MLX5_RX_HASH_SRC_PORT_TCP | 729 MLX5_RX_HASH_DST_PORT_TCP | 730 MLX5_RX_HASH_SRC_PORT_UDP | 731 MLX5_RX_HASH_DST_PORT_UDP; 732 resp.response_length += sizeof(resp.rss_caps); 733 } 734 } else { 735 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 736 resp.response_length += sizeof(resp.tso_caps); 737 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 738 resp.response_length += sizeof(resp.rss_caps); 739 } 740 741 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 742 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 743 props->device_cap_flags |= IB_DEVICE_UD_TSO; 744 } 745 746 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 747 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 748 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 749 750 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 751 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 752 753 props->vendor_part_id = mdev->pdev->device; 754 props->hw_ver = mdev->pdev->revision; 755 756 props->max_mr_size = ~0ull; 757 props->page_size_cap = ~(min_page_size - 1); 758 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 759 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 760 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 761 sizeof(struct mlx5_wqe_data_seg); 762 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 763 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 764 sizeof(struct mlx5_wqe_raddr_seg)) / 765 sizeof(struct mlx5_wqe_data_seg); 766 props->max_sge = min(max_rq_sg, max_sq_sg); 767 props->max_sge_rd = MLX5_MAX_SGE_RD; 768 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 769 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 770 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 771 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 772 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 773 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 774 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 775 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 776 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 777 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 778 props->max_srq_sge = max_rq_sg - 1; 779 props->max_fast_reg_page_list_len = 780 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 781 get_atomic_caps(dev, props); 782 props->masked_atomic_cap = IB_ATOMIC_NONE; 783 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 784 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 785 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 786 props->max_mcast_grp; 787 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 788 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 789 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 790 791#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 792 if (MLX5_CAP_GEN(mdev, pg)) 793 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 794 props->odp_caps = dev->odp_caps; 795#endif 796 797 if (MLX5_CAP_GEN(mdev, cd)) 798 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 799 800 if (!mlx5_core_is_pf(mdev)) 801 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 802 803 if (mlx5_ib_port_link_layer(ibdev, 1) == 804 IB_LINK_LAYER_ETHERNET) { 805 props->rss_caps.max_rwq_indirection_tables = 806 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 807 props->rss_caps.max_rwq_indirection_table_size = 808 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 809 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 810 props->max_wq_type_rq = 811 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 812 } 813 814 if (uhw->outlen) { 815 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 816 817 if (err) 818 return err; 819 } 820 821 return 0; 822} 823 824enum mlx5_ib_width { 825 MLX5_IB_WIDTH_1X = 1 << 0, 826 MLX5_IB_WIDTH_2X = 1 << 1, 827 MLX5_IB_WIDTH_4X = 1 << 2, 828 MLX5_IB_WIDTH_8X = 1 << 3, 829 MLX5_IB_WIDTH_12X = 1 << 4 830}; 831 832static int translate_active_width(struct ib_device *ibdev, u8 active_width, 833 u8 *ib_width) 834{ 835 struct mlx5_ib_dev *dev = to_mdev(ibdev); 836 int err = 0; 837 838 if (active_width & MLX5_IB_WIDTH_1X) { 839 *ib_width = IB_WIDTH_1X; 840 } else if (active_width & MLX5_IB_WIDTH_2X) { 841 *ib_width = IB_WIDTH_2X; 842 } else if (active_width & MLX5_IB_WIDTH_4X) { 843 *ib_width = IB_WIDTH_4X; 844 } else if (active_width & MLX5_IB_WIDTH_8X) { 845 *ib_width = IB_WIDTH_8X; 846 } else if (active_width & MLX5_IB_WIDTH_12X) { 847 *ib_width = IB_WIDTH_12X; 848 } else { 849 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 850 (int)active_width); 851 err = -EINVAL; 852 } 853 854 return err; 855} 856 857enum ib_max_vl_num { 858 __IB_MAX_VL_0 = 1, 859 __IB_MAX_VL_0_1 = 2, 860 __IB_MAX_VL_0_3 = 3, 861 __IB_MAX_VL_0_7 = 4, 862 __IB_MAX_VL_0_14 = 5, 863}; 864 865enum mlx5_vl_hw_cap { 866 MLX5_VL_HW_0 = 1, 867 MLX5_VL_HW_0_1 = 2, 868 MLX5_VL_HW_0_2 = 3, 869 MLX5_VL_HW_0_3 = 4, 870 MLX5_VL_HW_0_4 = 5, 871 MLX5_VL_HW_0_5 = 6, 872 MLX5_VL_HW_0_6 = 7, 873 MLX5_VL_HW_0_7 = 8, 874 MLX5_VL_HW_0_14 = 15 875}; 876 877static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 878 u8 *max_vl_num) 879{ 880 switch (vl_hw_cap) { 881 case MLX5_VL_HW_0: 882 *max_vl_num = __IB_MAX_VL_0; 883 break; 884 case MLX5_VL_HW_0_1: 885 *max_vl_num = __IB_MAX_VL_0_1; 886 break; 887 case MLX5_VL_HW_0_3: 888 *max_vl_num = __IB_MAX_VL_0_3; 889 break; 890 case MLX5_VL_HW_0_7: 891 *max_vl_num = __IB_MAX_VL_0_7; 892 break; 893 case MLX5_VL_HW_0_14: 894 *max_vl_num = __IB_MAX_VL_0_14; 895 break; 896 897 default: 898 return -EINVAL; 899 } 900 901 return 0; 902} 903 904static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 905 struct ib_port_attr *props) 906{ 907 struct mlx5_ib_dev *dev = to_mdev(ibdev); 908 struct mlx5_core_dev *mdev = dev->mdev; 909 u32 *rep; 910 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out); 911 struct mlx5_ptys_reg *ptys; 912 struct mlx5_pmtu_reg *pmtu; 913 struct mlx5_pvlc_reg pvlc; 914 void *ctx; 915 int err; 916 917 rep = mlx5_vzalloc(replen); 918 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL); 919 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL); 920 if (!rep || !ptys || !pmtu) { 921 err = -ENOMEM; 922 goto out; 923 } 924 925 memset(props, 0, sizeof(*props)); 926 927 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen); 928 if (err) 929 goto out; 930 931 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context); 932 933 props->lid = MLX5_GET(hca_vport_context, ctx, lid); 934 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc); 935 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid); 936 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl); 937 props->state = MLX5_GET(hca_vport_context, ctx, vport_state); 938 props->phys_state = MLX5_GET(hca_vport_context, ctx, 939 port_physical_state); 940 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1); 941 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 942 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 943 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 944 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx, 945 pkey_violation_counter); 946 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx, 947 qkey_violation_counter); 948 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx, 949 subnet_timeout); 950 props->init_type_reply = MLX5_GET(hca_vport_context, ctx, 951 init_type_reply); 952 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required); 953 954 ptys->proto_mask |= MLX5_PTYS_IB; 955 ptys->local_port = port; 956 err = mlx5_core_access_ptys(mdev, ptys, 0); 957 if (err) 958 goto out; 959 960 err = translate_active_width(ibdev, ptys->ib_link_width_oper, 961 &props->active_width); 962 if (err) 963 goto out; 964 965 props->active_speed = (u8)ptys->ib_proto_oper; 966 967 pmtu->local_port = port; 968 err = mlx5_core_access_pmtu(mdev, pmtu, 0); 969 if (err) 970 goto out; 971 972 props->max_mtu = pmtu->max_mtu; 973 props->active_mtu = pmtu->oper_mtu; 974 975 memset(&pvlc, 0, sizeof(pvlc)); 976 pvlc.local_port = port; 977 err = mlx5_core_access_pvlc(mdev, &pvlc, 0); 978 if (err) 979 goto out; 980 981 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap, 982 &props->max_vl_num); 983out: 984 kvfree(rep); 985 kfree(ptys); 986 kfree(pmtu); 987 return err; 988} 989 990int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 991 struct ib_port_attr *props) 992{ 993 switch (mlx5_get_vport_access_method(ibdev)) { 994 case MLX5_VPORT_ACCESS_METHOD_MAD: 995 return mlx5_query_mad_ifc_port(ibdev, port, props); 996 997 case MLX5_VPORT_ACCESS_METHOD_HCA: 998 return mlx5_query_hca_port(ibdev, port, props); 999 1000 case MLX5_VPORT_ACCESS_METHOD_NIC: 1001 return mlx5_query_port_roce(ibdev, port, props); 1002 1003 default: 1004 return -EINVAL; 1005 } 1006} 1007 1008static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1009 union ib_gid *gid) 1010{ 1011 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1012 struct mlx5_core_dev *mdev = dev->mdev; 1013 1014 switch (mlx5_get_vport_access_method(ibdev)) { 1015 case MLX5_VPORT_ACCESS_METHOD_MAD: 1016 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1017 1018 case MLX5_VPORT_ACCESS_METHOD_HCA: 1019 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid); 1020 1021 default: 1022 return -EINVAL; 1023 } 1024 1025} 1026 1027static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1028 u16 *pkey) 1029{ 1030 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1031 struct mlx5_core_dev *mdev = dev->mdev; 1032 1033 switch (mlx5_get_vport_access_method(ibdev)) { 1034 case MLX5_VPORT_ACCESS_METHOD_MAD: 1035 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1036 1037 case MLX5_VPORT_ACCESS_METHOD_HCA: 1038 case MLX5_VPORT_ACCESS_METHOD_NIC: 1039 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1040 pkey); 1041 default: 1042 return -EINVAL; 1043 } 1044} 1045 1046static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1047 struct ib_device_modify *props) 1048{ 1049 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1050 struct mlx5_reg_node_desc in; 1051 struct mlx5_reg_node_desc out; 1052 int err; 1053 1054 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1055 return -EOPNOTSUPP; 1056 1057 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1058 return 0; 1059 1060 /* 1061 * If possible, pass node desc to FW, so it can generate 1062 * a 144 trap. If cmd fails, just ignore. 1063 */ 1064 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1065 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1066 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1067 if (err) 1068 return err; 1069 1070 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1071 1072 return err; 1073} 1074 1075static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1076 struct ib_port_modify *props) 1077{ 1078 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1079 struct ib_port_attr attr; 1080 u32 tmp; 1081 int err; 1082 1083 /* 1084 * CM layer calls ib_modify_port() regardless of the link 1085 * layer. For Ethernet ports, qkey violation and Port 1086 * capabilities are meaningless. 1087 */ 1088 if (mlx5_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_ETHERNET) 1089 return 0; 1090 1091 mutex_lock(&dev->cap_mask_mutex); 1092 1093 err = mlx5_ib_query_port(ibdev, port, &attr); 1094 if (err) 1095 goto out; 1096 1097 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1098 ~props->clr_port_cap_mask; 1099 1100 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1101 1102out: 1103 mutex_unlock(&dev->cap_mask_mutex); 1104 return err; 1105} 1106 1107static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1108 struct ib_udata *udata) 1109{ 1110 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1111 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1112 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1113 struct mlx5_ib_ucontext *context; 1114 struct mlx5_uuar_info *uuari; 1115 struct mlx5_uar *uars; 1116 int gross_uuars; 1117 int num_uars; 1118 int ver; 1119 int uuarn; 1120 int err; 1121 int i; 1122 size_t reqlen; 1123 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1124 max_cqe_version); 1125 1126 if (!dev->ib_active) 1127 return ERR_PTR(-EAGAIN); 1128 1129 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1130 return ERR_PTR(-EINVAL); 1131 1132 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1133 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1134 ver = 0; 1135 else if (reqlen >= min_req_v2) 1136 ver = 2; 1137 else 1138 return ERR_PTR(-EINVAL); 1139 1140 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1141 if (err) 1142 return ERR_PTR(err); 1143 1144 if (req.flags) 1145 return ERR_PTR(-EINVAL); 1146 1147 if (req.total_num_uuars > MLX5_MAX_UUARS) 1148 return ERR_PTR(-ENOMEM); 1149 1150 if (req.total_num_uuars == 0) 1151 return ERR_PTR(-EINVAL); 1152 1153 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1154 return ERR_PTR(-EOPNOTSUPP); 1155 1156 if (reqlen > sizeof(req) && 1157 !ib_is_udata_cleared(udata, sizeof(req), 1158 reqlen - sizeof(req))) 1159 return ERR_PTR(-EOPNOTSUPP); 1160 1161 req.total_num_uuars = ALIGN(req.total_num_uuars, 1162 MLX5_NON_FP_BF_REGS_PER_PAGE); 1163 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 1164 return ERR_PTR(-EINVAL); 1165 1166 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 1167 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 1168 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1169 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1170 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1171 resp.cache_line_size = cache_line_size(); 1172 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1173 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1174 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1175 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1176 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1177 resp.cqe_version = min_t(__u8, 1178 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1179 req.max_cqe_version); 1180 resp.response_length = min(offsetof(typeof(resp), response_length) + 1181 sizeof(resp.response_length), udata->outlen); 1182 1183 context = kzalloc(sizeof(*context), GFP_KERNEL); 1184 if (!context) 1185 return ERR_PTR(-ENOMEM); 1186 1187 uuari = &context->uuari; 1188 mutex_init(&uuari->lock); 1189 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 1190 if (!uars) { 1191 err = -ENOMEM; 1192 goto out_ctx; 1193 } 1194 1195 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 1196 sizeof(*uuari->bitmap), 1197 GFP_KERNEL); 1198 if (!uuari->bitmap) { 1199 err = -ENOMEM; 1200 goto out_uar_ctx; 1201 } 1202 /* 1203 * clear all fast path uuars 1204 */ 1205 for (i = 0; i < gross_uuars; i++) { 1206 uuarn = i & 3; 1207 if (uuarn == 2 || uuarn == 3) 1208 set_bit(i, uuari->bitmap); 1209 } 1210 1211 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 1212 if (!uuari->count) { 1213 err = -ENOMEM; 1214 goto out_bitmap; 1215 } 1216 1217 for (i = 0; i < num_uars; i++) { 1218 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 1219 if (err) 1220 goto out_count; 1221 } 1222 1223#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1224 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1225#endif 1226 1227 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1228 err = mlx5_alloc_transport_domain(dev->mdev, 1229 &context->tdn); 1230 if (err) 1231 goto out_uars; 1232 } 1233 1234 INIT_LIST_HEAD(&context->vma_private_list); 1235 INIT_LIST_HEAD(&context->db_page_list); 1236 mutex_init(&context->db_page_mutex); 1237 1238 resp.tot_uuars = req.total_num_uuars; 1239 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1240 1241 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1242 resp.response_length += sizeof(resp.cqe_version); 1243 1244 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1245 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1246 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1247 resp.response_length += sizeof(resp.cmds_supp_uhw); 1248 } 1249 1250 /* 1251 * We don't want to expose information from the PCI bar that is located 1252 * after 4096 bytes, so if the arch only supports larger pages, let's 1253 * pretend we don't support reading the HCA's core clock. This is also 1254 * forced by mmap function. 1255 */ 1256 if (PAGE_SIZE <= 4096 && 1257 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1258 resp.comp_mask |= 1259 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1260 resp.hca_core_clock_offset = 1261 offsetof(struct mlx5_init_seg, internal_timer_h) % 1262 PAGE_SIZE; 1263 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1264 sizeof(resp.reserved2); 1265 } 1266 1267 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1268 if (err) 1269 goto out_td; 1270 1271 uuari->ver = ver; 1272 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1273 uuari->uars = uars; 1274 uuari->num_uars = num_uars; 1275 context->cqe_version = resp.cqe_version; 1276 1277 return &context->ibucontext; 1278 1279out_td: 1280 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1281 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1282 1283out_uars: 1284 for (i--; i >= 0; i--) 1285 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1286out_count: 1287 kfree(uuari->count); 1288 1289out_bitmap: 1290 kfree(uuari->bitmap); 1291 1292out_uar_ctx: 1293 kfree(uars); 1294 1295out_ctx: 1296 kfree(context); 1297 return ERR_PTR(err); 1298} 1299 1300static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1301{ 1302 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1303 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1304 struct mlx5_uuar_info *uuari = &context->uuari; 1305 int i; 1306 1307 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1308 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1309 1310 for (i = 0; i < uuari->num_uars; i++) { 1311 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1312 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1313 } 1314 1315 kfree(uuari->count); 1316 kfree(uuari->bitmap); 1317 kfree(uuari->uars); 1318 kfree(context); 1319 1320 return 0; 1321} 1322 1323static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1324{ 1325 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1326} 1327 1328static int get_command(unsigned long offset) 1329{ 1330 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1331} 1332 1333static int get_arg(unsigned long offset) 1334{ 1335 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1336} 1337 1338static int get_index(unsigned long offset) 1339{ 1340 return get_arg(offset); 1341} 1342 1343static void mlx5_ib_vma_open(struct vm_area_struct *area) 1344{ 1345 /* vma_open is called when a new VMA is created on top of our VMA. This 1346 * is done through either mremap flow or split_vma (usually due to 1347 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1348 * as this VMA is strongly hardware related. Therefore we set the 1349 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1350 * calling us again and trying to do incorrect actions. We assume that 1351 * the original VMA size is exactly a single page, and therefore all 1352 * "splitting" operation will not happen to it. 1353 */ 1354 area->vm_ops = NULL; 1355} 1356 1357static void mlx5_ib_vma_close(struct vm_area_struct *area) 1358{ 1359 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1360 1361 /* It's guaranteed that all VMAs opened on a FD are closed before the 1362 * file itself is closed, therefore no sync is needed with the regular 1363 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1364 * However need a sync with accessing the vma as part of 1365 * mlx5_ib_disassociate_ucontext. 1366 * The close operation is usually called under mm->mmap_sem except when 1367 * process is exiting. 1368 * The exiting case is handled explicitly as part of 1369 * mlx5_ib_disassociate_ucontext. 1370 */ 1371 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1372 1373 /* setting the vma context pointer to null in the mlx5_ib driver's 1374 * private data, to protect a race condition in 1375 * mlx5_ib_disassociate_ucontext(). 1376 */ 1377 mlx5_ib_vma_priv_data->vma = NULL; 1378 list_del(&mlx5_ib_vma_priv_data->list); 1379 kfree(mlx5_ib_vma_priv_data); 1380} 1381 1382static const struct vm_operations_struct mlx5_ib_vm_ops = { 1383 .open = mlx5_ib_vma_open, 1384 .close = mlx5_ib_vma_close 1385}; 1386 1387static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1388 struct mlx5_ib_ucontext *ctx) 1389{ 1390 struct mlx5_ib_vma_private_data *vma_prv; 1391 struct list_head *vma_head = &ctx->vma_private_list; 1392 1393 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1394 if (!vma_prv) 1395 return -ENOMEM; 1396 1397 vma_prv->vma = vma; 1398 vma->vm_private_data = vma_prv; 1399 vma->vm_ops = &mlx5_ib_vm_ops; 1400 1401 list_add(&vma_prv->list, vma_head); 1402 1403 return 0; 1404} 1405 1406static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1407{ 1408 int ret; 1409 struct vm_area_struct *vma; 1410 struct mlx5_ib_vma_private_data *vma_private, *n; 1411 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1412 struct task_struct *owning_process = NULL; 1413 struct mm_struct *owning_mm = NULL; 1414 1415 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1416 if (!owning_process) 1417 return; 1418 1419 owning_mm = get_task_mm(owning_process); 1420 if (!owning_mm) { 1421 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1422 while (1) { 1423 put_task_struct(owning_process); 1424 usleep_range(1000, 2000); 1425 owning_process = get_pid_task(ibcontext->tgid, 1426 PIDTYPE_PID); 1427 if (!owning_process || owning_process->task_thread-> 1428 td_proc->p_state == PRS_ZOMBIE) { 1429 pr_info("disassociate ucontext done, task was terminated\n"); 1430 /* in case task was dead need to release the 1431 * task struct. 1432 */ 1433 if (owning_process) 1434 put_task_struct(owning_process); 1435 return; 1436 } 1437 } 1438 } 1439 1440 /* need to protect from a race on closing the vma as part of 1441 * mlx5_ib_vma_close. 1442 */ 1443 down_write(&owning_mm->mmap_sem); 1444 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1445 list) { 1446 vma = vma_private->vma; 1447 ret = zap_vma_ptes(vma, vma->vm_start, 1448 PAGE_SIZE); 1449 if (ret == -ENOTSUP) { 1450 if (bootverbose) 1451 WARN_ONCE( 1452 "%s: zap_vma_ptes not implemented for unmanaged mappings", __func__); 1453 } else { 1454 WARN(ret, "%s: zap_vma_ptes failed, error %d", 1455 __func__, -ret); 1456 } 1457 /* context going to be destroyed, should 1458 * not access ops any more. 1459 */ 1460 /* XXXKIB vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); */ 1461 vma->vm_ops = NULL; 1462 list_del(&vma_private->list); 1463 kfree(vma_private); 1464 } 1465 up_write(&owning_mm->mmap_sem); 1466 mmput(owning_mm); 1467 put_task_struct(owning_process); 1468} 1469 1470static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1471{ 1472 switch (cmd) { 1473 case MLX5_IB_MMAP_WC_PAGE: 1474 return "WC"; 1475 case MLX5_IB_MMAP_REGULAR_PAGE: 1476 return "best effort WC"; 1477 case MLX5_IB_MMAP_NC_PAGE: 1478 return "NC"; 1479 default: 1480 return NULL; 1481 } 1482} 1483 1484static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1485 struct vm_area_struct *vma, 1486 struct mlx5_ib_ucontext *context) 1487{ 1488 struct mlx5_uuar_info *uuari = &context->uuari; 1489 int err; 1490 unsigned long idx; 1491 phys_addr_t pfn, pa; 1492 pgprot_t prot; 1493 1494 switch (cmd) { 1495 case MLX5_IB_MMAP_WC_PAGE: 1496/* Some architectures don't support WC memory */ 1497#if defined(CONFIG_X86) 1498 if (!pat_enabled()) 1499 return -EPERM; 1500#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1501 return -EPERM; 1502#endif 1503 /* fall through */ 1504 case MLX5_IB_MMAP_REGULAR_PAGE: 1505 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1506 prot = pgprot_writecombine(vma->vm_page_prot); 1507 break; 1508 case MLX5_IB_MMAP_NC_PAGE: 1509 prot = pgprot_noncached(vma->vm_page_prot); 1510 break; 1511 default: 1512 return -EINVAL; 1513 } 1514 1515 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1516 return -EINVAL; 1517 1518 idx = get_index(vma->vm_pgoff); 1519 if (idx >= uuari->num_uars) 1520 return -EINVAL; 1521 1522 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1523 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1524 1525 vma->vm_page_prot = prot; 1526 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1527 PAGE_SIZE, vma->vm_page_prot); 1528 if (err) { 1529 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n", 1530 err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1531 return -EAGAIN; 1532 } 1533 1534 pa = pfn << PAGE_SHIFT; 1535 mlx5_ib_dbg(dev, "mapped %s at 0x%llx, PA %pa\n", mmap_cmd2str(cmd), 1536 (unsigned long long)vma->vm_start, &pa); 1537 1538 return mlx5_ib_set_vma_data(vma, context); 1539} 1540 1541static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1542{ 1543 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1544 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1545 unsigned long command; 1546 phys_addr_t pfn; 1547 1548 command = get_command(vma->vm_pgoff); 1549 switch (command) { 1550 case MLX5_IB_MMAP_WC_PAGE: 1551 case MLX5_IB_MMAP_NC_PAGE: 1552 case MLX5_IB_MMAP_REGULAR_PAGE: 1553 return uar_mmap(dev, command, vma, context); 1554 1555 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1556 return -ENOSYS; 1557 1558 case MLX5_IB_MMAP_CORE_CLOCK: 1559 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1560 return -EINVAL; 1561 1562 if (vma->vm_flags & VM_WRITE) 1563 return -EPERM; 1564 1565 /* Don't expose to user-space information it shouldn't have */ 1566 if (PAGE_SIZE > 4096) 1567 return -EOPNOTSUPP; 1568 1569 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1570 pfn = (dev->mdev->iseg_base + 1571 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1572 PAGE_SHIFT; 1573 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1574 PAGE_SIZE, vma->vm_page_prot)) 1575 return -EAGAIN; 1576 1577 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n", 1578 (unsigned long long)vma->vm_start, 1579 (unsigned long long)pfn << PAGE_SHIFT); 1580 break; 1581 1582 default: 1583 return -EINVAL; 1584 } 1585 1586 return 0; 1587} 1588 1589static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1590 struct ib_ucontext *context, 1591 struct ib_udata *udata) 1592{ 1593 struct mlx5_ib_alloc_pd_resp resp; 1594 struct mlx5_ib_pd *pd; 1595 int err; 1596 1597 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1598 if (!pd) 1599 return ERR_PTR(-ENOMEM); 1600 1601 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1602 if (err) { 1603 kfree(pd); 1604 return ERR_PTR(err); 1605 } 1606 1607 if (context) { 1608 resp.pdn = pd->pdn; 1609 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1610 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1611 kfree(pd); 1612 return ERR_PTR(-EFAULT); 1613 } 1614 } 1615 1616 return &pd->ibpd; 1617} 1618 1619static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1620{ 1621 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1622 struct mlx5_ib_pd *mpd = to_mpd(pd); 1623 1624 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1625 kfree(mpd); 1626 1627 return 0; 1628} 1629 1630enum { 1631 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1632 MATCH_CRITERIA_ENABLE_MISC_BIT, 1633 MATCH_CRITERIA_ENABLE_INNER_BIT 1634}; 1635 1636#define HEADER_IS_ZERO(match_criteria, headers) \ 1637 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1638 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1639 1640static u8 get_match_criteria_enable(u32 *match_criteria) 1641{ 1642 u8 match_criteria_enable; 1643 1644 match_criteria_enable = 1645 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1646 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1647 match_criteria_enable |= 1648 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1649 MATCH_CRITERIA_ENABLE_MISC_BIT; 1650 match_criteria_enable |= 1651 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1652 MATCH_CRITERIA_ENABLE_INNER_BIT; 1653 1654 return match_criteria_enable; 1655} 1656 1657static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1658{ 1659 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1660 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1661} 1662 1663static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1664{ 1665 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1666 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1667 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1668 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1669} 1670 1671#define LAST_ETH_FIELD vlan_tag 1672#define LAST_IB_FIELD sl 1673#define LAST_IPV4_FIELD tos 1674#define LAST_IPV6_FIELD traffic_class 1675#define LAST_TCP_UDP_FIELD src_port 1676 1677/* Field is the last supported field */ 1678#define FIELDS_NOT_SUPPORTED(filter, field)\ 1679 memchr_inv((void *)&filter.field +\ 1680 sizeof(filter.field), 0,\ 1681 sizeof(filter) -\ 1682 offsetof(typeof(filter), field) -\ 1683 sizeof(filter.field)) 1684 1685static int parse_flow_attr(u32 *match_c, u32 *match_v, 1686 const union ib_flow_spec *ib_spec) 1687{ 1688 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1689 outer_headers); 1690 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1691 outer_headers); 1692 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1693 misc_parameters); 1694 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1695 misc_parameters); 1696 1697 switch (ib_spec->type) { 1698 case IB_FLOW_SPEC_ETH: 1699 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1700 return -ENOTSUPP; 1701 1702 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1703 dmac_47_16), 1704 ib_spec->eth.mask.dst_mac); 1705 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1706 dmac_47_16), 1707 ib_spec->eth.val.dst_mac); 1708 1709 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1710 smac_47_16), 1711 ib_spec->eth.mask.src_mac); 1712 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1713 smac_47_16), 1714 ib_spec->eth.val.src_mac); 1715 1716 if (ib_spec->eth.mask.vlan_tag) { 1717 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1718 cvlan_tag, 1); 1719 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1720 cvlan_tag, 1); 1721 1722 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1723 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1724 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1725 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1726 1727 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1728 first_cfi, 1729 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1730 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1731 first_cfi, 1732 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1733 1734 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1735 first_prio, 1736 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1737 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1738 first_prio, 1739 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1740 } 1741 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1742 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1743 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1744 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1745 break; 1746 case IB_FLOW_SPEC_IPV4: 1747 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1748 return -ENOTSUPP; 1749 1750 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1751 ethertype, 0xffff); 1752 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1753 ethertype, ETH_P_IP); 1754 1755 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1756 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1757 &ib_spec->ipv4.mask.src_ip, 1758 sizeof(ib_spec->ipv4.mask.src_ip)); 1759 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1760 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1761 &ib_spec->ipv4.val.src_ip, 1762 sizeof(ib_spec->ipv4.val.src_ip)); 1763 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1764 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1765 &ib_spec->ipv4.mask.dst_ip, 1766 sizeof(ib_spec->ipv4.mask.dst_ip)); 1767 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1768 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1769 &ib_spec->ipv4.val.dst_ip, 1770 sizeof(ib_spec->ipv4.val.dst_ip)); 1771 1772 set_tos(outer_headers_c, outer_headers_v, 1773 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1774 1775 set_proto(outer_headers_c, outer_headers_v, 1776 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1777 break; 1778 case IB_FLOW_SPEC_IPV6: 1779 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1780 return -ENOTSUPP; 1781 1782 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1783 ethertype, 0xffff); 1784 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1785 ethertype, IPPROTO_IPV6); 1786 1787 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1788 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1789 &ib_spec->ipv6.mask.src_ip, 1790 sizeof(ib_spec->ipv6.mask.src_ip)); 1791 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1792 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1793 &ib_spec->ipv6.val.src_ip, 1794 sizeof(ib_spec->ipv6.val.src_ip)); 1795 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1796 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1797 &ib_spec->ipv6.mask.dst_ip, 1798 sizeof(ib_spec->ipv6.mask.dst_ip)); 1799 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1800 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1801 &ib_spec->ipv6.val.dst_ip, 1802 sizeof(ib_spec->ipv6.val.dst_ip)); 1803 1804 set_tos(outer_headers_c, outer_headers_v, 1805 ib_spec->ipv6.mask.traffic_class, 1806 ib_spec->ipv6.val.traffic_class); 1807 1808 set_proto(outer_headers_c, outer_headers_v, 1809 ib_spec->ipv6.mask.next_hdr, 1810 ib_spec->ipv6.val.next_hdr); 1811 1812 MLX5_SET(fte_match_set_misc, misc_params_c, 1813 outer_ipv6_flow_label, 1814 ntohl(ib_spec->ipv6.mask.flow_label)); 1815 MLX5_SET(fte_match_set_misc, misc_params_v, 1816 outer_ipv6_flow_label, 1817 ntohl(ib_spec->ipv6.val.flow_label)); 1818 break; 1819 case IB_FLOW_SPEC_TCP: 1820 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1821 LAST_TCP_UDP_FIELD)) 1822 return -ENOTSUPP; 1823 1824 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1825 0xff); 1826 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1827 IPPROTO_TCP); 1828 1829 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1830 ntohs(ib_spec->tcp_udp.mask.src_port)); 1831 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1832 ntohs(ib_spec->tcp_udp.val.src_port)); 1833 1834 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1835 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1836 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1837 ntohs(ib_spec->tcp_udp.val.dst_port)); 1838 break; 1839 case IB_FLOW_SPEC_UDP: 1840 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1841 LAST_TCP_UDP_FIELD)) 1842 return -ENOTSUPP; 1843 1844 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1845 0xff); 1846 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1847 IPPROTO_UDP); 1848 1849 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1850 ntohs(ib_spec->tcp_udp.mask.src_port)); 1851 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1852 ntohs(ib_spec->tcp_udp.val.src_port)); 1853 1854 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1855 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1856 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1857 ntohs(ib_spec->tcp_udp.val.dst_port)); 1858 break; 1859 default: 1860 return -EINVAL; 1861 } 1862 1863 return 0; 1864} 1865 1866/* If a flow could catch both multicast and unicast packets, 1867 * it won't fall into the multicast flow steering table and this rule 1868 * could steal other multicast packets. 1869 */ 1870static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1871{ 1872 struct ib_flow_spec_eth *eth_spec; 1873 1874 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1875 ib_attr->size < sizeof(struct ib_flow_attr) + 1876 sizeof(struct ib_flow_spec_eth) || 1877 ib_attr->num_of_specs < 1) 1878 return false; 1879 1880 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1881 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1882 eth_spec->size != sizeof(*eth_spec)) 1883 return false; 1884 1885 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1886 is_multicast_ether_addr(eth_spec->val.dst_mac); 1887} 1888 1889static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 1890{ 1891 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1892 bool has_ipv4_spec = false; 1893 bool eth_type_ipv4 = true; 1894 unsigned int spec_index; 1895 1896 /* Validate that ethertype is correct */ 1897 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1898 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1899 ib_spec->eth.mask.ether_type) { 1900 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1901 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1902 eth_type_ipv4 = false; 1903 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1904 has_ipv4_spec = true; 1905 } 1906 ib_spec = (void *)ib_spec + ib_spec->size; 1907 } 1908 return !has_ipv4_spec || eth_type_ipv4; 1909} 1910 1911static void put_flow_table(struct mlx5_ib_dev *dev, 1912 struct mlx5_ib_flow_prio *prio, bool ft_added) 1913{ 1914 prio->refcount -= !!ft_added; 1915 if (!prio->refcount) { 1916 mlx5_destroy_flow_table(prio->flow_table); 1917 prio->flow_table = NULL; 1918 } 1919} 1920 1921static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1922{ 1923 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1924 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1925 struct mlx5_ib_flow_handler, 1926 ibflow); 1927 struct mlx5_ib_flow_handler *iter, *tmp; 1928 1929 mutex_lock(&dev->flow_db.lock); 1930 1931 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1932 mlx5_del_flow_rule(iter->rule); 1933 put_flow_table(dev, iter->prio, true); 1934 list_del(&iter->list); 1935 kfree(iter); 1936 } 1937 1938 mlx5_del_flow_rule(handler->rule); 1939 put_flow_table(dev, handler->prio, true); 1940 mutex_unlock(&dev->flow_db.lock); 1941 1942 kfree(handler); 1943 1944 return 0; 1945} 1946 1947static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1948{ 1949 priority *= 2; 1950 if (!dont_trap) 1951 priority++; 1952 return priority; 1953} 1954 1955enum flow_table_type { 1956 MLX5_IB_FT_RX, 1957 MLX5_IB_FT_TX 1958}; 1959 1960#define MLX5_FS_MAX_TYPES 10 1961#define MLX5_FS_MAX_ENTRIES 32000UL 1962static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1963 struct ib_flow_attr *flow_attr, 1964 enum flow_table_type ft_type) 1965{ 1966 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1967 struct mlx5_flow_namespace *ns = NULL; 1968 struct mlx5_ib_flow_prio *prio; 1969 struct mlx5_flow_table *ft; 1970 int num_entries; 1971 int num_groups; 1972 int priority; 1973 int err = 0; 1974 1975 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1976 if (flow_is_multicast_only(flow_attr) && 1977 !dont_trap) 1978 priority = MLX5_IB_FLOW_MCAST_PRIO; 1979 else 1980 priority = ib_prio_to_core_prio(flow_attr->priority, 1981 dont_trap); 1982 ns = mlx5_get_flow_namespace(dev->mdev, 1983 MLX5_FLOW_NAMESPACE_BYPASS); 1984 num_entries = MLX5_FS_MAX_ENTRIES; 1985 num_groups = MLX5_FS_MAX_TYPES; 1986 prio = &dev->flow_db.prios[priority]; 1987 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1988 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1989 ns = mlx5_get_flow_namespace(dev->mdev, 1990 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1991 build_leftovers_ft_param("bypass", &priority, 1992 &num_entries, 1993 &num_groups); 1994 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1995 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 1996 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 1997 allow_sniffer_and_nic_rx_shared_tir)) 1998 return ERR_PTR(-ENOTSUPP); 1999 2000 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2001 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2002 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2003 2004 prio = &dev->flow_db.sniffer[ft_type]; 2005 priority = 0; 2006 num_entries = 1; 2007 num_groups = 1; 2008 } 2009 2010 if (!ns) 2011 return ERR_PTR(-ENOTSUPP); 2012 2013 ft = prio->flow_table; 2014 if (!ft) { 2015 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass", 2016 num_entries, 2017 num_groups); 2018 2019 if (!IS_ERR(ft)) { 2020 prio->refcount = 0; 2021 prio->flow_table = ft; 2022 } else { 2023 err = PTR_ERR(ft); 2024 } 2025 } 2026 2027 return err ? ERR_PTR(err) : prio; 2028} 2029 2030static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2031 struct mlx5_ib_flow_prio *ft_prio, 2032 const struct ib_flow_attr *flow_attr, 2033 struct mlx5_flow_destination *dst) 2034{ 2035 struct mlx5_flow_table *ft = ft_prio->flow_table; 2036 struct mlx5_ib_flow_handler *handler; 2037 struct mlx5_flow_spec *spec; 2038 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2039 unsigned int spec_index; 2040 u32 action; 2041 int err = 0; 2042 2043 if (!is_valid_attr(flow_attr)) 2044 return ERR_PTR(-EINVAL); 2045 2046 spec = mlx5_vzalloc(sizeof(*spec)); 2047 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2048 if (!handler || !spec) { 2049 err = -ENOMEM; 2050 goto free; 2051 } 2052 2053 INIT_LIST_HEAD(&handler->list); 2054 2055 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2056 err = parse_flow_attr(spec->match_criteria, 2057 spec->match_value, ib_flow); 2058 if (err < 0) 2059 goto free; 2060 2061 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2062 } 2063 2064 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2065 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2066 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2067 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable, 2068 spec->match_criteria, 2069 spec->match_value, 2070 action, 2071 MLX5_FS_DEFAULT_FLOW_TAG, 2072 dst); 2073 2074 if (IS_ERR(handler->rule)) { 2075 err = PTR_ERR(handler->rule); 2076 goto free; 2077 } 2078 2079 ft_prio->refcount++; 2080 handler->prio = ft_prio; 2081 2082 ft_prio->flow_table = ft; 2083free: 2084 if (err) 2085 kfree(handler); 2086 kvfree(spec); 2087 return err ? ERR_PTR(err) : handler; 2088} 2089 2090static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2091 struct mlx5_ib_flow_prio *ft_prio, 2092 struct ib_flow_attr *flow_attr, 2093 struct mlx5_flow_destination *dst) 2094{ 2095 struct mlx5_ib_flow_handler *handler_dst = NULL; 2096 struct mlx5_ib_flow_handler *handler = NULL; 2097 2098 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2099 if (!IS_ERR(handler)) { 2100 handler_dst = create_flow_rule(dev, ft_prio, 2101 flow_attr, dst); 2102 if (IS_ERR(handler_dst)) { 2103 mlx5_del_flow_rule(handler->rule); 2104 ft_prio->refcount--; 2105 kfree(handler); 2106 handler = handler_dst; 2107 } else { 2108 list_add(&handler_dst->list, &handler->list); 2109 } 2110 } 2111 2112 return handler; 2113} 2114enum { 2115 LEFTOVERS_MC, 2116 LEFTOVERS_UC, 2117}; 2118 2119static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2120 struct mlx5_ib_flow_prio *ft_prio, 2121 struct ib_flow_attr *flow_attr, 2122 struct mlx5_flow_destination *dst) 2123{ 2124 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2125 struct mlx5_ib_flow_handler *handler = NULL; 2126 2127 static struct { 2128 struct ib_flow_attr flow_attr; 2129 struct ib_flow_spec_eth eth_flow; 2130 } leftovers_specs[] = { 2131 [LEFTOVERS_MC] = { 2132 .flow_attr = { 2133 .num_of_specs = 1, 2134 .size = sizeof(leftovers_specs[0]) 2135 }, 2136 .eth_flow = { 2137 .type = IB_FLOW_SPEC_ETH, 2138 .size = sizeof(struct ib_flow_spec_eth), 2139 .mask = {.dst_mac = {0x1} }, 2140 .val = {.dst_mac = {0x1} } 2141 } 2142 }, 2143 [LEFTOVERS_UC] = { 2144 .flow_attr = { 2145 .num_of_specs = 1, 2146 .size = sizeof(leftovers_specs[0]) 2147 }, 2148 .eth_flow = { 2149 .type = IB_FLOW_SPEC_ETH, 2150 .size = sizeof(struct ib_flow_spec_eth), 2151 .mask = {.dst_mac = {0x1} }, 2152 .val = {.dst_mac = {} } 2153 } 2154 } 2155 }; 2156 2157 handler = create_flow_rule(dev, ft_prio, 2158 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2159 dst); 2160 if (!IS_ERR(handler) && 2161 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2162 handler_ucast = create_flow_rule(dev, ft_prio, 2163 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2164 dst); 2165 if (IS_ERR(handler_ucast)) { 2166 mlx5_del_flow_rule(handler->rule); 2167 ft_prio->refcount--; 2168 kfree(handler); 2169 handler = handler_ucast; 2170 } else { 2171 list_add(&handler_ucast->list, &handler->list); 2172 } 2173 } 2174 2175 return handler; 2176} 2177 2178static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2179 struct mlx5_ib_flow_prio *ft_rx, 2180 struct mlx5_ib_flow_prio *ft_tx, 2181 struct mlx5_flow_destination *dst) 2182{ 2183 struct mlx5_ib_flow_handler *handler_rx; 2184 struct mlx5_ib_flow_handler *handler_tx; 2185 int err; 2186 static const struct ib_flow_attr flow_attr = { 2187 .num_of_specs = 0, 2188 .size = sizeof(flow_attr) 2189 }; 2190 2191 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2192 if (IS_ERR(handler_rx)) { 2193 err = PTR_ERR(handler_rx); 2194 goto err; 2195 } 2196 2197 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2198 if (IS_ERR(handler_tx)) { 2199 err = PTR_ERR(handler_tx); 2200 goto err_tx; 2201 } 2202 2203 list_add(&handler_tx->list, &handler_rx->list); 2204 2205 return handler_rx; 2206 2207err_tx: 2208 mlx5_del_flow_rule(handler_rx->rule); 2209 ft_rx->refcount--; 2210 kfree(handler_rx); 2211err: 2212 return ERR_PTR(err); 2213} 2214 2215static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2216 struct ib_flow_attr *flow_attr, 2217 int domain) 2218{ 2219 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2220 struct mlx5_ib_qp *mqp = to_mqp(qp); 2221 struct mlx5_ib_flow_handler *handler = NULL; 2222 struct mlx5_flow_destination *dst = NULL; 2223 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2224 struct mlx5_ib_flow_prio *ft_prio; 2225 int err; 2226 2227 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2228 return ERR_PTR(-ENOSPC); 2229 2230 if (domain != IB_FLOW_DOMAIN_USER || 2231 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2232 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2233 return ERR_PTR(-EINVAL); 2234 2235 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2236 if (!dst) 2237 return ERR_PTR(-ENOMEM); 2238 2239 mutex_lock(&dev->flow_db.lock); 2240 2241 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2242 if (IS_ERR(ft_prio)) { 2243 err = PTR_ERR(ft_prio); 2244 goto unlock; 2245 } 2246 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2247 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2248 if (IS_ERR(ft_prio_tx)) { 2249 err = PTR_ERR(ft_prio_tx); 2250 ft_prio_tx = NULL; 2251 goto destroy_ft; 2252 } 2253 } 2254 2255 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2256 if (mqp->flags & MLX5_IB_QP_RSS) 2257 dst->tir_num = mqp->rss_qp.tirn; 2258 else 2259 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2260 2261 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2262 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2263 handler = create_dont_trap_rule(dev, ft_prio, 2264 flow_attr, dst); 2265 } else { 2266 handler = create_flow_rule(dev, ft_prio, flow_attr, 2267 dst); 2268 } 2269 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2270 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2271 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2272 dst); 2273 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2274 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2275 } else { 2276 err = -EINVAL; 2277 goto destroy_ft; 2278 } 2279 2280 if (IS_ERR(handler)) { 2281 err = PTR_ERR(handler); 2282 handler = NULL; 2283 goto destroy_ft; 2284 } 2285 2286 mutex_unlock(&dev->flow_db.lock); 2287 kfree(dst); 2288 2289 return &handler->ibflow; 2290 2291destroy_ft: 2292 put_flow_table(dev, ft_prio, false); 2293 if (ft_prio_tx) 2294 put_flow_table(dev, ft_prio_tx, false); 2295unlock: 2296 mutex_unlock(&dev->flow_db.lock); 2297 kfree(dst); 2298 kfree(handler); 2299 return ERR_PTR(err); 2300} 2301 2302static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2303{ 2304 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2305 int err; 2306 2307 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2308 if (err) 2309 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2310 ibqp->qp_num, gid->raw); 2311 2312 return err; 2313} 2314 2315static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2316{ 2317 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2318 int err; 2319 2320 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2321 if (err) 2322 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2323 ibqp->qp_num, gid->raw); 2324 2325 return err; 2326} 2327 2328static int init_node_data(struct mlx5_ib_dev *dev) 2329{ 2330 int err; 2331 2332 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2333 if (err) 2334 return err; 2335 2336 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2337} 2338 2339static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2340 char *buf) 2341{ 2342 struct mlx5_ib_dev *dev = 2343 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2344 2345 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages); 2346} 2347 2348static ssize_t show_reg_pages(struct device *device, 2349 struct device_attribute *attr, char *buf) 2350{ 2351 struct mlx5_ib_dev *dev = 2352 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2353 2354 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2355} 2356 2357static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2358 char *buf) 2359{ 2360 struct mlx5_ib_dev *dev = 2361 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2362 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2363} 2364 2365static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2366 char *buf) 2367{ 2368 struct mlx5_ib_dev *dev = 2369 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2370 return sprintf(buf, "%x\n", dev->mdev->pdev->revision); 2371} 2372 2373static ssize_t show_board(struct device *device, struct device_attribute *attr, 2374 char *buf) 2375{ 2376 struct mlx5_ib_dev *dev = 2377 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2378 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2379 dev->mdev->board_id); 2380} 2381 2382static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2383static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2384static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2385static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2386static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2387 2388static struct device_attribute *mlx5_class_attributes[] = { 2389 &dev_attr_hw_rev, 2390 &dev_attr_hca_type, 2391 &dev_attr_board_id, 2392 &dev_attr_fw_pages, 2393 &dev_attr_reg_pages, 2394}; 2395 2396static void pkey_change_handler(struct work_struct *work) 2397{ 2398 struct mlx5_ib_port_resources *ports = 2399 container_of(work, struct mlx5_ib_port_resources, 2400 pkey_change_work); 2401 2402 mutex_lock(&ports->devr->mutex); 2403 mlx5_ib_gsi_pkey_change(ports->gsi); 2404 mutex_unlock(&ports->devr->mutex); 2405} 2406 2407static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2408{ 2409 struct mlx5_ib_qp *mqp; 2410 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2411 struct mlx5_core_cq *mcq; 2412 struct list_head cq_armed_list; 2413 unsigned long flags_qp; 2414 unsigned long flags_cq; 2415 unsigned long flags; 2416 2417 INIT_LIST_HEAD(&cq_armed_list); 2418 2419 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2420 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2421 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2422 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2423 if (mqp->sq.tail != mqp->sq.head) { 2424 send_mcq = to_mcq(mqp->ibqp.send_cq); 2425 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2426 if (send_mcq->mcq.comp && 2427 mqp->ibqp.send_cq->comp_handler) { 2428 if (!send_mcq->mcq.reset_notify_added) { 2429 send_mcq->mcq.reset_notify_added = 1; 2430 list_add_tail(&send_mcq->mcq.reset_notify, 2431 &cq_armed_list); 2432 } 2433 } 2434 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2435 } 2436 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2437 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2438 /* no handling is needed for SRQ */ 2439 if (!mqp->ibqp.srq) { 2440 if (mqp->rq.tail != mqp->rq.head) { 2441 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2442 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2443 if (recv_mcq->mcq.comp && 2444 mqp->ibqp.recv_cq->comp_handler) { 2445 if (!recv_mcq->mcq.reset_notify_added) { 2446 recv_mcq->mcq.reset_notify_added = 1; 2447 list_add_tail(&recv_mcq->mcq.reset_notify, 2448 &cq_armed_list); 2449 } 2450 } 2451 spin_unlock_irqrestore(&recv_mcq->lock, 2452 flags_cq); 2453 } 2454 } 2455 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2456 } 2457 /*At that point all inflight post send were put to be executed as of we 2458 * lock/unlock above locks Now need to arm all involved CQs. 2459 */ 2460 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2461 mcq->comp(mcq); 2462 } 2463 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2464} 2465 2466static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2467 enum mlx5_dev_event event, unsigned long param) 2468{ 2469 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2470 struct ib_event ibev; 2471 bool fatal = false; 2472 u8 port = (u8)param; 2473 2474 switch (event) { 2475 case MLX5_DEV_EVENT_SYS_ERROR: 2476 ibev.event = IB_EVENT_DEVICE_FATAL; 2477 mlx5_ib_handle_internal_error(ibdev); 2478 fatal = true; 2479 break; 2480 2481 case MLX5_DEV_EVENT_PORT_UP: 2482 case MLX5_DEV_EVENT_PORT_DOWN: 2483 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2484 /* In RoCE, port up/down events are handled in 2485 * mlx5_netdev_event(). 2486 */ 2487 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2488 IB_LINK_LAYER_ETHERNET) 2489 return; 2490 2491 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2492 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2493 break; 2494 2495 case MLX5_DEV_EVENT_LID_CHANGE: 2496 ibev.event = IB_EVENT_LID_CHANGE; 2497 break; 2498 2499 case MLX5_DEV_EVENT_PKEY_CHANGE: 2500 ibev.event = IB_EVENT_PKEY_CHANGE; 2501 2502 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2503 break; 2504 2505 case MLX5_DEV_EVENT_GUID_CHANGE: 2506 ibev.event = IB_EVENT_GID_CHANGE; 2507 break; 2508 2509 case MLX5_DEV_EVENT_CLIENT_REREG: 2510 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2511 break; 2512 2513 default: 2514 /* unsupported event */ 2515 return; 2516 } 2517 2518 ibev.device = &ibdev->ib_dev; 2519 ibev.element.port_num = port; 2520 2521 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 2522 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port); 2523 return; 2524 } 2525 2526 if (ibdev->ib_active) 2527 ib_dispatch_event(&ibev); 2528 2529 if (fatal) 2530 ibdev->ib_active = false; 2531} 2532 2533static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2534{ 2535 int port; 2536 2537 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2538 mlx5_query_ext_port_caps(dev, port); 2539} 2540 2541static int get_port_caps(struct mlx5_ib_dev *dev) 2542{ 2543 struct ib_device_attr *dprops = NULL; 2544 struct ib_port_attr *pprops = NULL; 2545 int err = -ENOMEM; 2546 int port; 2547 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2548 2549 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2550 if (!pprops) 2551 goto out; 2552 2553 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2554 if (!dprops) 2555 goto out; 2556 2557 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2558 if (err) { 2559 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2560 goto out; 2561 } 2562 2563 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2564 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2565 if (err) { 2566 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2567 port, err); 2568 break; 2569 } 2570 dev->mdev->port_caps[port - 1].pkey_table_len = 2571 dprops->max_pkeys; 2572 dev->mdev->port_caps[port - 1].gid_table_len = 2573 pprops->gid_tbl_len; 2574 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2575 dprops->max_pkeys, pprops->gid_tbl_len); 2576 } 2577 2578out: 2579 kfree(pprops); 2580 kfree(dprops); 2581 2582 return err; 2583} 2584 2585static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2586{ 2587 int err; 2588 2589 err = mlx5_mr_cache_cleanup(dev); 2590 if (err) 2591 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2592 2593 mlx5_ib_destroy_qp(dev->umrc.qp); 2594 ib_free_cq(dev->umrc.cq); 2595 ib_dealloc_pd(dev->umrc.pd); 2596} 2597 2598enum { 2599 MAX_UMR_WR = 128, 2600}; 2601 2602static int create_umr_res(struct mlx5_ib_dev *dev) 2603{ 2604 struct ib_qp_init_attr *init_attr = NULL; 2605 struct ib_qp_attr *attr = NULL; 2606 struct ib_pd *pd; 2607 struct ib_cq *cq; 2608 struct ib_qp *qp; 2609 int ret; 2610 2611 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2612 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2613 if (!attr || !init_attr) { 2614 ret = -ENOMEM; 2615 goto error_0; 2616 } 2617 2618 pd = ib_alloc_pd(&dev->ib_dev, 0); 2619 if (IS_ERR(pd)) { 2620 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2621 ret = PTR_ERR(pd); 2622 goto error_0; 2623 } 2624 2625 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2626 if (IS_ERR(cq)) { 2627 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2628 ret = PTR_ERR(cq); 2629 goto error_2; 2630 } 2631 2632 init_attr->send_cq = cq; 2633 init_attr->recv_cq = cq; 2634 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2635 init_attr->cap.max_send_wr = MAX_UMR_WR; 2636 init_attr->cap.max_send_sge = 1; 2637 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2638 init_attr->port_num = 1; 2639 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2640 if (IS_ERR(qp)) { 2641 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2642 ret = PTR_ERR(qp); 2643 goto error_3; 2644 } 2645 qp->device = &dev->ib_dev; 2646 qp->real_qp = qp; 2647 qp->uobject = NULL; 2648 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2649 2650 attr->qp_state = IB_QPS_INIT; 2651 attr->port_num = 1; 2652 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2653 IB_QP_PORT, NULL); 2654 if (ret) { 2655 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2656 goto error_4; 2657 } 2658 2659 memset(attr, 0, sizeof(*attr)); 2660 attr->qp_state = IB_QPS_RTR; 2661 attr->path_mtu = IB_MTU_256; 2662 2663 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2664 if (ret) { 2665 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2666 goto error_4; 2667 } 2668 2669 memset(attr, 0, sizeof(*attr)); 2670 attr->qp_state = IB_QPS_RTS; 2671 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2672 if (ret) { 2673 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2674 goto error_4; 2675 } 2676 2677 dev->umrc.qp = qp; 2678 dev->umrc.cq = cq; 2679 dev->umrc.pd = pd; 2680 2681 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2682 ret = mlx5_mr_cache_init(dev); 2683 if (ret) { 2684 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2685 goto error_4; 2686 } 2687 2688 kfree(attr); 2689 kfree(init_attr); 2690 2691 return 0; 2692 2693error_4: 2694 mlx5_ib_destroy_qp(qp); 2695 2696error_3: 2697 ib_free_cq(cq); 2698 2699error_2: 2700 ib_dealloc_pd(pd); 2701 2702error_0: 2703 kfree(attr); 2704 kfree(init_attr); 2705 return ret; 2706} 2707 2708static int create_dev_resources(struct mlx5_ib_resources *devr) 2709{ 2710 struct ib_srq_init_attr attr; 2711 struct mlx5_ib_dev *dev; 2712 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2713 int port; 2714 int ret = 0; 2715 2716 dev = container_of(devr, struct mlx5_ib_dev, devr); 2717 2718 mutex_init(&devr->mutex); 2719 2720 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2721 if (IS_ERR(devr->p0)) { 2722 ret = PTR_ERR(devr->p0); 2723 goto error0; 2724 } 2725 devr->p0->device = &dev->ib_dev; 2726 devr->p0->uobject = NULL; 2727 atomic_set(&devr->p0->usecnt, 0); 2728 2729 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2730 if (IS_ERR(devr->c0)) { 2731 ret = PTR_ERR(devr->c0); 2732 goto error1; 2733 } 2734 devr->c0->device = &dev->ib_dev; 2735 devr->c0->uobject = NULL; 2736 devr->c0->comp_handler = NULL; 2737 devr->c0->event_handler = NULL; 2738 devr->c0->cq_context = NULL; 2739 atomic_set(&devr->c0->usecnt, 0); 2740 2741 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2742 if (IS_ERR(devr->x0)) { 2743 ret = PTR_ERR(devr->x0); 2744 goto error2; 2745 } 2746 devr->x0->device = &dev->ib_dev; 2747 devr->x0->inode = NULL; 2748 atomic_set(&devr->x0->usecnt, 0); 2749 mutex_init(&devr->x0->tgt_qp_mutex); 2750 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2751 2752 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2753 if (IS_ERR(devr->x1)) { 2754 ret = PTR_ERR(devr->x1); 2755 goto error3; 2756 } 2757 devr->x1->device = &dev->ib_dev; 2758 devr->x1->inode = NULL; 2759 atomic_set(&devr->x1->usecnt, 0); 2760 mutex_init(&devr->x1->tgt_qp_mutex); 2761 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2762 2763 memset(&attr, 0, sizeof(attr)); 2764 attr.attr.max_sge = 1; 2765 attr.attr.max_wr = 1; 2766 attr.srq_type = IB_SRQT_XRC; 2767 attr.ext.xrc.cq = devr->c0; 2768 attr.ext.xrc.xrcd = devr->x0; 2769 2770 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2771 if (IS_ERR(devr->s0)) { 2772 ret = PTR_ERR(devr->s0); 2773 goto error4; 2774 } 2775 devr->s0->device = &dev->ib_dev; 2776 devr->s0->pd = devr->p0; 2777 devr->s0->uobject = NULL; 2778 devr->s0->event_handler = NULL; 2779 devr->s0->srq_context = NULL; 2780 devr->s0->srq_type = IB_SRQT_XRC; 2781 devr->s0->ext.xrc.xrcd = devr->x0; 2782 devr->s0->ext.xrc.cq = devr->c0; 2783 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2784 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2785 atomic_inc(&devr->p0->usecnt); 2786 atomic_set(&devr->s0->usecnt, 0); 2787 2788 memset(&attr, 0, sizeof(attr)); 2789 attr.attr.max_sge = 1; 2790 attr.attr.max_wr = 1; 2791 attr.srq_type = IB_SRQT_BASIC; 2792 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2793 if (IS_ERR(devr->s1)) { 2794 ret = PTR_ERR(devr->s1); 2795 goto error5; 2796 } 2797 devr->s1->device = &dev->ib_dev; 2798 devr->s1->pd = devr->p0; 2799 devr->s1->uobject = NULL; 2800 devr->s1->event_handler = NULL; 2801 devr->s1->srq_context = NULL; 2802 devr->s1->srq_type = IB_SRQT_BASIC; 2803 devr->s1->ext.xrc.cq = devr->c0; 2804 atomic_inc(&devr->p0->usecnt); 2805 atomic_set(&devr->s0->usecnt, 0); 2806 2807 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2808 INIT_WORK(&devr->ports[port].pkey_change_work, 2809 pkey_change_handler); 2810 devr->ports[port].devr = devr; 2811 } 2812 2813 return 0; 2814 2815error5: 2816 mlx5_ib_destroy_srq(devr->s0); 2817error4: 2818 mlx5_ib_dealloc_xrcd(devr->x1); 2819error3: 2820 mlx5_ib_dealloc_xrcd(devr->x0); 2821error2: 2822 mlx5_ib_destroy_cq(devr->c0); 2823error1: 2824 mlx5_ib_dealloc_pd(devr->p0); 2825error0: 2826 return ret; 2827} 2828 2829static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2830{ 2831 struct mlx5_ib_dev *dev = 2832 container_of(devr, struct mlx5_ib_dev, devr); 2833 int port; 2834 2835 mlx5_ib_destroy_srq(devr->s1); 2836 mlx5_ib_destroy_srq(devr->s0); 2837 mlx5_ib_dealloc_xrcd(devr->x0); 2838 mlx5_ib_dealloc_xrcd(devr->x1); 2839 mlx5_ib_destroy_cq(devr->c0); 2840 mlx5_ib_dealloc_pd(devr->p0); 2841 2842 /* Make sure no change P_Key work items are still executing */ 2843 for (port = 0; port < dev->num_ports; ++port) 2844 cancel_work_sync(&devr->ports[port].pkey_change_work); 2845} 2846 2847static u32 get_core_cap_flags(struct ib_device *ibdev) 2848{ 2849 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2850 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2851 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2852 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2853 u32 ret = 0; 2854 2855 if (ll == IB_LINK_LAYER_INFINIBAND) 2856 return RDMA_CORE_PORT_IBA_IB; 2857 2858 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2859 return 0; 2860 2861 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2862 return 0; 2863 2864 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2865 ret |= RDMA_CORE_PORT_IBA_ROCE; 2866 2867 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2868 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2869 2870 return ret; 2871} 2872 2873static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2874 struct ib_port_immutable *immutable) 2875{ 2876 struct ib_port_attr attr; 2877 int err; 2878 2879 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2880 if (err) 2881 return err; 2882 2883 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2884 immutable->gid_tbl_len = attr.gid_tbl_len; 2885 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2886 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2887 2888 return 0; 2889} 2890 2891static void get_dev_fw_str(struct ib_device *ibdev, char *str, 2892 size_t str_len) 2893{ 2894 struct mlx5_ib_dev *dev = 2895 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2896 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 2897 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 2898} 2899 2900static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev) 2901{ 2902 return 0; 2903} 2904 2905static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev) 2906{ 2907} 2908 2909static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev) 2910{ 2911 if (dev->roce.nb.notifier_call) { 2912 unregister_netdevice_notifier(&dev->roce.nb); 2913 dev->roce.nb.notifier_call = NULL; 2914 } 2915} 2916 2917static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2918{ 2919 VNET_ITERATOR_DECL(vnet_iter); 2920 struct net_device *idev; 2921 int err; 2922 2923 /* Check if mlx5en net device already exists */ 2924 VNET_LIST_RLOCK(); 2925 VNET_FOREACH(vnet_iter) { 2926 IFNET_RLOCK(); 2927 CURVNET_SET_QUIET(vnet_iter); 2928 TAILQ_FOREACH(idev, &V_ifnet, if_link) { 2929 /* check if network interface belongs to mlx5en */ 2930 if (!mlx5_netdev_match(idev, dev->mdev, "mce")) 2931 continue; 2932 write_lock(&dev->roce.netdev_lock); 2933 dev->roce.netdev = idev; 2934 write_unlock(&dev->roce.netdev_lock); 2935 } 2936 CURVNET_RESTORE(); 2937 IFNET_RUNLOCK(); 2938 } 2939 VNET_LIST_RUNLOCK(); 2940 2941 dev->roce.nb.notifier_call = mlx5_netdev_event; 2942 err = register_netdevice_notifier(&dev->roce.nb); 2943 if (err) { 2944 dev->roce.nb.notifier_call = NULL; 2945 return err; 2946 } 2947 2948 err = mlx5_nic_vport_enable_roce(dev->mdev); 2949 if (err) 2950 goto err_unregister_netdevice_notifier; 2951 2952 err = mlx5_roce_lag_init(dev); 2953 if (err) 2954 goto err_disable_roce; 2955 2956 return 0; 2957 2958err_disable_roce: 2959 mlx5_nic_vport_disable_roce(dev->mdev); 2960 2961err_unregister_netdevice_notifier: 2962 mlx5_remove_roce_notifier(dev); 2963 return err; 2964} 2965 2966static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2967{ 2968 mlx5_roce_lag_cleanup(dev); 2969 mlx5_nic_vport_disable_roce(dev->mdev); 2970} 2971 2972static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num) 2973{ 2974 mlx5_vport_dealloc_q_counter(dev->mdev, 2975 MLX5_INTERFACE_PROTOCOL_IB, 2976 dev->port[port_num].q_cnt_id); 2977 dev->port[port_num].q_cnt_id = 0; 2978} 2979 2980static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 2981{ 2982 unsigned int i; 2983 2984 for (i = 0; i < dev->num_ports; i++) 2985 mlx5_ib_dealloc_q_port_counter(dev, i); 2986} 2987 2988static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 2989{ 2990 int i; 2991 int ret; 2992 2993 for (i = 0; i < dev->num_ports; i++) { 2994 ret = mlx5_vport_alloc_q_counter(dev->mdev, 2995 MLX5_INTERFACE_PROTOCOL_IB, 2996 &dev->port[i].q_cnt_id); 2997 if (ret) { 2998 mlx5_ib_warn(dev, 2999 "couldn't allocate queue counter for port %d, err %d\n", 3000 i + 1, ret); 3001 goto dealloc_counters; 3002 } 3003 } 3004 3005 return 0; 3006 3007dealloc_counters: 3008 while (--i >= 0) 3009 mlx5_ib_dealloc_q_port_counter(dev, i); 3010 3011 return ret; 3012} 3013 3014static const char * const names[] = { 3015 "rx_write_requests", 3016 "rx_read_requests", 3017 "rx_atomic_requests", 3018 "out_of_buffer", 3019 "out_of_sequence", 3020 "duplicate_request", 3021 "rnr_nak_retry_err", 3022 "packet_seq_err", 3023 "implied_nak_seq_err", 3024 "local_ack_timeout_err", 3025}; 3026 3027static const size_t stats_offsets[] = { 3028 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 3029 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 3030 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 3031 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 3032 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 3033 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 3034 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 3035 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 3036 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 3037 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 3038}; 3039 3040static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3041 u8 port_num) 3042{ 3043 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 3044 3045 /* We support only per port stats */ 3046 if (port_num == 0) 3047 return NULL; 3048 3049 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 3050 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3051} 3052 3053static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3054 struct rdma_hw_stats *stats, 3055 u8 port, int index) 3056{ 3057 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3058 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3059 void *out; 3060 __be32 val; 3061 int ret; 3062 int i; 3063 3064 if (!port || !stats) 3065 return -ENOSYS; 3066 3067 out = mlx5_vzalloc(outlen); 3068 if (!out) 3069 return -ENOMEM; 3070 3071 ret = mlx5_vport_query_q_counter(dev->mdev, 3072 dev->port[port - 1].q_cnt_id, 0, 3073 out, outlen); 3074 if (ret) 3075 goto free; 3076 3077 for (i = 0; i < ARRAY_SIZE(names); i++) { 3078 val = *(__be32 *)(out + stats_offsets[i]); 3079 stats->value[i] = (u64)be32_to_cpu(val); 3080 } 3081free: 3082 kvfree(out); 3083 return ARRAY_SIZE(names); 3084} 3085 3086static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3087{ 3088 struct mlx5_ib_dev *dev; 3089 enum rdma_link_layer ll; 3090 int port_type_cap; 3091 int err; 3092 int i; 3093 3094 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3095 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3096 3097 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 3098 return NULL; 3099 3100 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3101 if (!dev) 3102 return NULL; 3103 3104 dev->mdev = mdev; 3105 3106 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3107 GFP_KERNEL); 3108 if (!dev->port) 3109 goto err_dealloc; 3110 3111 rwlock_init(&dev->roce.netdev_lock); 3112 err = get_port_caps(dev); 3113 if (err) 3114 goto err_free_port; 3115 3116 if (mlx5_use_mad_ifc(dev)) 3117 get_ext_port_caps(dev); 3118 3119 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 3120 3121 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev)); 3122 dev->ib_dev.owner = THIS_MODULE; 3123 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3124 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3125 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3126 dev->ib_dev.phys_port_cnt = dev->num_ports; 3127 dev->ib_dev.num_comp_vectors = 3128 dev->mdev->priv.eq_table.num_comp_vectors; 3129 dev->ib_dev.dma_device = &mdev->pdev->dev; 3130 3131 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3132 dev->ib_dev.uverbs_cmd_mask = 3133 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3134 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3135 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3136 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3137 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3138 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3139 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3140 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3141 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3142 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3143 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3144 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3145 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3146 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3147 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3148 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3149 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3150 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3151 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3152 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3153 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3154 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3155 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3156 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3157 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3158 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3159 dev->ib_dev.uverbs_ex_cmd_mask = 3160 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3161 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3162 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 3163 3164 dev->ib_dev.query_device = mlx5_ib_query_device; 3165 dev->ib_dev.query_port = mlx5_ib_query_port; 3166 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3167 if (ll == IB_LINK_LAYER_ETHERNET) 3168 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3169 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3170 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3171 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3172 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3173 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3174 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3175 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3176 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3177 dev->ib_dev.mmap = mlx5_ib_mmap; 3178 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3179 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3180 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3181 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3182 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3183 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3184 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3185 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3186 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3187 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3188 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3189 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3190 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3191 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3192 dev->ib_dev.post_send = mlx5_ib_post_send; 3193 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3194 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3195 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3196 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3197 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3198 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3199 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3200 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3201 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3202 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3203 dev->ib_dev.reg_phys_mr = mlx5_ib_reg_phys_mr; 3204 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3205 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3206 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3207 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3208 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3209 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3210 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3211 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3212 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3213 if (mlx5_core_is_pf(mdev)) { 3214 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3215 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3216 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3217 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3218 } 3219 3220 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3221 3222 mlx5_ib_internal_fill_odp_caps(dev); 3223 3224 if (MLX5_CAP_GEN(mdev, imaicl)) { 3225 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3226 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3227 dev->ib_dev.uverbs_cmd_mask |= 3228 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3229 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3230 } 3231 3232 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 3233 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3234 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3235 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3236 } 3237 3238 if (MLX5_CAP_GEN(mdev, xrc)) { 3239 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3240 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3241 dev->ib_dev.uverbs_cmd_mask |= 3242 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3243 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3244 } 3245 3246 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3247 IB_LINK_LAYER_ETHERNET) { 3248 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3249 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3250 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3251 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3252 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3253 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3254 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3255 dev->ib_dev.uverbs_ex_cmd_mask |= 3256 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3257 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3258 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3259 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3260 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3261 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3262 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3263 } 3264 err = init_node_data(dev); 3265 if (err) 3266 goto err_free_port; 3267 3268 mutex_init(&dev->flow_db.lock); 3269 mutex_init(&dev->cap_mask_mutex); 3270 INIT_LIST_HEAD(&dev->qp_list); 3271 spin_lock_init(&dev->reset_flow_resource_lock); 3272 3273 if (ll == IB_LINK_LAYER_ETHERNET) { 3274 err = mlx5_enable_roce(dev); 3275 if (err) 3276 goto err_free_port; 3277 } 3278 3279 err = create_dev_resources(&dev->devr); 3280 if (err) 3281 goto err_disable_roce; 3282 3283 err = mlx5_ib_odp_init_one(dev); 3284 if (err) 3285 goto err_rsrc; 3286 3287 err = mlx5_ib_alloc_q_counters(dev); 3288 if (err) 3289 goto err_odp; 3290 3291 err = ib_register_device(&dev->ib_dev, NULL); 3292 if (err) 3293 goto err_q_cnt; 3294 3295 err = create_umr_res(dev); 3296 if (err) 3297 goto err_dev; 3298 3299 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3300 err = device_create_file(&dev->ib_dev.dev, 3301 mlx5_class_attributes[i]); 3302 if (err) 3303 goto err_umrc; 3304 } 3305 3306 err = mlx5_ib_init_congestion(dev); 3307 if (err) 3308 goto err_umrc; 3309 3310 dev->ib_active = true; 3311 3312 return dev; 3313 3314err_umrc: 3315 destroy_umrc_res(dev); 3316 3317err_dev: 3318 ib_unregister_device(&dev->ib_dev); 3319 3320err_q_cnt: 3321 mlx5_ib_dealloc_q_counters(dev); 3322 3323err_odp: 3324 mlx5_ib_odp_remove_one(dev); 3325 3326err_rsrc: 3327 destroy_dev_resources(&dev->devr); 3328 3329err_disable_roce: 3330 if (ll == IB_LINK_LAYER_ETHERNET) { 3331 mlx5_disable_roce(dev); 3332 mlx5_remove_roce_notifier(dev); 3333 } 3334 3335err_free_port: 3336 kfree(dev->port); 3337 3338err_dealloc: 3339 ib_dealloc_device((struct ib_device *)dev); 3340 3341 return NULL; 3342} 3343 3344static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3345{ 3346 struct mlx5_ib_dev *dev = context; 3347 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3348 3349 mlx5_ib_cleanup_congestion(dev); 3350 mlx5_remove_roce_notifier(dev); 3351 ib_unregister_device(&dev->ib_dev); 3352 mlx5_ib_dealloc_q_counters(dev); 3353 destroy_umrc_res(dev); 3354 mlx5_ib_odp_remove_one(dev); 3355 destroy_dev_resources(&dev->devr); 3356 if (ll == IB_LINK_LAYER_ETHERNET) 3357 mlx5_disable_roce(dev); 3358 kfree(dev->port); 3359 ib_dealloc_device(&dev->ib_dev); 3360} 3361 3362static struct mlx5_interface mlx5_ib_interface = { 3363 .add = mlx5_ib_add, 3364 .remove = mlx5_ib_remove, 3365 .event = mlx5_ib_event, 3366 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3367}; 3368 3369static int __init mlx5_ib_init(void) 3370{ 3371 int err; 3372 3373 err = mlx5_ib_odp_init(); 3374 if (err) 3375 return err; 3376 3377 err = mlx5_register_interface(&mlx5_ib_interface); 3378 if (err) 3379 goto clean_odp; 3380 3381 return err; 3382 3383clean_odp: 3384 mlx5_ib_odp_cleanup(); 3385 return err; 3386} 3387 3388static void __exit mlx5_ib_cleanup(void) 3389{ 3390 mlx5_unregister_interface(&mlx5_ib_interface); 3391 mlx5_ib_odp_cleanup(); 3392} 3393 3394static void 3395mlx5_ib_show_version(void __unused *arg) 3396{ 3397 3398 printf("%s", mlx5_version); 3399} 3400SYSINIT(mlx5_ib_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5_ib_show_version, NULL); 3401 3402module_init_order(mlx5_ib_init, SI_ORDER_SEVENTH); 3403module_exit_order(mlx5_ib_cleanup, SI_ORDER_SEVENTH); 3404