1171095Ssam/*- 2171095Ssam * Copyright (c) 2002-2007 Neterion, Inc. 3171095Ssam * All rights reserved. 4171095Ssam * 5171095Ssam * Redistribution and use in source and binary forms, with or without 6171095Ssam * modification, are permitted provided that the following conditions 7171095Ssam * are met: 8171095Ssam * 1. Redistributions of source code must retain the above copyright 9171095Ssam * notice, this list of conditions and the following disclaimer. 10171095Ssam * 2. Redistributions in binary form must reproduce the above copyright 11171095Ssam * notice, this list of conditions and the following disclaimer in the 12171095Ssam * documentation and/or other materials provided with the distribution. 13171095Ssam * 14171095Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15171095Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16171095Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17171095Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18171095Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19171095Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20171095Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21171095Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22171095Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23171095Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24171095Ssam * SUCH DAMAGE. 25171095Ssam * 26171095Ssam * $FreeBSD$ 27171095Ssam */ 28171095Ssam 29171095Ssam#ifndef XGE_HAL_REGS_H 30171095Ssam#define XGE_HAL_REGS_H 31171095Ssam 32173139Srwatson__EXTERN_BEGIN_DECLS 33173139Srwatson 34171095Ssamtypedef struct { 35171095Ssam 36171095Ssam/* General Control-Status Registers */ 37171095Ssam u64 general_int_status; 38171095Ssam#define XGE_HAL_GEN_INTR_TXPIC BIT(0) 39171095Ssam#define XGE_HAL_GEN_INTR_TXDMA BIT(1) 40171095Ssam#define XGE_HAL_GEN_INTR_TXMAC BIT(2) 41171095Ssam#define XGE_HAL_GEN_INTR_TXXGXS BIT(3) 42171095Ssam#define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8) 43171095Ssam#define XGE_HAL_GEN_INTR_RXPIC BIT(32) 44171095Ssam#define XGE_HAL_GEN_INTR_RXDMA BIT(33) 45171095Ssam#define XGE_HAL_GEN_INTR_RXMAC BIT(34) 46171095Ssam#define XGE_HAL_GEN_INTR_MC BIT(35) 47171095Ssam#define XGE_HAL_GEN_INTR_RXXGXS BIT(36) 48171095Ssam#define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40) 49171095Ssam#define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \ 50173139Srwatson XGE_HAL_GEN_INTR_RXPIC | \ 51173139Srwatson XGE_HAL_GEN_INTR_TXDMA | \ 52173139Srwatson XGE_HAL_GEN_INTR_RXDMA | \ 53173139Srwatson XGE_HAL_GEN_INTR_TXMAC | \ 54173139Srwatson XGE_HAL_GEN_INTR_RXMAC | \ 55173139Srwatson XGE_HAL_GEN_INTR_TXXGXS | \ 56173139Srwatson XGE_HAL_GEN_INTR_RXXGXS | \ 57173139Srwatson XGE_HAL_GEN_INTR_MC) 58171095Ssam 59171095Ssam u64 general_int_mask; 60171095Ssam 61171095Ssam u8 unused0[0x100 - 0x10]; 62171095Ssam 63171095Ssam u64 sw_reset; 64171095Ssam 65171095Ssam/* XGXS must be removed from reset only once. */ 66171095Ssam#define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8) 67171095Ssam#define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8) 68171095Ssam#define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8) 69171095Ssam#define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8) 70171095Ssam#define XGE_HAL_SW_RESET_ALL (XGE_HAL_SW_RESET_XENA | \ 71173139Srwatson XGE_HAL_SW_RESET_FLASH | \ 72173139Srwatson XGE_HAL_SW_RESET_EOI | \ 73173139Srwatson XGE_HAL_SW_RESET_XGXS) 74171095Ssam 75171095Ssam/* The SW_RESET register must read this value after a successful reset. */ 76171095Ssam#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN) 77173139Srwatson#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL 78173139Srwatson#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL 79171095Ssam#else 80173139Srwatson#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL 81173139Srwatson#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL 82171095Ssam#endif 83171095Ssam 84171095Ssam 85171095Ssam u64 adapter_status; 86171095Ssam#define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0) 87171095Ssam#define XGE_HAL_ADAPTER_STATUS_RDMA_READY BIT(1) 88171095Ssam#define XGE_HAL_ADAPTER_STATUS_PFC_READY BIT(2) 89171095Ssam#define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3) 90171095Ssam#define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT BIT(5) 91171095Ssam#define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6) 92171095Ssam#define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7) 93171095Ssam#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) 94171095Ssam#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8) 95171095Ssam#define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 96171095Ssam 97171095Ssam#define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) 98171095Ssam#define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY BIT(24) 99171095Ssam#define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY BIT(25) 100171095Ssam#define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK BIT(30) 101171095Ssam#define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK BIT(31) 102171095Ssam 103171095Ssam u64 adapter_control; 104171095Ssam#define XGE_HAL_ADAPTER_CNTL_EN BIT(7) 105171095Ssam#define XGE_HAL_ADAPTER_EOI_TX_ON BIT(15) 106171095Ssam#define XGE_HAL_ADAPTER_LED_ON BIT(23) 107171095Ssam#define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4) 108171095Ssam#define XGE_HAL_ADAPTER_WAIT_INT BIT(48) 109171095Ssam#define XGE_HAL_ADAPTER_ECC_EN BIT(55) 110171095Ssam 111171095Ssam u64 serr_source; 112173139Srwatson#define XGE_HAL_SERR_SOURCE_PIC BIT(0) 113171095Ssam#define XGE_HAL_SERR_SOURCE_TXDMA BIT(1) 114171095Ssam#define XGE_HAL_SERR_SOURCE_RXDMA BIT(2) 115173139Srwatson#define XGE_HAL_SERR_SOURCE_MAC BIT(3) 116173139Srwatson#define XGE_HAL_SERR_SOURCE_MC BIT(4) 117173139Srwatson#define XGE_HAL_SERR_SOURCE_XGXS BIT(5) 118173139Srwatson#define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \ 119173139Srwatson XGE_HAL_SERR_SOURCE_TXDMA | \ 120173139Srwatson XGE_HAL_SERR_SOURCE_RXDMA | \ 121173139Srwatson XGE_HAL_SERR_SOURCE_MAC | \ 122173139Srwatson XGE_HAL_SERR_SOURCE_MC | \ 123173139Srwatson XGE_HAL_SERR_SOURCE_XGXS) 124171095Ssam 125173139Srwatson u64 pci_info; 126173139Srwatson#define XGE_HAL_PCI_INFO vBIT(0xF,0,4) 127173139Srwatson#define XGE_HAL_PCI_32_BIT BIT(8) 128171095Ssam 129171095Ssam u8 unused0_1[0x160 - 0x128]; 130171095Ssam 131171095Ssam u64 ric_status; 132171095Ssam 133171095Ssam u8 unused0_2[0x558 - 0x168]; 134171095Ssam 135171095Ssam u64 mbist_status; 136171095Ssam 137171095Ssam u8 unused0_3[0x800 - 0x560]; 138171095Ssam 139171095Ssam/* PCI-X Controller registers */ 140171095Ssam u64 pic_int_status; 141171095Ssam u64 pic_int_mask; 142171095Ssam#define XGE_HAL_PIC_INT_TX BIT(0) 143171095Ssam#define XGE_HAL_PIC_INT_FLSH BIT(1) 144171095Ssam#define XGE_HAL_PIC_INT_MDIO BIT(2) 145171095Ssam#define XGE_HAL_PIC_INT_IIC BIT(3) 146171095Ssam#define XGE_HAL_PIC_INT_MISC BIT(4) 147171095Ssam#define XGE_HAL_PIC_INT_RX BIT(32) 148171095Ssam 149171095Ssam u64 txpic_int_reg; 150171095Ssam#define XGE_HAL_TXPIC_INT_SCHED_INTR BIT(42) 151171095Ssam u64 txpic_int_mask; 152171095Ssam#define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0) 153171095Ssam#define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR BIT(1) 154171095Ssam#define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8) 155171095Ssam#define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9) 156171095Ssam#define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR BIT(10) 157171095Ssam#define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11) 158171095Ssam#define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR BIT(13) 159171095Ssam#define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR BIT(14) 160171095Ssam#define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR BIT(15) 161171095Ssam#define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21) 162171095Ssam#define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23) 163171095Ssam#define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR BIT(48) 164171095Ssam#define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR BIT(50) 165171095Ssam/* 166171095Ssam#define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52) 167171095Ssam#define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54) 168171095Ssam#define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58) 169171095Ssam*/ 170171095Ssam u64 txpic_alarms; 171171095Ssam u64 rxpic_int_reg; 172171095Ssam#define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0) 173171095Ssam#define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR BIT(44) 174171095Ssam#define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR BIT(55) 175171095Ssam u64 rxpic_int_mask; 176171095Ssam u64 rxpic_alarms; 177171095Ssam 178171095Ssam u64 flsh_int_reg; 179171095Ssam u64 flsh_int_mask; 180171095Ssam#define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63) 181171095Ssam#define XGE_HAL_PIC_FLSH_INT_REG_ERR BIT(62) 182171095Ssam u64 flash_alarms; 183171095Ssam 184171095Ssam u64 mdio_int_reg; 185171095Ssam u64 mdio_int_mask; 186171095Ssam#define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0) 187171095Ssam#define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR BIT(8) 188171095Ssam#define XGE_HAL_MDIO_INT_REG_LASI BIT(39) 189171095Ssam u64 mdio_alarms; 190171095Ssam 191171095Ssam u64 iic_int_reg; 192171095Ssam u64 iic_int_mask; 193171095Ssam#define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR BIT(4) 194171095Ssam#define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR BIT(5) 195171095Ssam#define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR BIT(6) 196171095Ssam#define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR BIT(7) 197171095Ssam#define XGE_HAL_IIC_INT_REG_ACK_ERR BIT(8) 198171095Ssam u64 iic_alarms; 199171095Ssam 200171095Ssam u64 msi_pending_reg; 201171095Ssam 202171095Ssam u64 misc_int_reg; 203173139Srwatson#define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0) 204173139Srwatson#define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1) 205173139Srwatson#define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2) 206171095Ssam u64 misc_int_mask; 207171095Ssam u64 misc_alarms; 208171095Ssam 209171095Ssam u64 msi_triggered_reg; 210171095Ssam 211171095Ssam u64 xfp_gpio_int_reg; 212171095Ssam u64 xfp_gpio_int_mask; 213171095Ssam u64 xfp_alarms; 214171095Ssam 215171095Ssam u8 unused5[0x8E0 - 0x8C8]; 216171095Ssam 217171095Ssam u64 tx_traffic_int; 218171095Ssam#define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n) 219171095Ssam u64 tx_traffic_mask; 220171095Ssam 221171095Ssam u64 rx_traffic_int; 222171095Ssam#define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n) 223171095Ssam u64 rx_traffic_mask; 224171095Ssam 225171095Ssam/* PIC Control registers */ 226171095Ssam u64 pic_control; 227171095Ssam#define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0) 228171095Ssam#define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT BIT(1) 229171095Ssam#define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4) 230171095Ssam 231171095Ssam u64 swapper_ctrl; 232171095Ssam#define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0) 233171095Ssam#define XGE_HAL_SWAPPER_CTRL_PIF_R_SE BIT(1) 234171095Ssam#define XGE_HAL_SWAPPER_CTRL_PIF_W_FE BIT(8) 235171095Ssam#define XGE_HAL_SWAPPER_CTRL_PIF_W_SE BIT(9) 236171095Ssam#define XGE_HAL_SWAPPER_CTRL_RTH_FE BIT(10) 237171095Ssam#define XGE_HAL_SWAPPER_CTRL_RTH_SE BIT(11) 238171095Ssam#define XGE_HAL_SWAPPER_CTRL_TXP_FE BIT(16) 239171095Ssam#define XGE_HAL_SWAPPER_CTRL_TXP_SE BIT(17) 240171095Ssam#define XGE_HAL_SWAPPER_CTRL_TXD_R_FE BIT(18) 241171095Ssam#define XGE_HAL_SWAPPER_CTRL_TXD_R_SE BIT(19) 242171095Ssam#define XGE_HAL_SWAPPER_CTRL_TXD_W_FE BIT(20) 243171095Ssam#define XGE_HAL_SWAPPER_CTRL_TXD_W_SE BIT(21) 244171095Ssam#define XGE_HAL_SWAPPER_CTRL_TXF_R_FE BIT(22) 245171095Ssam#define XGE_HAL_SWAPPER_CTRL_TXF_R_SE BIT(23) 246171095Ssam#define XGE_HAL_SWAPPER_CTRL_RXD_R_FE BIT(32) 247171095Ssam#define XGE_HAL_SWAPPER_CTRL_RXD_R_SE BIT(33) 248171095Ssam#define XGE_HAL_SWAPPER_CTRL_RXD_W_FE BIT(34) 249171095Ssam#define XGE_HAL_SWAPPER_CTRL_RXD_W_SE BIT(35) 250171095Ssam#define XGE_HAL_SWAPPER_CTRL_RXF_W_FE BIT(36) 251171095Ssam#define XGE_HAL_SWAPPER_CTRL_RXF_W_SE BIT(37) 252171095Ssam#define XGE_HAL_SWAPPER_CTRL_XMSI_FE BIT(40) 253171095Ssam#define XGE_HAL_SWAPPER_CTRL_XMSI_SE BIT(41) 254171095Ssam#define XGE_HAL_SWAPPER_CTRL_STATS_FE BIT(48) 255171095Ssam#define XGE_HAL_SWAPPER_CTRL_STATS_SE BIT(49) 256171095Ssam 257171095Ssam u64 pif_rd_swapper_fb; 258171095Ssam#define XGE_HAL_IF_RD_SWAPPER_FB 0x0123456789ABCDEFULL 259171095Ssam 260171095Ssam u64 scheduled_int_ctrl; 261171095Ssam#define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0) 262171095Ssam#define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1) 263173139Srwatson#define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) 264173139Srwatson#define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32) 265173139Srwatson#define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL 266171095Ssam 267171095Ssam 268171095Ssam u64 txreqtimeout; 269173139Srwatson#define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32) 270173139Srwatson#define XGE_HAL_TXREQTO_EN BIT(63) 271171095Ssam 272171095Ssam u64 statsreqtimeout; 273171095Ssam#define XGE_HAL_STATREQTO_VAL(n) TBD 274171095Ssam#define XGE_HAL_STATREQTO_EN BIT(63) 275171095Ssam 276171095Ssam u64 read_retry_delay; 277171095Ssam u64 read_retry_acceleration; 278171095Ssam u64 write_retry_delay; 279171095Ssam u64 write_retry_acceleration; 280171095Ssam 281171095Ssam u64 xmsi_control; 282173139Srwatson#define XGE_HAL_XMSI_EN BIT(0) 283173139Srwatson#define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1) 284173139Srwatson#define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3) 285171095Ssam 286171095Ssam u64 xmsi_access; 287173139Srwatson#define XGE_HAL_XMSI_WR_RDN BIT(7) 288173139Srwatson#define XGE_HAL_XMSI_STROBE BIT(15) 289173139Srwatson#define XGE_HAL_XMSI_NO(val) vBIT(val,26,6) 290171095Ssam 291171095Ssam u64 xmsi_address; 292171095Ssam u64 xmsi_data; 293171095Ssam 294171095Ssam u64 rx_mat; 295173139Srwatson#define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8) 296171095Ssam 297171095Ssam u8 unused6[0x8]; 298171095Ssam 299171095Ssam u64 tx_mat[8]; 300173139Srwatson#define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8) 301171095Ssam 302171095Ssam u64 xmsi_mask_reg; 303171095Ssam 304171095Ssam /* Automated statistics collection */ 305171095Ssam u64 stat_byte_cnt; 306171095Ssam u64 stat_cfg; 307171095Ssam#define XGE_HAL_STAT_CFG_STAT_EN BIT(0) 308171095Ssam#define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1) 309171095Ssam#define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8) 310171095Ssam#define XGE_HAL_STAT_CFG_STAT_RO BIT(9) 311173139Srwatson#define XGE_HAL_XENA_PER_SEC 0x208d5 312173139Srwatson#define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32) 313171095Ssam 314171095Ssam u64 stat_addr; 315171095Ssam 316171095Ssam /* General Configuration */ 317171095Ssam u64 mdio_control; 318173139Srwatson#define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16) 319173139Srwatson#define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5) 320173139Srwatson#define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5) 321173139Srwatson#define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16) 322173139Srwatson#define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4) 323173139Srwatson#define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2) 324173139Srwatson#define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n) ((n>>16)&0xFFFF) 325173139Srwatson#define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR 0x01 326173139Srwatson#define XGE_HAL_MDIO_DOM_REG_ADDR 0xA100 327173139Srwatson#define XGE_HAL_MDIO_ALARM_FLAGS_ADDR 0xA070 328173139Srwatson#define XGE_HAL_MDIO_WARN_FLAGS_ADDR 0xA074 329173139Srwatson#define XGE_HAL_MDIO_CTRL_START 0xE 330173139Srwatson#define XGE_HAL_MDIO_OP_ADDRESS 0x0 331173139Srwatson#define XGE_HAL_MDIO_OP_WRITE 0x1 332173139Srwatson#define XGE_HAL_MDIO_OP_READ 0x3 333173139Srwatson#define XGE_HAL_MDIO_OP_READ_POST_INCREMENT 0x2 334173139Srwatson#define XGE_HAL_MDIO_ALARM_TEMPHIGH 0x0080 335173139Srwatson#define XGE_HAL_MDIO_ALARM_TEMPLOW 0x0040 336173139Srwatson#define XGE_HAL_MDIO_ALARM_BIASHIGH 0x0008 337173139Srwatson#define XGE_HAL_MDIO_ALARM_BIASLOW 0x0004 338173139Srwatson#define XGE_HAL_MDIO_ALARM_POUTPUTHIGH 0x0002 339173139Srwatson#define XGE_HAL_MDIO_ALARM_POUTPUTLOW 0x0001 340173139Srwatson#define XGE_HAL_MDIO_WARN_TEMPHIGH 0x0080 341173139Srwatson#define XGE_HAL_MDIO_WARN_TEMPLOW 0x0040 342173139Srwatson#define XGE_HAL_MDIO_WARN_BIASHIGH 0x0008 343173139Srwatson#define XGE_HAL_MDIO_WARN_BIASLOW 0x0004 344173139Srwatson#define XGE_HAL_MDIO_WARN_POUTPUTHIGH 0x0002 345173139Srwatson#define XGE_HAL_MDIO_WARN_POUTPUTLOW 0x0001 346171095Ssam 347171095Ssam u64 dtx_control; 348171095Ssam 349171095Ssam u64 i2c_control; 350173139Srwatson#define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) 351173139Srwatson#define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) 352173139Srwatson#define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) 353173139Srwatson#define XGE_HAL_I2C_CONTROL_READ BIT(24) 354173139Srwatson#define XGE_HAL_I2C_CONTROL_NACK BIT(25) 355173139Srwatson#define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4) 356173139Srwatson#define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) 357173139Srwatson#define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) 358173139Srwatson#define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) 359171095Ssam 360171095Ssam u64 beacon_control; 361171095Ssam u64 misc_control; 362173139Srwatson#define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3) 363171095Ssam#define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1) 364173139Srwatson#define XGE_HAL_MISC_CONTROL_LINK_FAULT BIT(0) 365171095Ssam 366171095Ssam u64 xfb_control; 367171095Ssam u64 gpio_control; 368173139Srwatson#define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8) 369171095Ssam 370171095Ssam u64 txfifo_dw_mask; 371171095Ssam u64 split_table_line_no; 372171095Ssam u64 sc_timeout; 373171095Ssam u64 pic_control_2; 374171095Ssam#define XGE_HAL_TXD_WRITE_BC(n) vBIT(n, 13, 3) 375171095Ssam u64 ini_dperr_ctrl; 376171095Ssam u64 wreq_split_mask; 377171095Ssam u64 qw_per_rxd; 378171095Ssam u8 unused7[0x300 - 0x250]; 379171095Ssam 380171095Ssam u64 pic_status; 381171095Ssam u64 txp_status; 382171095Ssam u64 txp_err_context; 383171095Ssam u64 spdm_bir_offset; 384173139Srwatson#define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \ 385173139Srwatson (u8)(spdm_bir_offset >> 61) 386171095Ssam#define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \ 387173139Srwatson (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF) 388171095Ssam u64 spdm_overwrite; 389171095Ssam#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \ 390173139Srwatson (u8)((spdm_overwrite >> 48) & 0xff) 391171095Ssam#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \ 392173139Srwatson (u8)((spdm_overwrite >> 40) & 0x3) 393171095Ssam#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \ 394173139Srwatson (u8)((spdm_overwrite >> 32) & 0x7) 395171095Ssam u64 cfg_addr_on_dperr; 396171095Ssam u64 pif_addr_on_dperr; 397171095Ssam u64 tags_in_use; 398171095Ssam u64 rd_req_types; 399171095Ssam u64 split_table_line; 400171095Ssam u64 unxp_split_add_ph; 401171095Ssam u64 unexp_split_attr_ph; 402171095Ssam u64 split_message; 403171095Ssam u64 spdm_structure; 404171095Ssam#define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure) (u16)(spdm_structure >> 48) 405171095Ssam#define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \ 406173139Srwatson (u8)((spdm_structure >> 40) & 0xff) 407171095Ssam#define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \ 408173139Srwatson (u8)((spdm_structure >> 32) & 0xff) 409171095Ssam 410171095Ssam u64 txdw_ptr_cnt_0; 411171095Ssam u64 txdw_ptr_cnt_1; 412171095Ssam u64 txdw_ptr_cnt_2; 413171095Ssam u64 txdw_ptr_cnt_3; 414171095Ssam u64 txdw_ptr_cnt_4; 415171095Ssam u64 txdw_ptr_cnt_5; 416171095Ssam u64 txdw_ptr_cnt_6; 417171095Ssam u64 txdw_ptr_cnt_7; 418171095Ssam u64 rxdw_cnt_ring_0; 419171095Ssam u64 rxdw_cnt_ring_1; 420171095Ssam u64 rxdw_cnt_ring_2; 421171095Ssam u64 rxdw_cnt_ring_3; 422171095Ssam u64 rxdw_cnt_ring_4; 423171095Ssam u64 rxdw_cnt_ring_5; 424171095Ssam u64 rxdw_cnt_ring_6; 425171095Ssam u64 rxdw_cnt_ring_7; 426171095Ssam 427171095Ssam u8 unused8[0x410]; 428171095Ssam 429171095Ssam/* TxDMA registers */ 430171095Ssam u64 txdma_int_status; 431171095Ssam u64 txdma_int_mask; 432173139Srwatson#define XGE_HAL_TXDMA_PFC_INT BIT(0) 433173139Srwatson#define XGE_HAL_TXDMA_TDA_INT BIT(1) 434173139Srwatson#define XGE_HAL_TXDMA_PCC_INT BIT(2) 435173139Srwatson#define XGE_HAL_TXDMA_TTI_INT BIT(3) 436173139Srwatson#define XGE_HAL_TXDMA_LSO_INT BIT(4) 437173139Srwatson#define XGE_HAL_TXDMA_TPA_INT BIT(5) 438173139Srwatson#define XGE_HAL_TXDMA_SM_INT BIT(6) 439171095Ssam u64 pfc_err_reg; 440173139Srwatson#define XGE_HAL_PFC_ECC_SG_ERR BIT(7) 441173139Srwatson#define XGE_HAL_PFC_ECC_DB_ERR BIT(15) 442173139Srwatson#define XGE_HAL_PFC_SM_ERR_ALARM BIT(23) 443173139Srwatson#define XGE_HAL_PFC_MISC_0_ERR BIT(31) 444173139Srwatson#define XGE_HAL_PFC_MISC_1_ERR BIT(32) 445173139Srwatson#define XGE_HAL_PFC_PCIX_ERR BIT(39) 446171095Ssam u64 pfc_err_mask; 447171095Ssam u64 pfc_err_alarm; 448171095Ssam 449171095Ssam u64 tda_err_reg; 450173139Srwatson#define XGE_HAL_TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) 451173139Srwatson#define XGE_HAL_TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) 452173139Srwatson#define XGE_HAL_TDA_SM0_ERR_ALARM BIT(22) 453173139Srwatson#define XGE_HAL_TDA_SM1_ERR_ALARM BIT(23) 454173139Srwatson#define XGE_HAL_TDA_PCIX_ERR BIT(39) 455171095Ssam u64 tda_err_mask; 456171095Ssam u64 tda_err_alarm; 457171095Ssam 458171095Ssam u64 pcc_err_reg; 459173139Srwatson#define XGE_HAL_PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8) 460173139Srwatson#define XGE_HAL_PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8) 461173139Srwatson#define XGE_HAL_PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8) 462173139Srwatson#define XGE_HAL_PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8) 463173139Srwatson#define XGE_HAL_PCC_SM_ERR_ALARM vBIT(0xff,32,8) 464173139Srwatson#define XGE_HAL_PCC_WR_ERR_ALARM vBIT(0xff,40,8) 465173139Srwatson#define XGE_HAL_PCC_N_SERR vBIT(0xff,48,8) 466173139Srwatson#define XGE_HAL_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 467173139Srwatson#define XGE_HAL_PCC_6_COF_OV_ERR BIT(56) 468173139Srwatson#define XGE_HAL_PCC_7_COF_OV_ERR BIT(57) 469173139Srwatson#define XGE_HAL_PCC_6_LSO_OV_ERR BIT(58) 470173139Srwatson#define XGE_HAL_PCC_7_LSO_OV_ERR BIT(59) 471171095Ssam u64 pcc_err_mask; 472171095Ssam u64 pcc_err_alarm; 473171095Ssam 474171095Ssam u64 tti_err_reg; 475173139Srwatson#define XGE_HAL_TTI_ECC_SG_ERR BIT(7) 476173139Srwatson#define XGE_HAL_TTI_ECC_DB_ERR BIT(15) 477173139Srwatson#define XGE_HAL_TTI_SM_ERR_ALARM BIT(23) 478171095Ssam u64 tti_err_mask; 479171095Ssam u64 tti_err_alarm; 480171095Ssam 481171095Ssam u64 lso_err_reg; 482173139Srwatson#define XGE_HAL_LSO6_SEND_OFLOW BIT(12) 483173139Srwatson#define XGE_HAL_LSO7_SEND_OFLOW BIT(13) 484173139Srwatson#define XGE_HAL_LSO6_ABORT BIT(14) 485173139Srwatson#define XGE_HAL_LSO7_ABORT BIT(15) 486173139Srwatson#define XGE_HAL_LSO6_SM_ERR_ALARM BIT(22) 487173139Srwatson#define XGE_HAL_LSO7_SM_ERR_ALARM BIT(23) 488171095Ssam u64 lso_err_mask; 489171095Ssam u64 lso_err_alarm; 490171095Ssam 491171095Ssam u64 tpa_err_reg; 492173139Srwatson#define XGE_HAL_TPA_TX_FRM_DROP BIT(7) 493173139Srwatson#define XGE_HAL_TPA_SM_ERR_ALARM BIT(23) 494171095Ssam u64 tpa_err_mask; 495171095Ssam u64 tpa_err_alarm; 496171095Ssam 497171095Ssam u64 sm_err_reg; 498173139Srwatson#define XGE_HAL_SM_SM_ERR_ALARM BIT(15) 499171095Ssam u64 sm_err_mask; 500171095Ssam u64 sm_err_alarm; 501171095Ssam 502171095Ssam u8 unused9[0x100 - 0xB8]; 503171095Ssam 504171095Ssam/* TxDMA arbiter */ 505171095Ssam u64 tx_dma_wrap_stat; 506171095Ssam 507171095Ssam/* Tx FIFO controller */ 508171095Ssam#define XGE_HAL_X_MAX_FIFOS 8 509173139Srwatson#define XGE_HAL_X_FIFO_MAX_LEN 0x1FFF /*8191 */ 510171095Ssam u64 tx_fifo_partition_0; 511171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0) 512171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) 513171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) 514171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) 515171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) 516171095Ssam 517171095Ssam u64 tx_fifo_partition_1; 518171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) 519171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) 520171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) 521171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) 522171095Ssam 523171095Ssam u64 tx_fifo_partition_2; 524171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) 525171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) 526171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) 527171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) 528171095Ssam 529171095Ssam u64 tx_fifo_partition_3; 530171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) 531171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) 532171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) 533171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) 534171095Ssam 535173139Srwatson#define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */ 536171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_PRI_1 1 537171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_PRI_2 2 538171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_PRI_3 3 539171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_PRI_4 4 540171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_PRI_5 5 541171095Ssam#define XGE_HAL_TX_FIFO_PARTITION_PRI_6 6 542173139Srwatson#define XGE_HAL_TX_FIFO_PARTITION_PRI_7 7 /* lowest */ 543171095Ssam 544171095Ssam u64 tx_w_round_robin_0; 545171095Ssam u64 tx_w_round_robin_1; 546171095Ssam u64 tx_w_round_robin_2; 547171095Ssam u64 tx_w_round_robin_3; 548171095Ssam u64 tx_w_round_robin_4; 549171095Ssam 550171095Ssam u64 tti_command_mem; 551171095Ssam#define XGE_HAL_TTI_CMD_MEM_WE BIT(7) 552171095Ssam#define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 553171095Ssam#define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15) 554171095Ssam#define XGE_HAL_TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) 555171095Ssam 556171095Ssam u64 tti_data1_mem; 557171095Ssam#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) 558171095Ssam#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) 559171095Ssam#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38) 560171095Ssam#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39) 561171095Ssam#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) 562171095Ssam#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) 563171095Ssam#define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) 564171095Ssam 565171095Ssam u64 tti_data2_mem; 566171095Ssam#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) 567171095Ssam#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) 568171095Ssam#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) 569171095Ssam#define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) 570171095Ssam 571171095Ssam/* Tx Protocol assist */ 572171095Ssam u64 tx_pa_cfg; 573171095Ssam#define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1) 574171095Ssam#define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 575171095Ssam#define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 576173139Srwatson#define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6) 577171095Ssam 578171095Ssam/* Recent add, used only debug purposes. */ 579171095Ssam u64 pcc_enable; 580171095Ssam 581171095Ssam u64 pfc_monitor_0; 582171095Ssam u64 pfc_monitor_1; 583171095Ssam u64 pfc_monitor_2; 584171095Ssam u64 pfc_monitor_3; 585171095Ssam u64 txd_ownership_ctrl; 586171095Ssam u64 pfc_read_cntrl; 587171095Ssam u64 pfc_read_data; 588171095Ssam 589171095Ssam u8 unused10[0x1700 - 0x11B0]; 590171095Ssam 591171095Ssam u64 txdma_debug_ctrl; 592171095Ssam 593171095Ssam u8 unused11[0x1800 - 0x1708]; 594171095Ssam 595171095Ssam/* RxDMA Registers */ 596171095Ssam u64 rxdma_int_status; 597171095Ssam#define XGE_HAL_RXDMA_RC_INT BIT(0) 598171095Ssam#define XGE_HAL_RXDMA_RPA_INT BIT(1) 599171095Ssam#define XGE_HAL_RXDMA_RDA_INT BIT(2) 600171095Ssam#define XGE_HAL_RXDMA_RTI_INT BIT(3) 601171095Ssam 602171095Ssam u64 rxdma_int_mask; 603171095Ssam#define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0) 604171095Ssam#define XGE_HAL_RXDMA_INT_RPA_INT_M BIT(1) 605171095Ssam#define XGE_HAL_RXDMA_INT_RDA_INT_M BIT(2) 606171095Ssam#define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3) 607171095Ssam 608171095Ssam u64 rda_err_reg; 609173139Srwatson#define XGE_HAL_RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) 610173139Srwatson#define XGE_HAL_RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) 611173139Srwatson#define XGE_HAL_RDA_FRM_ECC_SG_ERR BIT(23) 612173139Srwatson#define XGE_HAL_RDA_FRM_ECC_DB_N_AERR BIT(31) 613173139Srwatson#define XGE_HAL_RDA_SM1_ERR_ALARM BIT(38) 614173139Srwatson#define XGE_HAL_RDA_SM0_ERR_ALARM BIT(39) 615173139Srwatson#define XGE_HAL_RDA_MISC_ERR BIT(47) 616173139Srwatson#define XGE_HAL_RDA_PCIX_ERR BIT(55) 617173139Srwatson#define XGE_HAL_RDA_RXD_ECC_DB_SERR BIT(63) 618171095Ssam u64 rda_err_mask; 619171095Ssam u64 rda_err_alarm; 620171095Ssam 621171095Ssam u64 rc_err_reg; 622173139Srwatson#define XGE_HAL_RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) 623173139Srwatson#define XGE_HAL_RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) 624173139Srwatson#define XGE_HAL_RC_FTC_ECC_SG_ERR BIT(23) 625173139Srwatson#define XGE_HAL_RC_FTC_ECC_DB_ERR BIT(31) 626173139Srwatson#define XGE_HAL_RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) 627173139Srwatson#define XGE_HAL_RC_FTC_SM_ERR_ALARM BIT(47) 628173139Srwatson#define XGE_HAL_RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) 629171095Ssam u64 rc_err_mask; 630171095Ssam u64 rc_err_alarm; 631171095Ssam 632171095Ssam u64 prc_pcix_err_reg; 633173139Srwatson#define XGE_HAL_PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8) 634173139Srwatson#define XGE_HAL_PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8) 635173139Srwatson#define XGE_HAL_PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8) 636173139Srwatson#define XGE_HAL_PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8) 637173139Srwatson#define XGE_HAL_PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8) 638173139Srwatson#define XGE_HAL_PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8) 639171095Ssam u64 prc_pcix_err_mask; 640171095Ssam u64 prc_pcix_err_alarm; 641171095Ssam 642171095Ssam u64 rpa_err_reg; 643173139Srwatson#define XGE_HAL_RPA_ECC_SG_ERR BIT(7) 644173139Srwatson#define XGE_HAL_RPA_ECC_DB_ERR BIT(15) 645173139Srwatson#define XGE_HAL_RPA_FLUSH_REQUEST BIT(22) 646173139Srwatson#define XGE_HAL_RPA_SM_ERR_ALARM BIT(23) 647173139Srwatson#define XGE_HAL_RPA_CREDIT_ERR BIT(31) 648171095Ssam u64 rpa_err_mask; 649171095Ssam u64 rpa_err_alarm; 650171095Ssam 651171095Ssam u64 rti_err_reg; 652173139Srwatson#define XGE_HAL_RTI_ECC_SG_ERR BIT(7) 653173139Srwatson#define XGE_HAL_RTI_ECC_DB_ERR BIT(15) 654173139Srwatson#define XGE_HAL_RTI_SM_ERR_ALARM BIT(23) 655171095Ssam u64 rti_err_mask; 656171095Ssam u64 rti_err_alarm; 657171095Ssam 658171095Ssam u8 unused12[0x100 - 0x88]; 659171095Ssam 660171095Ssam/* DMA arbiter */ 661171095Ssam u64 rx_queue_priority; 662171095Ssam#define XGE_HAL_RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) 663171095Ssam#define XGE_HAL_RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) 664171095Ssam#define XGE_HAL_RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) 665171095Ssam#define XGE_HAL_RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) 666171095Ssam#define XGE_HAL_RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) 667171095Ssam#define XGE_HAL_RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) 668171095Ssam#define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) 669171095Ssam#define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) 670171095Ssam 671173139Srwatson#define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */ 672171095Ssam#define XGE_HAL_RX_QUEUE_PRI_1 1 673171095Ssam#define XGE_HAL_RX_QUEUE_PRI_2 2 674171095Ssam#define XGE_HAL_RX_QUEUE_PRI_3 3 675171095Ssam#define XGE_HAL_RX_QUEUE_PRI_4 4 676171095Ssam#define XGE_HAL_RX_QUEUE_PRI_5 5 677171095Ssam#define XGE_HAL_RX_QUEUE_PRI_6 6 678173139Srwatson#define XGE_HAL_RX_QUEUE_PRI_7 7 /* lowest */ 679171095Ssam 680171095Ssam u64 rx_w_round_robin_0; 681171095Ssam u64 rx_w_round_robin_1; 682171095Ssam u64 rx_w_round_robin_2; 683171095Ssam u64 rx_w_round_robin_3; 684171095Ssam u64 rx_w_round_robin_4; 685171095Ssam 686171095Ssam /* Per-ring controller regs */ 687171095Ssam#define XGE_HAL_RX_MAX_RINGS 8 688171095Ssam u64 prc_rxd0_n[XGE_HAL_RX_MAX_RINGS]; 689171095Ssam u64 prc_ctrl_n[XGE_HAL_RX_MAX_RINGS]; 690171095Ssam#define XGE_HAL_PRC_CTRL_RC_ENABLED BIT(7) 691171095Ssam#define XGE_HAL_PRC_CTRL_RING_MODE (BIT(14)|BIT(15)) 692171095Ssam#define XGE_HAL_PRC_CTRL_RING_MODE_1 vBIT(0,14,2) 693171095Ssam#define XGE_HAL_PRC_CTRL_RING_MODE_3 vBIT(1,14,2) 694171095Ssam#define XGE_HAL_PRC_CTRL_RING_MODE_5 vBIT(2,14,2) 695171095Ssam#define XGE_HAL_PRC_CTRL_RING_MODE_x vBIT(3,14,2) 696171095Ssam#define XGE_HAL_PRC_CTRL_NO_SNOOP(n) vBIT(n,22,2) 697171095Ssam#define XGE_HAL_PRC_CTRL_RTH_DISABLE BIT(31) 698171095Ssam#define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT BIT(37) 699171095Ssam#define XGE_HAL_PRC_CTRL_GROUP_READS BIT(38) 700171095Ssam#define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) 701171095Ssam 702171095Ssam u64 prc_alarm_action; 703171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP BIT(3) 704171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP BIT(7) 705171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP BIT(11) 706171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP BIT(15) 707171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP BIT(19) 708171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP BIT(23) 709171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP BIT(27) 710171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP BIT(31) 711171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP BIT(35) 712171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP BIT(39) 713171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP BIT(43) 714171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP BIT(47) 715171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP BIT(51) 716171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP BIT(55) 717171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP BIT(59) 718171095Ssam#define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP BIT(63) 719171095Ssam 720171095Ssam/* Receive traffic interrupts */ 721171095Ssam u64 rti_command_mem; 722171095Ssam#define XGE_HAL_RTI_CMD_MEM_WE BIT(7) 723171095Ssam#define XGE_HAL_RTI_CMD_MEM_STROBE BIT(15) 724171095Ssam#define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 725171095Ssam#define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15) 726171095Ssam#define XGE_HAL_RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) 727171095Ssam 728171095Ssam u64 rti_data1_mem; 729171095Ssam#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) 730171095Ssam#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38) 731171095Ssam#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39) 732171095Ssam#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) 733171095Ssam#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) 734171095Ssam#define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) 735171095Ssam 736171095Ssam u64 rti_data2_mem; 737171095Ssam#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) 738171095Ssam#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) 739171095Ssam#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) 740171095Ssam#define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) 741171095Ssam 742171095Ssam u64 rx_pa_cfg; 743171095Ssam#define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR BIT(1) 744171095Ssam#define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 745171095Ssam#define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 746171095Ssam#define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n) vBIT(n,6,1) 747171095Ssam#define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1) 748171095Ssam 749171095Ssam u8 unused13_0[0x8]; 750171095Ssam 751171095Ssam u64 ring_bump_counter1; 752171095Ssam u64 ring_bump_counter2; 753171095Ssam#define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4)))) 754171095Ssam 755171095Ssam u8 unused13[0x700 - 0x1f0]; 756171095Ssam 757171095Ssam u64 rxdma_debug_ctrl; 758171095Ssam 759171095Ssam u8 unused14[0x2000 - 0x1f08]; 760171095Ssam 761171095Ssam/* Media Access Controller Register */ 762171095Ssam u64 mac_int_status; 763171095Ssam u64 mac_int_mask; 764171095Ssam#define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0) 765171095Ssam#define XGE_HAL_MAC_INT_STATUS_RMAC_INT BIT(1) 766171095Ssam 767171095Ssam u64 mac_tmac_err_reg; 768173139Srwatson#define XGE_HAL_TMAC_ECC_DB_ERR BIT(15) 769173139Srwatson#define XGE_HAL_TMAC_TX_BUF_OVRN BIT(23) 770173139Srwatson#define XGE_HAL_TMAC_TX_CRI_ERR BIT(31) 771173139Srwatson#define XGE_HAL_TMAC_TX_SM_ERR BIT(39) 772171095Ssam u64 mac_tmac_err_mask; 773171095Ssam u64 mac_tmac_err_alarm; 774171095Ssam 775171095Ssam u64 mac_rmac_err_reg; 776173139Srwatson#define XGE_HAL_RMAC_RX_BUFF_OVRN BIT(0) 777173139Srwatson#define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR BIT(0) 778173139Srwatson#define XGE_HAL_RMAC_RTS_ECC_DB_ERR BIT(0) 779173139Srwatson#define XGE_HAL_RMAC_ECC_DB_ERR BIT(0) 780173139Srwatson#define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR BIT(0) 781173139Srwatson#define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(0) 782173139Srwatson#define XGE_HAL_RMAC_RX_SM_ERR BIT(39) 783171095Ssam u64 mac_rmac_err_mask; 784171095Ssam u64 mac_rmac_err_alarm; 785171095Ssam 786171095Ssam u8 unused15[0x100 - 0x40]; 787171095Ssam 788171095Ssam u64 mac_cfg; 789171095Ssam#define XGE_HAL_MAC_CFG_TMAC_ENABLE BIT(0) 790171095Ssam#define XGE_HAL_MAC_CFG_RMAC_ENABLE BIT(1) 791171095Ssam#define XGE_HAL_MAC_CFG_LAN_NOT_WAN BIT(2) 792171095Ssam#define XGE_HAL_MAC_CFG_TMAC_LOOPBACK BIT(3) 793171095Ssam#define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD BIT(4) 794171095Ssam#define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS BIT(5) 795171095Ssam#define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD BIT(6) 796171095Ssam#define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE BIT(7) 797171095Ssam#define XGE_HAL_MAC_RMAC_DISCARD_PFRM BIT(8) 798171095Ssam#define XGE_HAL_MAC_RMAC_BCAST_ENABLE BIT(9) 799171095Ssam#define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE BIT(10) 800171095Ssam#define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) 801171095Ssam 802171095Ssam u64 tmac_avg_ipg; 803171095Ssam#define XGE_HAL_TMAC_AVG_IPG(val) vBIT(val,0,8) 804171095Ssam 805171095Ssam u64 rmac_max_pyld_len; 806171095Ssam#define XGE_HAL_RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) 807171095Ssam 808171095Ssam u64 rmac_err_cfg; 809171095Ssam#define XGE_HAL_RMAC_ERR_FCS BIT(0) 810171095Ssam#define XGE_HAL_RMAC_ERR_FCS_ACCEPT BIT(1) 811171095Ssam#define XGE_HAL_RMAC_ERR_TOO_LONG BIT(1) 812171095Ssam#define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT BIT(1) 813171095Ssam#define XGE_HAL_RMAC_ERR_RUNT BIT(2) 814171095Ssam#define XGE_HAL_RMAC_ERR_RUNT_ACCEPT BIT(2) 815171095Ssam#define XGE_HAL_RMAC_ERR_LEN_MISMATCH BIT(3) 816171095Ssam#define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3) 817171095Ssam 818171095Ssam u64 rmac_cfg_key; 819171095Ssam#define XGE_HAL_RMAC_CFG_KEY(val) vBIT(val,0,16) 820171095Ssam 821171095Ssam#define XGE_HAL_MAX_MAC_ADDRESSES 64 822171095Ssam#define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET 63 823171095Ssam#define XGE_HAL_MAX_MAC_ADDRESSES_HERC 256 824171095Ssam#define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET_HERC 255 825171095Ssam 826171095Ssam u64 rmac_addr_cmd_mem; 827171095Ssam#define XGE_HAL_RMAC_ADDR_CMD_MEM_WE BIT(7) 828171095Ssam#define XGE_HAL_RMAC_ADDR_CMD_MEM_RD 0 829171095Ssam#define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15) 830171095Ssam#define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15) 831171095Ssam#define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) 832171095Ssam 833171095Ssam u64 rmac_addr_data0_mem; 834171095Ssam#define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) 835171095Ssam#define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER BIT(48) 836171095Ssam 837171095Ssam u64 rmac_addr_data1_mem; 838171095Ssam#define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) 839171095Ssam 840171095Ssam u8 unused16[0x8]; 841171095Ssam 842171095Ssam/* 843173139Srwatson u64 rmac_addr_cfg; 844171095Ssam#define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) 845171095Ssam#define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) 846171095Ssam#define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48 847171095Ssam#define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 848171095Ssam*/ 849171095Ssam u64 tmac_ipg_cfg; 850171095Ssam 851171095Ssam u64 rmac_pause_cfg; 852171095Ssam#define XGE_HAL_RMAC_PAUSE_GEN_EN BIT(0) 853171095Ssam#define XGE_HAL_RMAC_PAUSE_RCV_EN BIT(1) 854171095Ssam#define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) 855171095Ssam#define XGE_HAL_RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) 856171095Ssam 857171095Ssam u64 rmac_red_cfg; 858171095Ssam 859171095Ssam u64 rmac_red_rate_q0q3; 860171095Ssam u64 rmac_red_rate_q4q7; 861171095Ssam 862171095Ssam u64 mac_link_util; 863171095Ssam#define XGE_HAL_MAC_TX_LINK_UTIL vBIT(0xFE,1,7) 864171095Ssam#define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) 865171095Ssam#define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) 866171095Ssam#define XGE_HAL_MAC_RX_LINK_UTIL vBIT(0xFE,33,7) 867171095Ssam#define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) 868171095Ssam#define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) 869171095Ssam 870171095Ssam#define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \ 871173139Srwatson XGE_HAL_MAC_RX_LINK_UTIL_DISABLE) 872171095Ssam 873171095Ssam u64 rmac_invalid_ipg; 874171095Ssam 875171095Ssam/* rx traffic steering */ 876173139Srwatson#define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) 877171095Ssam u64 rts_frm_len_n[8]; 878171095Ssam 879171095Ssam u64 rts_qos_steering; 880171095Ssam 881171095Ssam#define XGE_HAL_MAX_DIX_MAP 4 882171095Ssam u64 rts_dix_map_n[XGE_HAL_MAX_DIX_MAP]; 883171095Ssam#define XGE_HAL_RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) 884171095Ssam#define XGE_HAL_RTS_DIX_MAP_SCW(val) BIT(val,21) 885171095Ssam 886171095Ssam u64 rts_q_alternates; 887171095Ssam u64 rts_default_q; 888173139Srwatson#define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3) 889171095Ssam 890171095Ssam u64 rts_ctrl; 891171095Ssam#define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI BIT(2) 892171095Ssam#define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL BIT(3) 893173139Srwatson#define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7) 894171095Ssam 895171095Ssam u64 rts_pn_cam_ctrl; 896171095Ssam#define XGE_HAL_RTS_PN_CAM_CTRL_WE BIT(7) 897171095Ssam#define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15) 898171095Ssam#define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15) 899171095Ssam#define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) 900171095Ssam u64 rts_pn_cam_data; 901171095Ssam#define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT BIT(7) 902171095Ssam#define XGE_HAL_RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) 903171095Ssam#define XGE_HAL_RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) 904171095Ssam 905171095Ssam u64 rts_ds_mem_ctrl; 906171095Ssam#define XGE_HAL_RTS_DS_MEM_CTRL_WE BIT(7) 907171095Ssam#define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15) 908171095Ssam#define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15) 909171095Ssam#define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) 910171095Ssam u64 rts_ds_mem_data; 911171095Ssam#define XGE_HAL_RTS_DS_MEM_DATA(n) vBIT(n,0,8) 912171095Ssam 913171095Ssam u8 unused16_1[0x308 - 0x220]; 914171095Ssam 915171095Ssam u64 rts_vid_mem_ctrl; 916171095Ssam u64 rts_vid_mem_data; 917171095Ssam u64 rts_p0_p3_map; 918171095Ssam u64 rts_p4_p7_map; 919171095Ssam u64 rts_p8_p11_map; 920171095Ssam u64 rts_p12_p15_map; 921171095Ssam 922171095Ssam u64 rts_mac_cfg; 923171095Ssam#define XGE_HAL_RTS_MAC_SECT0_EN BIT(0) 924171095Ssam#define XGE_HAL_RTS_MAC_SECT1_EN BIT(1) 925171095Ssam#define XGE_HAL_RTS_MAC_SECT2_EN BIT(2) 926171095Ssam#define XGE_HAL_RTS_MAC_SECT3_EN BIT(3) 927171095Ssam#define XGE_HAL_RTS_MAC_SECT4_EN BIT(4) 928171095Ssam#define XGE_HAL_RTS_MAC_SECT5_EN BIT(5) 929171095Ssam#define XGE_HAL_RTS_MAC_SECT6_EN BIT(6) 930171095Ssam#define XGE_HAL_RTS_MAC_SECT7_EN BIT(7) 931171095Ssam 932171095Ssam u8 unused16_2[0x380 - 0x340]; 933171095Ssam 934171095Ssam u64 rts_rth_cfg; 935171095Ssam#define XGE_HAL_RTS_RTH_EN BIT(3) 936171095Ssam#define XGE_HAL_RTS_RTH_BUCKET_SIZE(n) vBIT(n,4,4) 937171095Ssam#define XGE_HAL_RTS_RTH_ALG_SEL_MS BIT(11) 938171095Ssam#define XGE_HAL_RTS_RTH_TCP_IPV4_EN BIT(15) 939171095Ssam#define XGE_HAL_RTS_RTH_UDP_IPV4_EN BIT(19) 940171095Ssam#define XGE_HAL_RTS_RTH_IPV4_EN BIT(23) 941171095Ssam#define XGE_HAL_RTS_RTH_TCP_IPV6_EN BIT(27) 942171095Ssam#define XGE_HAL_RTS_RTH_UDP_IPV6_EN BIT(31) 943171095Ssam#define XGE_HAL_RTS_RTH_IPV6_EN BIT(35) 944171095Ssam#define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN BIT(39) 945171095Ssam#define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN BIT(43) 946171095Ssam#define XGE_HAL_RTS_RTH_IPV6_EX_EN BIT(47) 947171095Ssam 948171095Ssam u64 rts_rth_map_mem_ctrl; 949171095Ssam#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE BIT(7) 950171095Ssam#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE BIT(15) 951171095Ssam#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 952171095Ssam 953171095Ssam u64 rts_rth_map_mem_data; 954171095Ssam#define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN BIT(3) 955171095Ssam#define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n) vBIT(n,5,3) 956171095Ssam 957171095Ssam u64 rts_rth_spdm_mem_ctrl; 958171095Ssam#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE BIT(15) 959171095Ssam#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n,21,3) 960171095Ssam#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 961171095Ssam 962171095Ssam u64 rts_rth_spdm_mem_data; 963171095Ssam 964171095Ssam u64 rts_rth_jhash_cfg; 965171095Ssam#define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n) vBIT(n,0,32) 966171095Ssam#define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n) vBIT(n,32,32) 967171095Ssam 968171095Ssam u64 rts_rth_hash_mask[5]; /* rth mask's 0...4 */ 969171095Ssam u64 rts_rth_hash_mask_5; 970171095Ssam#define XGE_HAL_RTH_HASH_MASK_5(n) vBIT(n,0,32) 971171095Ssam 972171095Ssam u64 rts_rth_status; 973171095Ssam#define XGE_HAL_RTH_STATUS_SPDM_USE_L4 BIT(3) 974171095Ssam 975171095Ssam u8 unused17[0x400 - 0x3E8]; 976171095Ssam 977171095Ssam u64 rmac_red_fine_q0q3; 978171095Ssam u64 rmac_red_fine_q4q7; 979171095Ssam u64 rmac_pthresh_cross; 980171095Ssam u64 rmac_rthresh_cross; 981171095Ssam u64 rmac_pnum_range[32]; 982171095Ssam 983171095Ssam u64 rmac_mp_crc_0; 984171095Ssam u64 rmac_mp_mask_a_0; 985171095Ssam u64 rmac_mp_mask_b_0; 986171095Ssam 987171095Ssam u64 rmac_mp_crc_1; 988171095Ssam u64 rmac_mp_mask_a_1; 989171095Ssam u64 rmac_mp_mask_b_1; 990171095Ssam 991171095Ssam u64 rmac_mp_crc_2; 992171095Ssam u64 rmac_mp_mask_a_2; 993171095Ssam u64 rmac_mp_mask_b_2; 994171095Ssam 995171095Ssam u64 rmac_mp_crc_3; 996171095Ssam u64 rmac_mp_mask_a_3; 997171095Ssam u64 rmac_mp_mask_b_3; 998171095Ssam 999171095Ssam u64 rmac_mp_crc_4; 1000171095Ssam u64 rmac_mp_mask_a_4; 1001171095Ssam u64 rmac_mp_mask_b_4; 1002171095Ssam 1003171095Ssam u64 rmac_mp_crc_5; 1004171095Ssam u64 rmac_mp_mask_a_5; 1005171095Ssam u64 rmac_mp_mask_b_5; 1006171095Ssam 1007171095Ssam u64 rmac_mp_crc_6; 1008171095Ssam u64 rmac_mp_mask_a_6; 1009171095Ssam u64 rmac_mp_mask_b_6; 1010171095Ssam 1011171095Ssam u64 rmac_mp_crc_7; 1012171095Ssam u64 rmac_mp_mask_a_7; 1013171095Ssam u64 rmac_mp_mask_b_7; 1014171095Ssam 1015171095Ssam u64 mac_ctrl; 1016171095Ssam u64 activity_control; 1017171095Ssam 1018171095Ssam u8 unused17_2[0x700 - 0x5F0]; 1019171095Ssam 1020171095Ssam u64 mac_debug_ctrl; 1021173139Srwatson#define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL 1022171095Ssam 1023171095Ssam u8 unused18[0x2800 - 0x2708]; 1024171095Ssam 1025171095Ssam/* memory controller registers */ 1026171095Ssam u64 mc_int_status; 1027171095Ssam#define XGE_HAL_MC_INT_STATUS_MC_INT BIT(0) 1028171095Ssam u64 mc_int_mask; 1029171095Ssam#define XGE_HAL_MC_INT_MASK_MC_INT BIT(0) 1030171095Ssam 1031171095Ssam u64 mc_err_reg; 1032171095Ssam#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L BIT(2) /* non-Xena */ 1033171095Ssam#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U BIT(3) /* non-Xena */ 1034171095Ssam#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L BIT(4) /* non-Xena */ 1035171095Ssam#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U BIT(5) /* non-Xena */ 1036171095Ssam#define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L BIT(6) 1037171095Ssam#define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U BIT(7) 1038171095Ssam#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L BIT(10) /* non-Xena */ 1039171095Ssam#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U BIT(11) /* non-Xena */ 1040171095Ssam#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L BIT(12) /* non-Xena */ 1041171095Ssam#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U BIT(13) /* non-Xena */ 1042171095Ssam#define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L BIT(14) 1043171095Ssam#define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U BIT(15) 1044171095Ssam#define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 BIT(17) 1045171095Ssam#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) /* Xena: reset */ 1046171095Ssam#define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 BIT(19) 1047171095Ssam#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) /* Xena: reset */ 1048171095Ssam#define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22) 1049171095Ssam#define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23) 1050171095Ssam#define XGE_HAL_MC_ERR_REG_SM_ERR BIT(31) 1051171095Ssam#define XGE_HAL_MC_ERR_REG_PL_LOCK_N BIT(39) 1052171095Ssam 1053171095Ssam u64 mc_err_mask; 1054171095Ssam u64 mc_err_alarm; 1055171095Ssam 1056171095Ssam u8 unused19[0x100 - 0x28]; 1057171095Ssam 1058171095Ssam/* MC configuration */ 1059171095Ssam u64 rx_queue_cfg; 1060171095Ssam#define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) 1061171095Ssam#define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) 1062171095Ssam#define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) 1063171095Ssam#define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) 1064171095Ssam#define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) 1065171095Ssam#define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) 1066171095Ssam#define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) 1067171095Ssam#define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) 1068171095Ssam 1069171095Ssam u64 mc_rldram_mrs; 1070173139Srwatson#define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) 1071173139Srwatson#define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47) 1072171095Ssam 1073171095Ssam u64 mc_rldram_interleave; 1074171095Ssam 1075171095Ssam u64 mc_pause_thresh_q0q3; 1076171095Ssam u64 mc_pause_thresh_q4q7; 1077171095Ssam 1078171095Ssam u64 mc_red_thresh_q[8]; 1079171095Ssam 1080171095Ssam u8 unused20[0x200 - 0x168]; 1081171095Ssam u64 mc_rldram_ref_per; 1082171095Ssam u8 unused21[0x220 - 0x208]; 1083171095Ssam u64 mc_rldram_test_ctrl; 1084173139Srwatson#define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47) 1085173139Srwatson#define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7) 1086173139Srwatson#define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15) 1087173139Srwatson#define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23) 1088173139Srwatson#define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31) 1089171095Ssam 1090171095Ssam u8 unused22[0x240 - 0x228]; 1091171095Ssam u64 mc_rldram_test_add; 1092171095Ssam u8 unused23[0x260 - 0x248]; 1093171095Ssam u64 mc_rldram_test_d0; 1094171095Ssam u8 unused24[0x280 - 0x268]; 1095171095Ssam u64 mc_rldram_test_d1; 1096171095Ssam u8 unused25[0x300 - 0x288]; 1097171095Ssam u64 mc_rldram_test_d2; 1098171095Ssam u8 unused26_1[0x2C00 - 0x2B08]; 1099171095Ssam u64 mc_rldram_test_read_d0; 1100171095Ssam u8 unused26_2[0x20 - 0x8]; 1101171095Ssam u64 mc_rldram_test_read_d1; 1102171095Ssam u8 unused26_3[0x40 - 0x28]; 1103171095Ssam u64 mc_rldram_test_read_d2; 1104171095Ssam u8 unused26_4[0x60 - 0x48]; 1105171095Ssam u64 mc_rldram_test_add_bkg; 1106171095Ssam u8 unused26_5[0x80 - 0x68]; 1107171095Ssam u64 mc_rldram_test_d0_bkg; 1108171095Ssam u8 unused26_6[0xD00 - 0xC88]; 1109171095Ssam u64 mc_rldram_test_d1_bkg; 1110171095Ssam u8 unused26_7[0x20 - 0x8]; 1111171095Ssam u64 mc_rldram_test_d2_bkg; 1112171095Ssam u8 unused26_8[0x40 - 0x28]; 1113171095Ssam u64 mc_rldram_test_read_d0_bkg; 1114171095Ssam u8 unused26_9[0x60 - 0x48]; 1115171095Ssam u64 mc_rldram_test_read_d1_bkg; 1116171095Ssam u8 unused26_10[0x80 - 0x68]; 1117171095Ssam u64 mc_rldram_test_read_d2_bkg; 1118171095Ssam u8 unused26_11[0xE00 - 0xD88]; 1119171095Ssam u64 mc_rldram_generation; 1120171095Ssam u8 unused26_12[0x20 - 0x8]; 1121171095Ssam u64 mc_driver; 1122171095Ssam u8 unused26_13[0x40 - 0x28]; 1123171095Ssam u64 mc_rldram_ref_per_herc; 1124171095Ssam#define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n) vBIT(n, 0, 16) 1125171095Ssam u8 unused26_14[0x660 - 0x648]; 1126171095Ssam u64 mc_rldram_mrs_herc; 1127171095Ssam#define XGE_HAL_MC_RLDRAM_MRS(n) vBIT(n, 14, 17) 1128171095Ssam u8 unused26_15[0x700 - 0x668]; 1129171095Ssam u64 mc_debug_ctrl; 1130171095Ssam 1131171095Ssam u8 unused27[0x3000 - 0x2f08]; 1132171095Ssam 1133171095Ssam/* XGXG */ 1134171095Ssam /* XGXS control registers */ 1135171095Ssam 1136171095Ssam u64 xgxs_int_status; 1137171095Ssam#define XGE_HAL_XGXS_INT_STATUS_TXGXS BIT(0) 1138171095Ssam#define XGE_HAL_XGXS_INT_STATUS_RXGXS BIT(1) 1139171095Ssam u64 xgxs_int_mask; 1140171095Ssam#define XGE_HAL_XGXS_INT_MASK_TXGXS BIT(0) 1141171095Ssam#define XGE_HAL_XGXS_INT_MASK_RXGXS BIT(1) 1142171095Ssam 1143171095Ssam u64 xgxs_txgxs_err_reg; 1144173139Srwatson#define XGE_HAL_TXGXS_ECC_SG_ERR BIT(7) 1145173139Srwatson#define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15) 1146173139Srwatson#define XGE_HAL_TXGXS_ESTORE_UFLOW BIT(31) 1147173139Srwatson#define XGE_HAL_TXGXS_TX_SM_ERR BIT(39) 1148171095Ssam u64 xgxs_txgxs_err_mask; 1149171095Ssam u64 xgxs_txgxs_err_alarm; 1150171095Ssam 1151171095Ssam u64 xgxs_rxgxs_err_reg; 1152173139Srwatson#define XGE_HAL_RXGXS_ESTORE_OFLOW BIT(7) 1153173139Srwatson#define XGE_HAL_RXGXS_RX_SM_ERR BIT(39) 1154171095Ssam u64 xgxs_rxgxs_err_mask; 1155171095Ssam u64 xgxs_rxgxs_err_alarm; 1156171095Ssam 1157171095Ssam u64 spi_err_reg; 1158171095Ssam u64 spi_err_mask; 1159171095Ssam u64 spi_err_alarm; 1160171095Ssam 1161171095Ssam u8 unused28[0x100 - 0x58]; 1162171095Ssam 1163171095Ssam u64 xgxs_cfg; 1164171095Ssam u64 xgxs_status; 1165171095Ssam 1166171095Ssam u64 xgxs_cfg_key; 1167171095Ssam u64 xgxs_efifo_cfg; /* CHANGED */ 1168171095Ssam u64 rxgxs_ber_0; /* CHANGED */ 1169171095Ssam u64 rxgxs_ber_1; /* CHANGED */ 1170171095Ssam 1171171095Ssam u64 spi_control; 1172171095Ssam u64 spi_data; 1173171095Ssam u64 spi_write_protect; 1174171095Ssam 1175171095Ssam u8 unused29[0x80 - 0x48]; 1176171095Ssam 1177171095Ssam u64 xgxs_cfg_1; 1178171095Ssam} xge_hal_pci_bar0_t; 1179171095Ssam 1180171095Ssam/* Using this strcture to calculate offsets */ 1181171095Ssamtypedef struct xge_hal_pci_config_le_t { 1182173139Srwatson u16 vendor_id; // 0x00 1183173139Srwatson u16 device_id; // 0x02 1184171095Ssam 1185173139Srwatson u16 command; // 0x04 1186173139Srwatson u16 status; // 0x06 1187171095Ssam 1188173139Srwatson u8 revision; // 0x08 1189173139Srwatson u8 pciClass[3]; // 0x09 1190171095Ssam 1191173139Srwatson u8 cache_line_size; // 0x0c 1192173139Srwatson u8 latency_timer; // 0x0d 1193173139Srwatson u8 header_type; // 0x0e 1194173139Srwatson u8 bist; // 0x0f 1195171095Ssam 1196173139Srwatson u32 base_addr0_lo; // 0x10 1197173139Srwatson u32 base_addr0_hi; // 0x14 1198171095Ssam 1199173139Srwatson u32 base_addr1_lo; // 0x18 1200173139Srwatson u32 base_addr1_hi; // 0x1C 1201171095Ssam 1202173139Srwatson u32 not_Implemented1; // 0x20 1203173139Srwatson u32 not_Implemented2; // 0x24 1204171095Ssam 1205173139Srwatson u32 cardbus_cis_pointer; // 0x28 1206171095Ssam 1207173139Srwatson u16 subsystem_vendor_id; // 0x2c 1208173139Srwatson u16 subsystem_id; // 0x2e 1209171095Ssam 1210173139Srwatson u32 rom_base; // 0x30 1211173139Srwatson u8 capabilities_pointer; // 0x34 1212173139Srwatson u8 rsvd_35[3]; // 0x35 1213173139Srwatson u32 rsvd_38; // 0x38 1214171095Ssam 1215173139Srwatson u8 interrupt_line; // 0x3c 1216173139Srwatson u8 interrupt_pin; // 0x3d 1217173139Srwatson u8 min_grant; // 0x3e 1218173139Srwatson u8 max_latency; // 0x3f 1219171095Ssam 1220173139Srwatson u8 msi_cap_id; // 0x40 1221173139Srwatson u8 msi_next_ptr; // 0x41 1222173139Srwatson u16 msi_control; // 0x42 1223173139Srwatson u32 msi_lower_address; // 0x44 1224173139Srwatson u32 msi_higher_address; // 0x48 1225173139Srwatson u16 msi_data; // 0x4c 1226173139Srwatson u16 msi_unused; // 0x4e 1227171095Ssam 1228173139Srwatson u8 vpd_cap_id; // 0x50 1229173139Srwatson u8 vpd_next_cap; // 0x51 1230173139Srwatson u16 vpd_addr; // 0x52 1231173139Srwatson u32 vpd_data; // 0x54 1232171095Ssam 1233173139Srwatson u8 rsvd_b0[8]; // 0x58 1234171095Ssam 1235173139Srwatson u8 pcix_cap; // 0x60 1236173139Srwatson u8 pcix_next_cap; // 0x61 1237173139Srwatson u16 pcix_command; // 0x62 1238171095Ssam 1239173139Srwatson u32 pcix_status; // 0x64 1240171095Ssam 1241173139Srwatson u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1242171095Ssam} xge_hal_pci_config_le_t; // 0x100 1243171095Ssam 1244171095Ssamtypedef struct xge_hal_pci_config_t { 1245171095Ssam#ifdef XGE_OS_HOST_BIG_ENDIAN 1246173139Srwatson u16 device_id; // 0x02 1247173139Srwatson u16 vendor_id; // 0x00 1248171095Ssam 1249173139Srwatson u16 status; // 0x06 1250173139Srwatson u16 command; // 0x04 1251171095Ssam 1252173139Srwatson u8 pciClass[3]; // 0x09 1253173139Srwatson u8 revision; // 0x08 1254171095Ssam 1255173139Srwatson u8 bist; // 0x0f 1256173139Srwatson u8 header_type; // 0x0e 1257173139Srwatson u8 latency_timer; // 0x0d 1258173139Srwatson u8 cache_line_size; // 0x0c 1259171095Ssam 1260173139Srwatson u32 base_addr0_lo; // 0x10 1261173139Srwatson u32 base_addr0_hi; // 0x14 1262171095Ssam 1263173139Srwatson u32 base_addr1_lo; // 0x18 1264173139Srwatson u32 base_addr1_hi; // 0x1C 1265171095Ssam 1266173139Srwatson u32 not_Implemented1; // 0x20 1267173139Srwatson u32 not_Implemented2; // 0x24 1268171095Ssam 1269173139Srwatson u32 cardbus_cis_pointer; // 0x28 1270171095Ssam 1271173139Srwatson u16 subsystem_id; // 0x2e 1272173139Srwatson u16 subsystem_vendor_id; // 0x2c 1273171095Ssam 1274173139Srwatson u32 rom_base; // 0x30 1275173139Srwatson u8 rsvd_35[3]; // 0x35 1276173139Srwatson u8 capabilities_pointer; // 0x34 1277173139Srwatson u32 rsvd_38; // 0x38 1278171095Ssam 1279173139Srwatson u8 max_latency; // 0x3f 1280173139Srwatson u8 min_grant; // 0x3e 1281173139Srwatson u8 interrupt_pin; // 0x3d 1282173139Srwatson u8 interrupt_line; // 0x3c 1283171095Ssam 1284173139Srwatson u16 msi_control; // 0x42 1285173139Srwatson u8 msi_next_ptr; // 0x41 1286173139Srwatson u8 msi_cap_id; // 0x40 1287173139Srwatson u32 msi_lower_address; // 0x44 1288173139Srwatson u32 msi_higher_address; // 0x48 1289173139Srwatson u16 msi_unused; // 0x4e 1290173139Srwatson u16 msi_data; // 0x4c 1291171095Ssam 1292173139Srwatson u16 vpd_addr; // 0x52 1293173139Srwatson u8 vpd_next_cap; // 0x51 1294173139Srwatson u8 vpd_cap_id; // 0x50 1295173139Srwatson u32 vpd_data; // 0x54 1296171095Ssam 1297173139Srwatson u8 rsvd_b0[8]; // 0x58 1298171095Ssam 1299173139Srwatson u16 pcix_command; // 0x62 1300173139Srwatson u8 pcix_next_cap; // 0x61 1301173139Srwatson u8 pcix_cap; // 0x60 1302171095Ssam 1303173139Srwatson u32 pcix_status; // 0x64 1304171095Ssam#else 1305173139Srwatson u16 vendor_id; // 0x00 1306173139Srwatson u16 device_id; // 0x02 1307171095Ssam 1308173139Srwatson u16 command; // 0x04 1309173139Srwatson u16 status; // 0x06 1310171095Ssam 1311173139Srwatson u8 revision; // 0x08 1312173139Srwatson u8 pciClass[3]; // 0x09 1313171095Ssam 1314173139Srwatson u8 cache_line_size; // 0x0c 1315173139Srwatson u8 latency_timer; // 0x0d 1316173139Srwatson u8 header_type; // 0x0e 1317173139Srwatson u8 bist; // 0x0f 1318171095Ssam 1319173139Srwatson u32 base_addr0_lo; // 0x10 1320173139Srwatson u32 base_addr0_hi; // 0x14 1321171095Ssam 1322173139Srwatson u32 base_addr1_lo; // 0x18 1323173139Srwatson u32 base_addr1_hi; // 0x1C 1324171095Ssam 1325173139Srwatson u32 not_Implemented1; // 0x20 1326173139Srwatson u32 not_Implemented2; // 0x24 1327171095Ssam 1328173139Srwatson u32 cardbus_cis_pointer; // 0x28 1329171095Ssam 1330173139Srwatson u16 subsystem_vendor_id; // 0x2c 1331173139Srwatson u16 subsystem_id; // 0x2e 1332171095Ssam 1333173139Srwatson u32 rom_base; // 0x30 1334173139Srwatson u8 capabilities_pointer; // 0x34 1335173139Srwatson u8 rsvd_35[3]; // 0x35 1336173139Srwatson u32 rsvd_38; // 0x38 1337171095Ssam 1338173139Srwatson u8 interrupt_line; // 0x3c 1339173139Srwatson u8 interrupt_pin; // 0x3d 1340173139Srwatson u8 min_grant; // 0x3e 1341173139Srwatson u8 max_latency; // 0x3f 1342171095Ssam 1343173139Srwatson u8 msi_cap_id; // 0x40 1344173139Srwatson u8 msi_next_ptr; // 0x41 1345173139Srwatson u16 msi_control; // 0x42 1346173139Srwatson u32 msi_lower_address; // 0x44 1347173139Srwatson u32 msi_higher_address; // 0x48 1348173139Srwatson u16 msi_data; // 0x4c 1349173139Srwatson u16 msi_unused; // 0x4e 1350171095Ssam 1351173139Srwatson u8 vpd_cap_id; // 0x50 1352173139Srwatson u8 vpd_next_cap; // 0x51 1353173139Srwatson u16 vpd_addr; // 0x52 1354173139Srwatson u32 vpd_data; // 0x54 1355171095Ssam 1356173139Srwatson u8 rsvd_b0[8]; // 0x58 1357171095Ssam 1358173139Srwatson u8 pcix_cap; // 0x60 1359173139Srwatson u8 pcix_next_cap; // 0x61 1360173139Srwatson u16 pcix_command; // 0x62 1361171095Ssam 1362173139Srwatson u32 pcix_status; // 0x64 1363171095Ssam 1364171095Ssam#endif 1365173139Srwatson u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1366171095Ssam} xge_hal_pci_config_t; // 0x100 1367171095Ssam 1368173139Srwatson#define XGE_HAL_REG_SPACE sizeof(xge_hal_pci_bar0_t) 1369173139Srwatson#define XGE_HAL_EEPROM_SIZE (0x01 << 11) 1370171095Ssam 1371173139Srwatson__EXTERN_END_DECLS 1372173139Srwatson 1373171095Ssam#endif /* XGE_HAL_REGS_H */ 1374