1321936Shselasky/* 2321936Shselasky * Copyright (c) 2012 Mellanox Technologies, Inc. All rights reserved. 3321936Shselasky * 4321936Shselasky * This software is available to you under a choice of one of two 5321936Shselasky * licenses. You may choose to be licensed under the terms of the GNU 6321936Shselasky * General Public License (GPL) Version 2, available from the file 7321936Shselasky * COPYING in the main directory of this source tree, or the 8321936Shselasky * OpenIB.org BSD license below: 9321936Shselasky * 10321936Shselasky * Redistribution and use in source and binary forms, with or 11321936Shselasky * without modification, are permitted provided that the following 12321936Shselasky * conditions are met: 13321936Shselasky * 14321936Shselasky * - Redistributions of source code must retain the above 15321936Shselasky * copyright notice, this list of conditions and the following 16321936Shselasky * disclaimer. 17321936Shselasky * 18321936Shselasky * - Redistributions in binary form must reproduce the above 19321936Shselasky * copyright notice, this list of conditions and the following 20321936Shselasky * disclaimer in the documentation and/or other materials 21321936Shselasky * provided with the distribution. 22321936Shselasky * 23321936Shselasky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24321936Shselasky * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25321936Shselasky * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26321936Shselasky * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27321936Shselasky * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28321936Shselasky * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29321936Shselasky * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30321936Shselasky * SOFTWARE. 31321936Shselasky */ 32321936Shselasky 33321936Shselasky#ifndef MLX5_ABI_H 34321936Shselasky#define MLX5_ABI_H 35321936Shselasky 36321936Shselasky#include <infiniband/kern-abi.h> 37321936Shselasky#include <infiniband/verbs.h> 38321936Shselasky#include "mlx5dv.h" 39321936Shselasky 40321936Shselasky#define MLX5_UVERBS_MIN_ABI_VERSION 1 41321936Shselasky#define MLX5_UVERBS_MAX_ABI_VERSION 1 42321936Shselasky 43321936Shselaskyenum { 44321936Shselasky MLX5_QP_FLAG_SIGNATURE = 1 << 0, 45321936Shselasky MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 46321936Shselasky}; 47321936Shselasky 48321936Shselaskyenum { 49321936Shselasky MLX5_RWQ_FLAG_SIGNATURE = 1 << 0, 50321936Shselasky}; 51321936Shselasky 52321936Shselaskyenum { 53321936Shselasky MLX5_NUM_NON_FP_BFREGS_PER_UAR = 2, 54321936Shselasky NUM_BFREGS_PER_UAR = 4, 55321936Shselasky MLX5_MAX_UARS = 1 << 8, 56321936Shselasky MLX5_MAX_BFREGS = MLX5_MAX_UARS * MLX5_NUM_NON_FP_BFREGS_PER_UAR, 57321936Shselasky MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_NON_FP_BFREGS_PER_UAR, 58321936Shselasky MLX5_MED_BFREGS_TSHOLD = 12, 59321936Shselasky}; 60321936Shselasky 61321936Shselaskyenum mlx5_lib_caps { 62321936Shselasky MLX5_LIB_CAP_4K_UAR = 1 << 0, 63321936Shselasky}; 64321936Shselasky 65321936Shselaskystruct mlx5_alloc_ucontext { 66321936Shselasky struct ibv_get_context ibv_req; 67321936Shselasky __u32 total_num_uuars; 68321936Shselasky __u32 num_low_latency_uuars; 69321936Shselasky __u32 flags; 70321936Shselasky __u32 comp_mask; 71321936Shselasky __u8 cqe_version; 72321936Shselasky __u8 reserved0; 73321936Shselasky __u16 reserved1; 74321936Shselasky __u32 reserved2; 75321936Shselasky __u64 lib_caps; 76321936Shselasky}; 77321936Shselasky 78321936Shselaskyenum mlx5_ib_alloc_ucontext_resp_mask { 79321936Shselasky MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 80321936Shselasky}; 81321936Shselasky 82321936Shselaskystruct mlx5_alloc_ucontext_resp { 83321936Shselasky struct ibv_get_context_resp ibv_resp; 84321936Shselasky __u32 qp_tab_size; 85321936Shselasky __u32 bf_reg_size; 86321936Shselasky __u32 tot_uuars; 87321936Shselasky __u32 cache_line_size; 88321936Shselasky __u16 max_sq_desc_sz; 89321936Shselasky __u16 max_rq_desc_sz; 90321936Shselasky __u32 max_send_wqebb; 91321936Shselasky __u32 max_recv_wr; 92321936Shselasky __u32 max_srq_recv_wr; 93321936Shselasky __u16 num_ports; 94321936Shselasky __u16 reserved1; 95321936Shselasky __u32 comp_mask; 96321936Shselasky __u32 response_length; 97321936Shselasky __u8 cqe_version; 98321936Shselasky __u8 cmds_supp_uhw; 99321936Shselasky __u16 reserved2; 100321936Shselasky __u64 hca_core_clock_offset; 101321936Shselasky __u32 log_uar_size; 102321936Shselasky __u32 num_uars_per_page; 103321936Shselasky}; 104321936Shselasky 105321936Shselaskystruct mlx5_create_ah_resp { 106321936Shselasky struct ibv_create_ah_resp ibv_resp; 107321936Shselasky __u32 response_length; 108321936Shselasky __u8 dmac[ETHERNET_LL_SIZE]; 109321936Shselasky __u8 reserved[6]; 110321936Shselasky}; 111321936Shselasky 112321936Shselaskystruct mlx5_alloc_pd_resp { 113321936Shselasky struct ibv_alloc_pd_resp ibv_resp; 114321936Shselasky __u32 pdn; 115321936Shselasky}; 116321936Shselasky 117321936Shselaskystruct mlx5_create_cq { 118321936Shselasky struct ibv_create_cq ibv_cmd; 119321936Shselasky __u64 buf_addr; 120321936Shselasky __u64 db_addr; 121321936Shselasky __u32 cqe_size; 122321936Shselasky __u8 cqe_comp_en; 123321936Shselasky __u8 cqe_comp_res_format; 124321936Shselasky __u16 reserved; 125321936Shselasky}; 126321936Shselasky 127321936Shselaskystruct mlx5_create_cq_resp { 128321936Shselasky struct ibv_create_cq_resp ibv_resp; 129321936Shselasky __u32 cqn; 130321936Shselasky}; 131321936Shselasky 132321936Shselaskystruct mlx5_create_srq { 133321936Shselasky struct ibv_create_srq ibv_cmd; 134321936Shselasky __u64 buf_addr; 135321936Shselasky __u64 db_addr; 136321936Shselasky __u32 flags; 137321936Shselasky}; 138321936Shselasky 139321936Shselaskystruct mlx5_create_srq_resp { 140321936Shselasky struct ibv_create_srq_resp ibv_resp; 141321936Shselasky __u32 srqn; 142321936Shselasky __u32 reserved; 143321936Shselasky}; 144321936Shselasky 145321936Shselaskystruct mlx5_create_srq_ex { 146321936Shselasky struct ibv_create_xsrq ibv_cmd; 147321936Shselasky __u64 buf_addr; 148321936Shselasky __u64 db_addr; 149321936Shselasky __u32 flags; 150321936Shselasky __u32 reserved; 151321936Shselasky __u32 uidx; 152321936Shselasky __u32 reserved1; 153321936Shselasky}; 154321936Shselasky 155321936Shselaskystruct mlx5_create_qp_drv_ex { 156321936Shselasky __u64 buf_addr; 157321936Shselasky __u64 db_addr; 158321936Shselasky __u32 sq_wqe_count; 159321936Shselasky __u32 rq_wqe_count; 160321936Shselasky __u32 rq_wqe_shift; 161321936Shselasky __u32 flags; 162321936Shselasky __u32 uidx; 163321936Shselasky __u32 reserved; 164321936Shselasky /* SQ buffer address - used for Raw Packet QP */ 165321936Shselasky __u64 sq_buf_addr; 166321936Shselasky}; 167321936Shselasky 168321936Shselaskystruct mlx5_create_qp_ex { 169321936Shselasky struct ibv_create_qp_ex ibv_cmd; 170321936Shselasky struct mlx5_create_qp_drv_ex drv_ex; 171321936Shselasky}; 172321936Shselasky 173321936Shselaskystruct mlx5_create_qp_ex_rss { 174321936Shselasky struct ibv_create_qp_ex ibv_cmd; 175321936Shselasky __u64 rx_hash_fields_mask; /* enum ibv_rx_hash_fields */ 176321936Shselasky __u8 rx_hash_function; /* enum ibv_rx_hash_function_flags */ 177321936Shselasky __u8 rx_key_len; 178321936Shselasky __u8 reserved[6]; 179321936Shselasky __u8 rx_hash_key[128]; 180321936Shselasky __u32 comp_mask; 181321936Shselasky __u32 reserved1; 182321936Shselasky}; 183321936Shselasky 184321936Shselaskystruct mlx5_create_qp_resp_ex { 185321936Shselasky struct ibv_create_qp_resp_ex ibv_resp; 186321936Shselasky __u32 uuar_index; 187321936Shselasky __u32 reserved; 188321936Shselasky}; 189321936Shselasky 190321936Shselaskystruct mlx5_create_qp { 191321936Shselasky struct ibv_create_qp ibv_cmd; 192321936Shselasky __u64 buf_addr; 193321936Shselasky __u64 db_addr; 194321936Shselasky __u32 sq_wqe_count; 195321936Shselasky __u32 rq_wqe_count; 196321936Shselasky __u32 rq_wqe_shift; 197321936Shselasky __u32 flags; 198321936Shselasky __u32 uidx; 199321936Shselasky __u32 reserved; 200321936Shselasky /* SQ buffer address - used for Raw Packet QP */ 201321936Shselasky __u64 sq_buf_addr; 202321936Shselasky}; 203321936Shselasky 204321936Shselaskystruct mlx5_create_qp_resp { 205321936Shselasky struct ibv_create_qp_resp ibv_resp; 206321936Shselasky __u32 uuar_index; 207321936Shselasky}; 208321936Shselasky 209321936Shselaskystruct mlx5_drv_create_wq { 210321936Shselasky __u64 buf_addr; 211321936Shselasky __u64 db_addr; 212321936Shselasky __u32 rq_wqe_count; 213321936Shselasky __u32 rq_wqe_shift; 214321936Shselasky __u32 user_index; 215321936Shselasky __u32 flags; 216321936Shselasky __u32 comp_mask; 217321936Shselasky __u32 reserved; 218321936Shselasky}; 219321936Shselasky 220321936Shselaskystruct mlx5_create_wq { 221321936Shselasky struct ibv_create_wq ibv_cmd; 222321936Shselasky struct mlx5_drv_create_wq drv; 223321936Shselasky}; 224321936Shselasky 225321936Shselaskystruct mlx5_create_wq_resp { 226321936Shselasky struct ibv_create_wq_resp ibv_resp; 227321936Shselasky __u32 response_length; 228321936Shselasky __u32 reserved; 229321936Shselasky}; 230321936Shselasky 231321936Shselaskystruct mlx5_modify_wq { 232321936Shselasky struct ibv_modify_wq ibv_cmd; 233321936Shselasky __u32 comp_mask; 234321936Shselasky __u32 reserved; 235321936Shselasky}; 236321936Shselasky 237321936Shselaskystruct mlx5_create_rwq_ind_table_resp { 238321936Shselasky struct ibv_create_rwq_ind_table_resp ibv_resp; 239321936Shselasky}; 240321936Shselasky 241321936Shselaskystruct mlx5_destroy_rwq_ind_table { 242321936Shselasky struct ibv_destroy_rwq_ind_table ibv_cmd; 243321936Shselasky}; 244321936Shselasky 245321936Shselaskystruct mlx5_resize_cq { 246321936Shselasky struct ibv_resize_cq ibv_cmd; 247321936Shselasky __u64 buf_addr; 248321936Shselasky __u16 cqe_size; 249321936Shselasky __u16 reserved0; 250321936Shselasky __u32 reserved1; 251321936Shselasky}; 252321936Shselasky 253321936Shselaskystruct mlx5_resize_cq_resp { 254321936Shselasky struct ibv_resize_cq_resp ibv_resp; 255321936Shselasky}; 256321936Shselasky 257321936Shselaskystruct mlx5_query_device_ex { 258321936Shselasky struct ibv_query_device_ex ibv_cmd; 259321936Shselasky}; 260321936Shselasky 261321936Shselaskystruct mlx5_reserved_tso_caps { 262321936Shselasky __u64 reserved; 263321936Shselasky}; 264321936Shselasky 265321936Shselaskystruct mlx5_rss_caps { 266321936Shselasky __u64 rx_hash_fields_mask; /* enum ibv_rx_hash_fields */ 267321936Shselasky __u8 rx_hash_function; /* enum ibv_rx_hash_function_flags */ 268321936Shselasky __u8 reserved[7]; 269321936Shselasky}; 270321936Shselasky 271321936Shselaskystruct mlx5_packet_pacing_caps { 272321936Shselasky struct ibv_packet_pacing_caps caps; 273321936Shselasky __u32 reserved; 274321936Shselasky}; 275321936Shselasky 276321936Shselaskystruct mlx5_query_device_ex_resp { 277321936Shselasky struct ibv_query_device_resp_ex ibv_resp; 278321936Shselasky __u32 comp_mask; 279321936Shselasky __u32 response_length; 280321936Shselasky struct ibv_tso_caps tso_caps; 281321936Shselasky struct mlx5_rss_caps rss_caps; /* vendor data channel */ 282321936Shselasky struct mlx5dv_cqe_comp_caps cqe_comp_caps; 283321936Shselasky struct mlx5_packet_pacing_caps packet_pacing_caps; 284321936Shselasky __u32 support_multi_pkt_send_wqe; 285321936Shselasky __u32 reserved; 286321936Shselasky}; 287321936Shselasky 288321936Shselasky#endif /* MLX5_ABI_H */ 289