| /freebsd-11-stable/sys/arm/arm/ |
| H A D | cpufunc_asm_arm11.S | 44 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
45 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
66 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
79 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
85 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
91 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
|
| H A D | cpufunc_asm_armv4.S | 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
52 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
57 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
|
| H A D | cpufunc_asm_arm9.S | 50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
233 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
|
| H A D | cpufunc_asm_armv6.S | 56 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
|
| H A D | cpufunc_asm_fa526.S | 51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
63 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */
200 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
|
| H A D | cpufunc_asm_xscale.S | 151 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
169 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
170 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
485 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
|
| H A D | cpufunc_asm_arm11x6.S | 119 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */
|
| H A D | locore-v4.S | 217 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
411 mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
|
| H A D | cpufunc_asm_xscale_c3.S | 361 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
394 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
|
| H A D | cpufunc_asm_armv5_ec.S | 67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
|
| H A D | cpufunc_asm_sheeva.S | 64 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
|
| /freebsd-11-stable/lib/libmp/tests/ |
| H A D | legacy_test.c | 35 MINT *c0, *c1, *c2, *c3, *c5, *c6, *c8, *c10, *c14, *c15, *c25, \ variable
104 testmcmp(t0, c8, "mdiv0");
107 mp_mdiv(c10, c8, t0, t1);
112 testmcmp(t0, c8, "sdiv0");
139 testmcmp(t0, c8, "pow0");
143 testmcmp(t0, c8, "rpow0");
169 c8 = mp_itom(8);
198 mp_mfree(c8);
|
| /freebsd-11-stable/sys/arm/include/ |
| H A D | sysreg.h | 167 #define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */
168 #define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */
169 #define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */
170 #define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */
174 #define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */
175 #define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */
176 #define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged read */
177 #define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */
210 #define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */
211 #define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c
[all...] |
| /freebsd-11-stable/etc/rc.d/ |
| H A D | hostid | 90 dc698397-fa54-4cf2-82c8-b1b5307a6a7f)
|
| /freebsd-11-stable/contrib/libucl/src/ |
| H A D | ucl_hash.c | 130 unsigned char c1, c2, c3, c4, c5, c6, c7, c8; member in struct:__anon2135::__anon2136
141 u.c.c5 = s[i + 4], u.c.c6 = s[i + 5], u.c.c7 = s[i + 6], u.c.c8 = s[i + 7];
149 u.c.c4 = lc_map[u.c.c8];
|
| /freebsd-11-stable/contrib/amd/doc/ |
| H A D | texinfo.tex | 8956 \gdef^^c8{\`E}
9076 \gdef^^c8{\v C}
|