1272209Sandrew/*- 2272209Sandrew * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3272209Sandrew * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4272209Sandrew * All rights reserved. 5272209Sandrew * 6272209Sandrew * Redistribution and use in source and binary forms, with or without 7272209Sandrew * modification, are permitted provided that the following conditions 8272209Sandrew * are met: 9272209Sandrew * 1. Redistributions of source code must retain the above copyright 10272209Sandrew * notice, this list of conditions and the following disclaimer. 11272209Sandrew * 2. Redistributions in binary form must reproduce the above copyright 12272209Sandrew * notice, this list of conditions and the following disclaimer in the 13272209Sandrew * documentation and/or other materials provided with the distribution. 14272209Sandrew * 15272209Sandrew * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16272209Sandrew * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17272209Sandrew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18272209Sandrew * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19272209Sandrew * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20272209Sandrew * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21272209Sandrew * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22272209Sandrew * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23272209Sandrew * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24272209Sandrew * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25272209Sandrew * SUCH DAMAGE. 26272209Sandrew * 27272209Sandrew * $FreeBSD$ 28272209Sandrew */ 29272209Sandrew 30272209Sandrew/* 31272209Sandrew * Macros to make working with the System Control Registers simpler. 32276803Sian * 33276803Sian * Note that when register r0 is hard-coded in these definitions it means the 34276803Sian * cp15 operation neither reads nor writes the register, and r0 is used only 35276803Sian * because some syntatically-valid register name has to appear at that point to 36276803Sian * keep the asm parser happy. 37272209Sandrew */ 38272209Sandrew 39272209Sandrew#ifndef MACHINE_SYSREG_H 40272209Sandrew#define MACHINE_SYSREG_H 41272209Sandrew 42272209Sandrew/* 43294740Szbb * CP14 registers 44294740Szbb */ 45294740Szbb#if __ARM_ARCH >= 6 46294740Szbb 47294740Szbb#define CP14_DBGDIDR(rr) p14, 0, rr, c0, c0, 0 /* Debug ID Register */ 48294740Szbb#define CP14_DBGDSCRext_V6(rr) p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */ 49294740Szbb#define CP14_DBGDSCRext_V7(rr) p14, 0, rr, c0, c2, 2 /* Debug Status and Ctrl Register v7 */ 50294740Szbb#define CP14_DBGVCR(rr) p14, 0, rr, c0, c7, 0 /* Vector Catch Register */ 51294740Szbb#define CP14_DBGOSLAR(rr) p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */ 52294740Szbb#define CP14_DBGOSLSR(rr) p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */ 53294740Szbb#define CP14_DBGOSDLR(rr) p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */ 54294740Szbb#define CP14_DBGPRSR(rr) p14, 0, rr, c1, c5, 4 /* Device Powerdown and Reset Status */ 55294740Szbb 56294740Szbb#define CP14_DBGDSCRint(rr) CP14_DBGDSCRext_V6(rr) /* Debug Status and Ctrl internal view */ 57294740Szbb 58294740Szbb#endif 59294740Szbb 60294740Szbb/* 61272209Sandrew * CP15 C0 registers 62272209Sandrew */ 63272209Sandrew#define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ 64272209Sandrew#define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ 65272209Sandrew#define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ 66272209Sandrew#define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ 67272209Sandrew#define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ 68272209Sandrew#define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ 69272209Sandrew 70272209Sandrew#define CP15_ID_PFR0(rr) p15, 0, rr, c0, c1, 0 /* Processor Feature Register 0 */ 71272209Sandrew#define CP15_ID_PFR1(rr) p15, 0, rr, c0, c1, 1 /* Processor Feature Register 1 */ 72272209Sandrew#define CP15_ID_DFR0(rr) p15, 0, rr, c0, c1, 2 /* Debug Feature Register 0 */ 73272209Sandrew#define CP15_ID_AFR0(rr) p15, 0, rr, c0, c1, 3 /* Auxiliary Feature Register 0 */ 74272209Sandrew#define CP15_ID_MMFR0(rr) p15, 0, rr, c0, c1, 4 /* Memory Model Feature Register 0 */ 75272209Sandrew#define CP15_ID_MMFR1(rr) p15, 0, rr, c0, c1, 5 /* Memory Model Feature Register 1 */ 76272209Sandrew#define CP15_ID_MMFR2(rr) p15, 0, rr, c0, c1, 6 /* Memory Model Feature Register 2 */ 77272209Sandrew#define CP15_ID_MMFR3(rr) p15, 0, rr, c0, c1, 7 /* Memory Model Feature Register 3 */ 78272209Sandrew 79272209Sandrew#define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */ 80272209Sandrew#define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */ 81272209Sandrew#define CP15_ID_ISAR2(rr) p15, 0, rr, c0, c2, 2 /* Instruction Set Attribute Register 2 */ 82272209Sandrew#define CP15_ID_ISAR3(rr) p15, 0, rr, c0, c2, 3 /* Instruction Set Attribute Register 3 */ 83272209Sandrew#define CP15_ID_ISAR4(rr) p15, 0, rr, c0, c2, 4 /* Instruction Set Attribute Register 4 */ 84272209Sandrew#define CP15_ID_ISAR5(rr) p15, 0, rr, c0, c2, 5 /* Instruction Set Attribute Register 5 */ 85272209Sandrew 86272209Sandrew#define CP15_CCSIDR(rr) p15, 1, rr, c0, c0, 0 /* Cache Size ID Registers */ 87272209Sandrew#define CP15_CLIDR(rr) p15, 1, rr, c0, c0, 1 /* Cache Level ID Register */ 88272209Sandrew#define CP15_AIDR(rr) p15, 1, rr, c0, c0, 7 /* Auxiliary ID Register */ 89272209Sandrew 90272209Sandrew#define CP15_CSSELR(rr) p15, 2, rr, c0, c0, 0 /* Cache Size Selection Register */ 91272209Sandrew 92272209Sandrew/* 93272209Sandrew * CP15 C1 registers 94272209Sandrew */ 95272209Sandrew#define CP15_SCTLR(rr) p15, 0, rr, c1, c0, 0 /* System Control Register */ 96272209Sandrew#define CP15_ACTLR(rr) p15, 0, rr, c1, c0, 1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */ 97272209Sandrew#define CP15_CPACR(rr) p15, 0, rr, c1, c0, 2 /* Coprocessor Access Control Register */ 98272209Sandrew 99272209Sandrew#define CP15_SCR(rr) p15, 0, rr, c1, c1, 0 /* Secure Configuration Register */ 100272209Sandrew#define CP15_SDER(rr) p15, 0, rr, c1, c1, 1 /* Secure Debug Enable Register */ 101272209Sandrew#define CP15_NSACR(rr) p15, 0, rr, c1, c1, 2 /* Non-Secure Access Control Register */ 102272209Sandrew 103272209Sandrew/* 104272209Sandrew * CP15 C2 registers 105272209Sandrew */ 106272209Sandrew#define CP15_TTBR0(rr) p15, 0, rr, c2, c0, 0 /* Translation Table Base Register 0 */ 107272209Sandrew#define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */ 108272209Sandrew#define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */ 109272209Sandrew 110272209Sandrew/* 111272209Sandrew * CP15 C3 registers 112272209Sandrew */ 113272209Sandrew#define CP15_DACR(rr) p15, 0, rr, c3, c0, 0 /* Domain Access Control Register */ 114272209Sandrew 115272209Sandrew/* 116272209Sandrew * CP15 C5 registers 117272209Sandrew */ 118272209Sandrew#define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */ 119272209Sandrew 120272209Sandrew#if __ARM_ARCH >= 6 121272209Sandrew/* From ARMv6: */ 122272209Sandrew#define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */ 123276213Sian#endif 124276213Sian#if __ARM_ARCH >= 7 125272209Sandrew/* From ARMv7: */ 126272209Sandrew#define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */ 127272209Sandrew#define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */ 128272209Sandrew#endif 129272209Sandrew 130272209Sandrew/* 131272209Sandrew * CP15 C6 registers 132272209Sandrew */ 133272209Sandrew#define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */ 134272209Sandrew 135272209Sandrew#if __ARM_ARCH >= 6 136272209Sandrew/* From ARMv6k: */ 137272209Sandrew#define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */ 138272209Sandrew#endif 139272209Sandrew 140272209Sandrew/* 141272209Sandrew * CP15 C7 registers 142272209Sandrew */ 143276213Sian#if __ARM_ARCH >= 7 && defined(SMP) 144272209Sandrew/* From ARMv7: */ 145272209Sandrew#define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ 146272209Sandrew#define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ 147272209Sandrew#endif 148272209Sandrew 149290656Sskra#define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */ 150272209Sandrew 151272209Sandrew#define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ 152272209Sandrew#define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */ 153276213Sian#if __ARM_ARCH == 6 154272209Sandrew/* Deprecated in ARMv7 */ 155272209Sandrew#define CP15_CP15ISB p15, 0, r0, c7, c5, 4 /* ISB */ 156272209Sandrew#endif 157272209Sandrew#define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */ 158272209Sandrew#define CP15_BPIMVA p15, 0, rr, c7, c5, 7 /* Branch predictor invalidate by MVA */ 159272209Sandrew 160276213Sian#if __ARM_ARCH == 6 161272209Sandrew/* Only ARMv6: */ 162272209Sandrew#define CP15_DCIALL p15, 0, r0, c7, c6, 0 /* Data cache invalidate all */ 163272209Sandrew#endif 164272209Sandrew#define CP15_DCIMVAC(rr) p15, 0, rr, c7, c6, 1 /* Data cache invalidate by MVA PoC */ 165272209Sandrew#define CP15_DCISW(rr) p15, 0, rr, c7, c6, 2 /* Data cache invalidate by set/way */ 166272209Sandrew 167272209Sandrew#define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */ 168272209Sandrew#define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */ 169272209Sandrew#define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */ 170272209Sandrew#define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */ 171272209Sandrew 172276213Sian#if __ARM_ARCH >= 7 173272209Sandrew/* From ARMv7: */ 174272209Sandrew#define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */ 175272209Sandrew#define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */ 176272209Sandrew#define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged read */ 177272209Sandrew#define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */ 178272209Sandrew#endif 179272209Sandrew 180276213Sian#if __ARM_ARCH == 6 181272209Sandrew/* Only ARMv6: */ 182272209Sandrew#define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */ 183272209Sandrew#endif 184272209Sandrew#define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ 185272209Sandrew#define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ 186276213Sian#if __ARM_ARCH == 6 187272209Sandrew/* Only ARMv6: */ 188272209Sandrew#define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */ 189272209Sandrew#define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */ 190276519Sian#define CP15_CP15WFI p15, 0, r0, c7, c0, 4 /* WFI */ 191272209Sandrew#endif 192272209Sandrew 193276213Sian#if __ARM_ARCH >= 7 194272209Sandrew/* From ARMv7: */ 195272209Sandrew#define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ 196272209Sandrew#endif 197272209Sandrew 198276213Sian#if __ARM_ARCH == 6 199272209Sandrew/* Only ARMv6: */ 200272209Sandrew#define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */ 201272209Sandrew#endif 202272209Sandrew#define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */ 203272209Sandrew#define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */ 204272209Sandrew 205272209Sandrew/* 206272209Sandrew * CP15 C8 registers 207272209Sandrew */ 208276213Sian#if __ARM_ARCH >= 7 && defined(SMP) 209272209Sandrew/* From ARMv7: */ 210272209Sandrew#define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ 211272209Sandrew#define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ 212272209Sandrew#define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */ 213272209Sandrew#define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */ 214272209Sandrew#endif 215272209Sandrew 216272209Sandrew#define CP15_TLBIALL p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */ 217272209Sandrew#define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */ 218272209Sandrew#define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ 219272209Sandrew 220272209Sandrew#if __ARM_ARCH >= 6 221272209Sandrew/* From ARMv6: */ 222272209Sandrew#define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ 223272209Sandrew#endif 224272209Sandrew 225272209Sandrew/* 226276803Sian * CP15 C9 registers 227276803Sian */ 228276803Sian#if __ARM_ARCH == 6 && defined(CPU_ARM1176) 229283365Sandrew#define CP15_PMUSERENR(rr) p15, 0, rr, c15, c9, 0 /* Access Validation Control Register */ 230283365Sandrew#define CP15_PMCR(rr) p15, 0, rr, c15, c12, 0 /* Performance Monitor Control Register */ 231276803Sian#define CP15_PMCCNTR(rr) p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */ 232276803Sian#elif __ARM_ARCH > 6 233282547Szbb#define CP15_L2CTLR(rr) p15, 1, rr, c9, c0, 2 /* L2 Control Register */ 234276803Sian#define CP15_PMCR(rr) p15, 0, rr, c9, c12, 0 /* Performance Monitor Control Register */ 235276803Sian#define CP15_PMCNTENSET(rr) p15, 0, rr, c9, c12, 1 /* PM Count Enable Set Register */ 236276803Sian#define CP15_PMCNTENCLR(rr) p15, 0, rr, c9, c12, 2 /* PM Count Enable Clear Register */ 237276803Sian#define CP15_PMOVSR(rr) p15, 0, rr, c9, c12, 3 /* PM Overflow Flag Status Register */ 238276803Sian#define CP15_PMSWINC(rr) p15, 0, rr, c9, c12, 4 /* PM Software Increment Register */ 239276803Sian#define CP15_PMSELR(rr) p15, 0, rr, c9, c12, 5 /* PM Event Counter Selection Register */ 240276803Sian#define CP15_PMCCNTR(rr) p15, 0, rr, c9, c13, 0 /* PM Cycle Count Register */ 241276803Sian#define CP15_PMXEVTYPER(rr) p15, 0, rr, c9, c13, 1 /* PM Event Type Select Register */ 242276803Sian#define CP15_PMXEVCNTRR(rr) p15, 0, rr, c9, c13, 2 /* PM Event Count Register */ 243276803Sian#define CP15_PMUSERENR(rr) p15, 0, rr, c9, c14, 0 /* PM User Enable Register */ 244276803Sian#define CP15_PMINTENSET(rr) p15, 0, rr, c9, c14, 1 /* PM Interrupt Enable Set Register */ 245276803Sian#define CP15_PMINTENCLR(rr) p15, 0, rr, c9, c14, 2 /* PM Interrupt Enable Clear Register */ 246276803Sian#endif 247276803Sian 248276803Sian/* 249272209Sandrew * CP15 C10 registers 250272209Sandrew */ 251272209Sandrew/* Without LPAE this is PRRR, with LPAE it's MAIR0 */ 252272209Sandrew#define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */ 253272209Sandrew#define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */ 254272209Sandrew/* Without LPAE this is NMRR, with LPAE it's MAIR1 */ 255272209Sandrew#define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */ 256272209Sandrew#define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */ 257272209Sandrew 258272209Sandrew#define CP15_AMAIR0(rr) p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */ 259272209Sandrew#define CP15_AMAIR1(rr) p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */ 260272209Sandrew 261272209Sandrew/* 262272209Sandrew * CP15 C12 registers 263272209Sandrew */ 264272209Sandrew#define CP15_VBAR(rr) p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */ 265272209Sandrew#define CP15_MVBAR(rr) p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */ 266272209Sandrew 267272209Sandrew#define CP15_ISR(rr) p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */ 268272209Sandrew 269272209Sandrew/* 270272209Sandrew * CP15 C13 registers 271272209Sandrew */ 272272209Sandrew#define CP15_FCSEIDR(rr) p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */ 273272209Sandrew#define CP15_CONTEXTIDR(rr) p15, 0, rr, c13, c0, 1 /* Context ID Register */ 274272209Sandrew#define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */ 275272209Sandrew#define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ 276272209Sandrew#define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ 277272209Sandrew 278276213Sian/* 279280985Sandrew * CP15 C14 registers 280280985Sandrew * These are the Generic Timer registers and may be unallocated on some SoCs. 281280985Sandrew * Only use these when you know the Generic Timer is available. 282280985Sandrew */ 283280985Sandrew#define CP15_CNTFRQ(rr) p15, 0, rr, c14, c0, 0 /* Counter Frequency Register */ 284280985Sandrew#define CP15_CNTKCTL(rr) p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */ 285280985Sandrew#define CP15_CNTP_TVAL(rr) p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */ 286280985Sandrew#define CP15_CNTP_CTL(rr) p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */ 287280985Sandrew#define CP15_CNTV_TVAL(rr) p15, 0, rr, c14, c3, 0 /* Virtual Timer Value Register */ 288280985Sandrew#define CP15_CNTV_CTL(rr) p15, 0, rr, c14, c3, 1 /* Virtual Timer Control Register */ 289280985Sandrew#define CP15_CNTHCTL(rr) p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */ 290280985Sandrew#define CP15_CNTHP_TVAL(rr) p15, 4, rr, c14, c2, 0 /* PL2 Physical Timer Value Register */ 291280985Sandrew#define CP15_CNTHP_CTL(rr) p15, 4, rr, c14, c2, 1 /* PL2 Physical Timer Control Register */ 292280985Sandrew/* 64-bit registers for use with mcrr/mrrc */ 293280985Sandrew#define CP15_CNTPCT(rq, rr) p15, 0, rq, rr, c14 /* Physical Count Register */ 294280985Sandrew#define CP15_CNTVCT(rq, rr) p15, 1, rq, rr, c14 /* Virtual Count Register */ 295280985Sandrew#define CP15_CNTP_CVAL(rq, rr) p15, 2, rq, rr, c14 /* PL1 Physical Timer Compare Value Register */ 296280985Sandrew#define CP15_CNTV_CVAL(rq, rr) p15, 3, rq, rr, c14 /* Virtual Timer Compare Value Register */ 297280985Sandrew#define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */ 298280985Sandrew#define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */ 299280985Sandrew 300280985Sandrew/* 301276213Sian * CP15 C15 registers 302276213Sian */ 303276213Sian#define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */ 304276213Sian 305272209Sandrew#endif /* !MACHINE_SYSREG_H */ 306