Searched refs:c7 (Results 1 - 19 of 19) sorted by relevance

/freebsd-11-stable/sys/arm/arm/
H A Dcpufunc_asm_arm11.S46 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
64 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
66 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
79 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
80 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
86 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
92 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
100 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
H A Dcpufunc_asm_armv4.S47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
65 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
71 mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */
H A Dcpufunc_asm_armv6.S52 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
56 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
69 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
78 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
103 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
106 mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */
107 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
113 mcr p15, 0, r0, c7, c7,
[all...]
H A Dcpufunc_asm_arm11x6.S69 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
83 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
104 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
105 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
109 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
113 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
119 mcr p15, 0, r1, c8, c7,
[all...]
H A Dcpufunc_asm_xscale_c3.S137 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
149 mcr p15, 0, r3, c7, c14, 2 /* clean and invalidate */
158 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
175 1: mcr p15, 0, r0, c7, c14, 1 /* clean/invalidate L1 D cache entry */
177 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
184 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
197 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
198 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
205 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
218 1: mcr p15, 0, r0, c7, c1
[all...]
H A Dcpufunc_asm_fa526.S43 mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */
44 mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */
45 mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */
46 mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */
51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
63 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */
71 mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/
80 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
81 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
82 mcr p15, 0, r0, c7, c1
[all...]
H A Dcpufunc_asm_armv5_ec.S60 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
61 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
63 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
87 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
88 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
101 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
106 mrc p15, 0, APSR_nzcv, c7, c10, 3 /* Test and clean (don't invalidate) */
108 mcr p15, 0, r0, c7, c1
[all...]
H A Dcpufunc_asm_xscale.S119 mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
140 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
141 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
151 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
154 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
178 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
183 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
188 mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
193 mcr p15, 0, r0, c7, c
[all...]
H A Dcpufunc_asm_arm9.S50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
82 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
83 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
95 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
104 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
125 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
142 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
163 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
180 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
181 mcr p15, 0, r0, c7, c1
[all...]
H A Dcpufunc_asm.S170 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
174 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */
175 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
178 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
H A Dcpufunc_asm_sheeva.S50 mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */
51 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
60 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
64 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
106 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
145 mcr p15, 0, r0, c7, c5, 1
158 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
201 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
244 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
289 mcr p15, 0, r0, c7, c1
[all...]
H A Dlocore-v4.S217 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
411 mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
/freebsd-11-stable/sys/arm/include/
H A Dsysreg.h50 #define CP14_DBGVCR(rr) p14, 0, rr, c0, c7, 0 /* Vector Catch Register */
145 #define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */
146 #define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */
149 #define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */
151 #define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */
152 #define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */
155 #define CP15_CP15ISB p15, 0, r0, c7, c5, 4 /* ISB */
157 #define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */
158 #define CP15_BPIMVA p15, 0, rr, c7, c5, 7 /* Branch predictor invalidate by MVA */
162 #define CP15_DCIALL p15, 0, r0, c7, c
[all...]
/freebsd-11-stable/sys/arm/mv/armadaxp/
H A Dmptramp.S36 mcr p15, 0, r0, c7, c7, 0
/freebsd-11-stable/contrib/libucl/src/
H A Ducl_hash.c130 unsigned char c1, c2, c3, c4, c5, c6, c7, c8; member in struct:__anon2135::__anon2136
141 u.c.c5 = s[i + 4], u.c.c6 = s[i + 5], u.c.c7 = s[i + 6], u.c.c8 = s[i + 7];
148 u.c.c3 = lc_map[u.c.c7];
156 u.c.c7 = lc_map[(unsigned char)s[i++]];
/freebsd-11-stable/crypto/openssl/crypto/whrlpool/
H A Dwp_block.c156 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7
167 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7, \
168 c7,c0,c1,c2,c3,c4,c5,c6, \
169 c6,c7,c0,c1,c2,c3,c4,c5, \
170 c5,c6,c7,c0,c1,c2,c3,c4, \
171 c4,c5,c6,c7,c0,c1,c2,c3, \
172 c3,c4,c5,c6,c7,c0,c1,c2, \
173 c2,c3,c4,c5,c6,c7,c
[all...]
/freebsd-11-stable/share/mk/
H A Dbsd.cpu.mk101 . elif ${CPUTYPE} == "c7"
239 . elif ${CPUTYPE} == "c7"
/freebsd-11-stable/contrib/amd/doc/
H A Dtexinfo.tex8955 \gdef^^c7{\cedilla C}
9075 \gdef^^c7{\cedilla C}
/freebsd-11-stable/contrib/netbsd-tests/usr.bin/netpgpverify/
H A Dt_netpgpverify.sh4388 CK9p9ks0zep5AjGnE3fzysrvi6I10QS+c7/qRo1vlFpZLuqpFXWxHs3brbtKimNv

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