Searched refs:VirtReg (Results 1 - 25 of 28) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument
105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to "
107 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) {
113 Matrix[Unit].unify(VirtReg, Range);
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { argument
122 Register PhysReg = VRM->getPhys(VirtReg.reg);
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg
146 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
164 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
186 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument
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H A DRegAllocBase.cpp89 while (LiveInterval *VirtReg = dequeue()) {
90 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
93 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
94 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
95 aboutToRemoveInterval(*VirtReg);
96 LIS->removeInterval(VirtReg->reg);
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
108 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
113 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVReg
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H A DRegAllocBasic.cpp103 unsigned selectOrSplit(LiveInterval &VirtReg,
117 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
144 bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) { argument
145 LiveInterval &LI = LIS->getInterval(VirtReg);
146 if (VRM->hasPhys(VirtReg)) {
154 // dump will show the right state for that VirtReg.
159 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { argument
160 if (!VRM->hasPhys(VirtReg))
164 LiveInterval &LI = LIS->getInterval(VirtReg);
202 // that interfere with VirtReg
204 spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<unsigned> &SplitVRegs) argument
256 selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl<unsigned> &SplitVRegs) argument
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H A DAllocationOrder.cpp29 AllocationOrder::AllocationOrder(unsigned VirtReg, argument
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37 if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
H A DRegAllocFast.cpp86 Register VirtReg; ///< Virtual register number. member in struct:__anon1790::RegAllocFast::LiveReg
91 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} argument
94 return Register::virtReg2Index(VirtReg);
193 void killVirtReg(Register VirtReg);
195 void spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg);
203 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { argument
204 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
207 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) cons
248 getStackSpaceFor(Register VirtReg) argument
267 mayLiveOut(Register VirtReg) argument
296 mayLiveIn(Register VirtReg) argument
315 spill(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg AssignedReg, bool Kill) argument
343 reload(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg PhysReg) argument
397 killVirtReg(Register VirtReg) argument
407 spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg) argument
612 Register VirtReg = LR.VirtReg; local
663 const Register VirtReg = LR.VirtReg; local
754 Register VirtReg = MO.getReg(); local
778 defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg, Register Hint) argument
809 reloadVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg, Register Hint) argument
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H A DRegAllocGreedy.cpp255 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
256 return ExtraRegInfo[VirtReg.reg].Stage;
259 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { argument
261 ExtraRegInfo[VirtReg.reg].Stage = Stage;
465 unsigned canReassign(LiveInterval &VirtReg, unsigned PrevReg);
469 bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
473 LiveInterval &VirtReg, SlotIndex Start,
477 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
489 unsigned isSplitBenefitWorthCost(LiveInterval &VirtReg);
491 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
636 LRE_CanEraseVirtReg(unsigned VirtReg) argument
651 LRE_WillShrinkVirtReg(unsigned VirtReg) argument
762 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, const SmallVirtRegSet &FixedRegisters) argument
809 canReassign(LiveInterval &VirtReg, unsigned PrevReg) argument
872 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost, const SmallVirtRegSet &FixedRegisters) argument
969 canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg, SlotIndex Start, SlotIndex End, EvictionCost &MaxCost) argument
1022 getCheapestEvicteeWeight(const AllocationOrder &Order, LiveInterval &VirtReg, SlotIndex Start, SlotIndex End, float *BestEvictweight) argument
1048 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<unsigned> &NewVRegs) argument
1106 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, unsigned CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) argument
1821 isSplitBenefitWorthCost(LiveInterval &VirtReg) argument
1829 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
1872 calculateRegionSplitCost(LiveInterval &VirtReg, AllocationOrder &Order, BlockFrequency &BestCost, unsigned &NumCands, bool IgnoreCSR, bool *CanCauseEvictionChain) argument
1972 doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, bool HasCompact, SmallVectorImpl<unsigned> &NewVRegs) argument
2019 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
2086 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
2229 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
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H A DLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { argument
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { argument
67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
105 return is_contained(InterferingVRegs, VirtReg);
H A DRegisterCoalescer.h62 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument
64 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {}
H A DAllocationOrder.h39 /// Create a new AllocationOrder for VirtReg.
40 /// @param VirtReg Virtual register to allocate for.
43 AllocationOrder(unsigned VirtReg,
H A DVirtRegMap.cpp101 bool VirtRegMap::hasPreferredPhys(Register VirtReg) { argument
102 Register Hint = MRI->getSimpleHint(VirtReg);
107 return getPhys(VirtReg) == Hint;
110 bool VirtRegMap::hasKnownPreference(Register VirtReg) { argument
111 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
314 Register VirtReg = Register::index2VirtReg(Idx); local
315 if (MRI->reg_nodbg_empty(VirtReg))
317 LiveInterval &LI = LIS->getInterval(VirtReg);
322 Register PhysReg = VRM->getPhys(VirtReg);
517 Register VirtReg local
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H A DRegAllocBase.h94 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
104 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
H A DLiveDebugVariables.cpp426 /// Find the EC leader for VirtReg or null.
427 UserValue *lookupVirtReg(unsigned VirtReg);
477 void mapVirtReg(unsigned VirtReg, UserValue *EC);
603 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { argument
604 assert(Register::isVirtualRegister(VirtReg) && "Only map VirtRegs");
605 UserValue *&Leader = virtRegToEqClass[VirtReg];
609 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { argument
610 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
1193 Register VirtReg = Loc.getReg(); local
1194 if (VRM.isAssignedReg(VirtReg)
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H A DInlineSpiller.cpp543 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { argument
546 VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, VirtReg.reg, &Ops);
552 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
558 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
574 markValueUsed(&VirtReg, ParentVNI);
579 // If the instruction also writes VirtReg.reg, it had better not require the
582 markValueUsed(&VirtReg, ParentVNI);
598 if (!canGuaranteeAssignmentAfterRemat(VirtReg.reg, MI)) {
599 markValueUsed(&VirtReg, ParentVNI);
623 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg
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H A DMachineBasicBlock.cpp509 Register VirtReg = I->getOperand(0).getReg();
510 if (!MRI.constrainRegClass(VirtReg, RC))
512 return VirtReg;
516 Register VirtReg = MRI.createVirtualRegister(RC);
517 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
521 return VirtReg;
H A DTargetRegisterInfo.cpp383 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
391 MRI.getRegAllocationHints(VirtReg);
411 // Check that Phys is a valid hint in VirtReg's register class.
417 // from VirtReg's register class if they aren't in the allocation order. The
H A DPHIElimination.cpp219 /// Return true if all defs of VirtReg are implicit-defs.
221 static bool isImplicitlyDefined(unsigned VirtReg, argument
223 for (MachineInstr &DI : MRI.def_instructions(VirtReg))
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h99 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
103 /// Check for interference before assigning VirtReg to PhysReg.
104 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
107 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
116 /// Assign VirtReg to PhysReg.
117 /// This will mark VirtReg's live range as occupied in the LiveRegMatrix and
119 void assign(LiveInterval &VirtReg, unsigned PhysReg);
121 /// Unassign VirtReg from its PhysReg.
122 /// Assuming that VirtReg was previously assigned to a PhysReg, this undoes
124 void unassign(LiveInterval &VirtReg);
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H A DVirtRegMap.h126 /// returns true if VirtReg is assigned to its preferred physreg.
127 bool hasPreferredPhys(Register VirtReg);
129 /// returns true if VirtReg has a known preferred register.
130 /// This returns false if VirtReg has a preference that is a virtual
132 bool hasKnownPreference(Register VirtReg);
144 /// getOriginal - Return the original virtual register that VirtReg descends
148 unsigned getOriginal(unsigned VirtReg) const {
149 unsigned Orig = getPreSplitReg(VirtReg);
150 return Orig ? Orig : VirtReg;
H A DLiveIntervalUnion.h91 void unify(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg, const LiveRange &Range);
157 bool isSeenInterference(LiveInterval *VirtReg) const;
H A DScheduleDAGInstrs.h53 unsigned VirtReg; member in struct:llvm::VReg2SUnit
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
61 return Register::virtReg2Index(VirtReg);
H A DRegisterPressure.h535 bool hasUntiedDef(unsigned VirtReg) const {
536 return UntiedDefs.count(VirtReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp128 const Register VirtReg = MO.getReg(); local
129 if (Register::isPhysicalRegister(VirtReg))
132 if (!VRM->hasPhys(VirtReg))
135 Register PhysReg = VRM->getPhys(VirtReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp77 SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument
88 VirtReg, Order, Hints, MF, VRM, Matrix);
93 for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
98 if (VirtReg == Use.getOperand(0).getReg()) {
103 } else if (VirtReg == Use.getOperand(1).getReg()) {
106 } else if (VirtReg == Use.getOperand(2).getReg() &&
122 MRI->getRegClass(VirtReg));
136 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
139 Worklist.push_back(VirtReg);
148 // VirtReg
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H A DSystemZRegisterInfo.h61 bool getRegAllocationHints(unsigned VirtReg,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h152 bool getRegAllocationHints(unsigned VirtReg,

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