lib/CodeGen/RegAllocFast.cpp

86       Register VirtReg;                ///< Virtual register number.
91       explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {}
94         return Register::virtReg2Index(VirtReg);
193     void killVirtReg(Register VirtReg);
195     void spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg);
203     LiveRegMap::iterator findLiveVirtReg(Register VirtReg) {
204       return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
207     LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const {
208       return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
213     MCPhysReg defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
215     LiveReg &reloadVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
220     Register traceCopies(Register VirtReg) const;
223     int getStackSpaceFor(Register VirtReg);
224     void spill(MachineBasicBlock::iterator Before, Register VirtReg,
226     void reload(MachineBasicBlock::iterator Before, Register VirtReg,
229     bool mayLiveOut(Register VirtReg);
230     bool mayLiveIn(Register VirtReg);
248 int RegAllocFast::getStackSpaceFor(Register VirtReg) {
250   int SS = StackSlotForVirtReg[VirtReg];
256   const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
262   StackSlotForVirtReg[VirtReg] = FrameIdx;
266 /// Returns false if \p VirtReg is known to not live out of the current block.
267 bool RegAllocFast::mayLiveOut(Register VirtReg) {
268   if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) {
276     MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
284   for (const MachineInstr &UseInst : MRI->reg_nodbg_instructions(VirtReg)) {
286       MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
295 /// Returns false if \p VirtReg is known to not be live into the current block.
296 bool RegAllocFast::mayLiveIn(Register VirtReg) {
297   if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg)))
303   for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
305       MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
314 /// DBG_VALUEs with \p VirtReg operands with the stack slot.
315 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg,
317   LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI)
319   int FI = getStackSpaceFor(VirtReg);
322   const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
329   SmallVectorImpl<MachineInstr *> &LRIDbgValues = LiveDbgValueMap[VirtReg];
343 void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg,
345   LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into "
347   int FI = getStackSpaceFor(VirtReg);
348   const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
390   assert(PhysRegState[LR.PhysReg] == LR.VirtReg &&
397 void RegAllocFast::killVirtReg(Register VirtReg) {
398   assert(Register::isVirtualRegister(VirtReg) &&
400   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
405 /// This method spills the value specified by VirtReg into the corresponding
408                                 Register VirtReg) {
409   assert(Register::isVirtualRegister(VirtReg) &&
411   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
419   assert(PhysRegState[LR.PhysReg] == LR.VirtReg && "Broken RegState mapping");
427     spill(MI, LR.VirtReg, LR.PhysReg, SpillKill);
444     if (OnlyLiveOut && !mayLiveOut(LR.VirtReg))
524   switch (Register VirtReg = PhysRegState[PhysReg]) {
528     spillVirtReg(MI, VirtReg);
540     switch (Register VirtReg = PhysRegState[Alias]) {
544       spillVirtReg(MI, VirtReg);
566   switch (Register VirtReg = PhysRegState[PhysReg]) {
572     LLVM_DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding "
576     LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
578            "Missing VirtReg entry");
588     switch (Register VirtReg = PhysRegState[Alias]) {
597       LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
599              "Missing VirtReg entry");
609 /// proper container for VirtReg now.  The physical register must not be used
612   Register VirtReg = LR.VirtReg;
613   LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to "
618   setPhysRegState(PhysReg, VirtReg);
641 /// Check if any of \p VirtReg's definitions is a copy. If it is follow the
644 Register RegAllocFast::traceCopies(Register VirtReg) const {
647   for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) {
661 /// Allocates a physical register for VirtReg.
663   const Register VirtReg = LR.VirtReg;
665   assert(Register::isVirtualRegister(VirtReg) &&
668   const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
669   LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg)
694   Register Hint1 = traceCopies(VirtReg);
754   Register VirtReg = MO.getReg();
755   assert(Register::isVirtualRegister(VirtReg) && "Expected virtreg");
757   LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
762     const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
777 /// Allocates a register for VirtReg and mark it as dirty.
779                                       Register VirtReg, Register Hint) {
780   assert(Register::isVirtualRegister(VirtReg) && "Not a virtual register");
783   std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
787         MRI->hasOneNonDBGUse(VirtReg)) {
788       const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
796     // instruction defining VirtReg multiple times.
808 /// Make sure VirtReg is available in a physreg and return it.
811                                                    Register VirtReg,
813   assert(Register::isVirtualRegister(VirtReg) && "Not a virtual register");
816   std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
820     reload(MI, VirtReg, LRI->PhysReg);
992              "Missing VirtReg entry");
1006     assert(i->VirtReg.isVirtual() && "Bad map key");
1008     assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");
1200   for (Register VirtReg : VirtDead)
1201     killVirtReg(VirtReg);