1218885Sdim//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// 2218885Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6218885Sdim// 7218885Sdim//===----------------------------------------------------------------------===// 8218885Sdim// 9218885Sdim// This file implements an allocation order for virtual registers. 10218885Sdim// 11218885Sdim// The preferred allocation order for a virtual register depends on allocation 12218885Sdim// hints and target hooks. The AllocationOrder class encapsulates all of that. 13218885Sdim// 14218885Sdim//===----------------------------------------------------------------------===// 15218885Sdim 16218885Sdim#include "AllocationOrder.h" 17249423Sdim#include "llvm/CodeGen/MachineFunction.h" 18218885Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 19239462Sdim#include "llvm/CodeGen/RegisterClassInfo.h" 20249423Sdim#include "llvm/CodeGen/VirtRegMap.h" 21249423Sdim#include "llvm/Support/Debug.h" 22249423Sdim#include "llvm/Support/raw_ostream.h" 23218885Sdim 24218885Sdimusing namespace llvm; 25218885Sdim 26276479Sdim#define DEBUG_TYPE "regalloc" 27276479Sdim 28218885Sdim// Compare VirtRegMap::getRegAllocPref(). 29218885SdimAllocationOrder::AllocationOrder(unsigned VirtReg, 30218885Sdim const VirtRegMap &VRM, 31296417Sdim const RegisterClassInfo &RegClassInfo, 32296417Sdim const LiveRegMatrix *Matrix) 33327952Sdim : Pos(0), HardHints(false) { 34249423Sdim const MachineFunction &MF = VRM.getMachineFunction(); 35249423Sdim const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); 36249423Sdim Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 37327952Sdim if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix)) 38327952Sdim HardHints = true; 39249423Sdim rewind(); 40218885Sdim 41341825Sdim LLVM_DEBUG({ 42249423Sdim if (!Hints.empty()) { 43249423Sdim dbgs() << "hints:"; 44249423Sdim for (unsigned I = 0, E = Hints.size(); I != E; ++I) 45327952Sdim dbgs() << ' ' << printReg(Hints[I], TRI); 46249423Sdim dbgs() << '\n'; 47249423Sdim } 48249423Sdim }); 49249423Sdim#ifndef NDEBUG 50249423Sdim for (unsigned I = 0, E = Hints.size(); I != E; ++I) 51314564Sdim assert(is_contained(Order, Hints[I]) && 52249423Sdim "Target hint is outside allocation order."); 53249423Sdim#endif 54218885Sdim} 55