Searched refs:UseIdx (Results 1 - 21 of 21) sorted by relevance

/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/
H A DMCSubtargetInfo.h110 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, argument
117 if (I->UseIdx < UseIdx)
119 if (I->UseIdx > UseIdx)
H A DMCInstrItineraries.h202 /// itinerary class UseClass, operand index UseIdx.
204 unsigned UseClass, unsigned UseIdx) const {
214 if ((FirstUseIdx + UseIdx) >= LastUseIdx)
218 Forwardings[FirstUseIdx + UseIdx];
225 unsigned UseClass, unsigned UseIdx) const {
233 int UseCycle = getOperandCycle(UseClass, UseIdx);
239 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
H A DMCSchedule.h74 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
77 unsigned UseIdx; member in struct:llvm::MCReadAdvanceEntry
82 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DLiveRangeEdit.cpp77 /// OrigIdx are also available with the same value at UseIdx.
80 SlotIndex UseIdx) {
82 UseIdx = UseIdx.getRegSlot(true);
103 if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
106 if (OVNI != li.getVNInfoAt(UseIdx))
113 SlotIndex UseIdx,
136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
78 allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, SlotIndex UseIdx) argument
112 canRematerializeAt(Remat &RM, SlotIndex UseIdx, bool cheapAsAMove) argument
H A DTargetSchedule.cpp127 unsigned UseIdx = 0; local
131 ++UseIdx;
133 return UseIdx;
189 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); local
190 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
H A DTargetInstrInfoImpl.cpp518 SDNode *UseNode, unsigned UseIdx) const {
529 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
603 const MachineInstr *UseMI, unsigned UseIdx) const {
606 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
650 /// UseIdx to compute min latency.
654 const MachineInstr *UseMI, unsigned UseIdx,
665 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
652 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx, bool FindMin) const argument
H A DInlineSpiller.cpp835 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); local
836 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
845 DEBUG(dbgs() << UseIdx << '\t' << *MI);
857 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
859 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
870 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
901 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
904 NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI));
H A DSplitKit.h313 /// defFromParent - Define Reg from ParentVNI at UseIdx using either
317 SlotIndex UseIdx,
H A DMachineVerifier.cpp979 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); local
984 LiveRangeQuery LRQ(*LI, UseIdx);
987 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1002 LiveRangeQuery LRQ(LI, UseIdx);
1005 *OS << UseIdx << " is not live in " << LI << '\n';
H A DRegisterCoalescer.cpp611 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); local
612 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
663 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); local
664 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
683 SlotIndex DefIdx = UseIdx.getRegSlot();
H A DMachineInstr.cpp1160 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1172 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1174 MachineOperand &UseMO = getOperand(UseIdx);
1176 assert(UseMO.isUse() && "UseIdx must be a use operand");
1190 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1191 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
H A DSplitKit.cpp430 SlotIndex UseIdx,
443 if (Edit->canRematerializeAt(RM, UseIdx, true)) {
428 defFromParent(unsigned RegIdx, VNInfo *ParentVNI, SlotIndex UseIdx, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DARMBaseInstrInfo.h226 const MachineInstr *UseMI, unsigned UseIdx) const;
230 SDNode *UseNode, unsigned UseIdx) const;
258 unsigned UseIdx, unsigned UseAlign) const;
262 unsigned UseIdx, unsigned UseAlign) const;
267 unsigned UseIdx, unsigned UseAlign) const;
279 const MachineInstr *UseMI, unsigned UseIdx) const;
H A DARMBaseInstrInfo.cpp2836 unsigned UseIdx, unsigned UseAlign) const {
2837 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2839 return ItinData->getOperandCycle(UseClass, UseIdx);
2876 unsigned UseIdx, unsigned UseAlign) const {
2877 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2879 return ItinData->getOperandCycle(UseClass, UseIdx);
2906 unsigned UseIdx, unsigned UseAlign) const {
2910 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2911 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2961 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2833 getVSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument
2873 getSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument
2902 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument
3037 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/
H A DLiveRangeEdit.h84 /// OrigIdx are also available with the same value at UseIdx.
86 SlotIndex UseIdx);
160 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
163 SlotIndex UseIdx,
H A DMachineInstr.h798 /// UseIdx. The tie will cause the register allocator to ensure that the two
803 void tieOperands(unsigned DefIdx, unsigned UseIdx);
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Target/
H A DTargetInstrInfo.h780 SDNode *UseNode, unsigned UseIdx) const = 0;
793 unsigned UseIdx) const = 0;
801 const MachineInstr *UseMI, unsigned UseIdx,
834 const MachineInstr *UseMI, unsigned UseIdx) const {
1002 SDNode *UseNode, unsigned UseIdx) const;
1021 unsigned UseIdx) const;
/macosx-10.9.5/llvmCore-3425.0.33/utils/TableGen/
H A DSubtargetEmitter.cpp902 // Entries must be sorted first by UseIdx then by WriteResourceID.
903 for (unsigned UseIdx = 0, EndIdx = Reads.size();
904 UseIdx != EndIdx; ++UseIdx) {
906 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
928 RAEntry.UseIdx = UseIdx;
1033 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1040 OS << " {" << RAEntry.UseIdx << ", "
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86InstrInfo.h376 const MachineInstr *UseMI, unsigned UseIdx) const;
H A DX86InstrInfo.cpp4666 const MachineInstr *UseMI, unsigned UseIdx) const {
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp958 unsigned UseIdx = GroupIdx.back() + 1;
960 MI->tieOperands(DefIdx + j, UseIdx + j);

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