/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 366 SDValue Tmp1 = Vec; local 376 EVT VT = Tmp1.getValueType(); 384 DAG.getEntryNode(), dl, Tmp1, StackPtr, 1591 SDValue Tmp1 = SDValue(Node, 0); 1594 SDValue Chain = Tmp1.getOperand(0); 1606 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1608 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, 1610 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1615 Results.push_back(Tmp1); [all...] |
H A D | LegalizeFloatTypes.cpp | 1708 SDValue Tmp1, Tmp2, Tmp3; local 1709 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), 1713 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); 1714 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), 1718 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); 1719 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp [all...] |
H A D | SelectionDAG.cpp | 1939 SDValue Tmp1 = Node->getOperand(0); 1943 SDValue VAListLoad = getLoad(TLI.getPointerTy(getDataLayout()), dl, Tmp1, 1957 Tmp1 = getNode(ISD::ADD, dl, VAList.getValueType(), VAList, 1962 Tmp1 = 1963 getStore(VAListLoad.getValue(1), dl, Tmp1, Tmp2, MachinePointerInfo(V)); 1965 return getLoad(VT, dl, Tmp1, VAList, MachinePointerInfo()); 1975 SDValue Tmp1 = 1978 return getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
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H A D | SelectionDAGBuilder.cpp | 7590 SDValue Tmp1 = getValue(I.getArgOperand(1)); local 7592 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | IntegerDivision.cpp | 131 Value *Tmp1 = Builder.CreateAShr(Divisor, Shift); local 134 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); 135 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); 136 Value *Q_Sgn = Builder.CreateXor(Tmp1, Tmp); 255 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); local 256 Value *SR = Builder.CreateSub(Tmp0, Tmp1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | IntrinsicLowering.cpp | 64 Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), local 68 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); 78 Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), local 87 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); 108 Value* Tmp1 = Builder.CreateLShr(V, local 138 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4");
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 3609 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local 3610 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { 3612 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; 3645 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local 3646 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { 3647 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, 3678 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local 3679 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { 3680 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, 4226 SDValue Tmp0, Tmp1, Tmp local 4668 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local 4721 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local 4803 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local 4908 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local 4916 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain; local 5161 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local [all...] |
H A D | X86ISelLowering.cpp | 18495 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 18519 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); 18522 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); [all...] |
/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
H A D | CheckerManager.cpp | 125 ExplodedNodeSet Tmp1, Tmp2; local 133 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 387 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; local 389 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); 403 BuildMI(BB, DL, TII.get(FConst), Tmp1) 405 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); 409 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); 413 BuildMI(BB, DL, TII.get(FConst), Tmp1) 415 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPromoteAlloca.cpp | 817 Value *Tmp1 = Builder.CreateMul(TIdY, TCntZ, "", true, true); local 818 Value *TID = Builder.CreateAdd(Tmp0, Tmp1);
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H A D | AMDGPUCodeGenPrepare.cpp | 845 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero 846 Value *Tmp1 = Builder.CreateAnd(Remainder_GE_Den, Remainder_GE_Zero); local 847 Value *Tmp1_0_CC = Builder.CreateICmpEQ(Tmp1, Zero); 857 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One) 869 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
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H A D | AMDGPUISelLowering.cpp | 1919 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero 1920 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, local 1933 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One) 1934 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT), 1949 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den) 1950 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT), 2122 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); local 2123 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); 2140 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); local 2141 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySig 2226 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT, local [all...] |
H A D | AMDGPULegalizerInfo.cpp | 1372 auto Tmp1 = B.buildFAdd(Ty, Src, CopySign); 1373 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign); 1469 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); 1470 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1);
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H A D | SIISelLowering.cpp | 9069 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0)); local 9073 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 1877 SmallVector<MachineOperand,2> Tmp1; local 1880 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) 1885 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false);
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H A D | HexagonSplitDouble.cpp | 693 auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4/*size*/, A); local 694 LowI->addMemOperand(MF, Tmp1); 936 // Tmp1 = extractu R2.lo, #s, #32-s 937 // Tmp2 = or R1.hi, Tmp1
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2000 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); local 2004 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2060 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); local 2064 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2415 SDValue Tmp1 = ST->getChain(); local 2421 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8,
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/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGExprComplex.cpp | 843 llvm::Value *Tmp1 = Builder.CreateMul(LHSr, RHSr); // a*c local 845 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Support/ |
H A D | APInt.cpp | 679 unsigned Tmp1 = unsigned(U.VAL >> 16); 680 Tmp1 = ByteSwap_32(Tmp1); 683 return APInt(BitWidth, (uint64_t(Tmp2) << 32) | Tmp1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 5504 SDValue Tmp1 = Op.getOperand(1); local 5507 EVT SrcVT = Tmp1.getValueType(); 5525 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); 5527 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, 5528 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), 5531 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64, 5532 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), 5535 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); 5863 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); local 5905 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 5269 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); local 5272 ReplaceNode(N, CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), 5283 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); local 5286 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
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H A D | PPCISelLowering.cpp | 8395 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, local 8398 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 8424 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, local 8427 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 8452 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, local 8455 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 2964 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); local 2965 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 7400 Register Tmp1 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass); local 7403 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Tmp1); 7405 .addReg(Tmp1).addReg(Hi).addImm(SystemZ::subreg_h64);
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