/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 1340 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1341 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1342 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1343 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1428 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1429 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1430 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1431 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1432 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1433 { ISD::TRUNCATE, MV [all...] |
H A D | X86ISelLowering.cpp | 806 setOperationAction(ISD::TRUNCATE, VT, Expand); 1023 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom); 1024 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom); 1025 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Custom); 1026 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom); 1027 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom); 1028 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom); 1240 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom); 1241 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom); 1242 setOperationAction(ISD::TRUNCATE, MV [all...] |
H A D | X86IntrinsicsInfo.h | 641 ISD::TRUNCATE, X86ISD::VMTRUNC), 645 ISD::TRUNCATE, X86ISD::VMTRUNC), 647 ISD::TRUNCATE, X86ISD::VMTRUNC), 661 ISD::TRUNCATE, X86ISD::VMTRUNC),
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H A D | X86ISelDAGToDAG.cpp | 2108 RHS.getNode()->getOpcode() == ISD::TRUNCATE || 2618 if (N.getOpcode() == ISD::TRUNCATE) { 2687 if (N->getOpcode() == ISD::TRUNCATE) 3279 if (V->getOpcode() == ISD::TRUNCATE && checkOneUse(V)) { 3338 if (ShiftAmt.getOpcode() == ISD::TRUNCATE) { 3418 NBits = CurDAG->getNode(ISD::TRUNCATE, DL, MVT::i8, NBits); 3505 Extract = CurDAG->getNode(ISD::TRUNCATE, DL, NVT, Extract); 3714 if (ShiftAmt->getOpcode() == ISD::TRUNCATE) 3754 NewShiftAmt = CurDAG->getNode(ISD::TRUNCATE, DL, MVT::i8, NewShiftAmt); 5065 if (N0.getOpcode() == ISD::TRUNCATE [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 223 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 224 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 239 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 240 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 392 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 }, 393 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 }, 394 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 }, 395 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
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H A D | ARMSelectionDAGInfo.cpp | 91 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 534 /// TRUNCATE - Completely drop the high bits. 535 TRUNCATE, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 1104 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0)); 1218 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1)); 1288 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1)); 1360 SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD); 1574 case ISD::TRUNCATE: return visitTRUNCATE(N); 2376 // First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization. 2378 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) { 4109 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 4165 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 4242 Hi = DAG.getNode(ISD::TRUNCATE, D [all...] |
H A D | TargetLowering.cpp | 570 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), 571 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1))); 1783 case ISD::TRUNCATE: { 1797 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc)); 1830 TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0)); 2602 case ISD::TRUNCATE: 3178 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 3262 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); 3455 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 3494 if (Op0.getOpcode() == ISD::TRUNCATE) [all...] |
H A D | LegalizeVectorTypes.cpp | 101 case ISD::TRUNCATE: 292 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); 322 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op); 409 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); 475 Cond = DAG.getNode(ISD::TRUNCATE, SDLoc(N), BoolVT, Cond); 570 case ISD::TRUNCATE: 894 case ISD::TRUNCATE: 1479 Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Lo); 1481 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi); 1930 case ISD::TRUNCATE [all...] |
H A D | LegalizeIntegerTypes.cpp | 91 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 1043 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1); 1044 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2); 1055 SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp); 1070 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); 1295 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 1680 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op); 1773 return DAG.getNode(ISD::TRUNCATE, dl, VT, Reduce); 1842 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 3517 Lo = DAG.getNode(ISD::TRUNCATE, d [all...] |
H A D | LegalizeTypes.cpp | 998 Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op); 1007 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi);
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H A D | LegalizeDAG.cpp | 644 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value); 650 Value = DAG.getNode(ISD::TRUNCATE, dl, 1555 SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit); 2593 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 3118 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 3121 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 4264 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 4276 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 4301 TruncOp = ISD::TRUNCATE; 4350 TruncOp = ISD::TRUNCATE; [all...] |
/freebsd-11-stable/contrib/binutils/ld/ |
H A D | ldlex.l | 330 <MRI>"TRUNCATE" { RTOKEN(TRUNCATE); } 347 <MRI>"truncate" { RTOKEN(TRUNCATE); }
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H A D | ldgram.y | 148 %token FORMAT PUBLIC DEFSYMEND BASE ALIAS TRUNCATE REL 245 | TRUNCATE INT
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 302 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 303 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 304 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 305 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
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/freebsd-11-stable/contrib/gcc/ |
H A D | regrename.c | 546 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE 553 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE 1471 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE 1478 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE
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H A D | simplify-rtx.c | 611 return simplify_gen_unary (TRUNCATE, mode, temp, inner); 621 return simplify_gen_unary (TRUNCATE, mode, temp, inner); 626 case TRUNCATE: 652 && GET_CODE (SUBREG_REG (op)) == TRUNCATE 654 return simplify_gen_unary (TRUNCATE, mode, XEXP (SUBREG_REG (op), 0), 658 replace the TRUNCATE with a SUBREG. Note that this is also 816 if (GET_CODE (op) == TRUNCATE 1056 case TRUNCATE: 1202 case TRUNCATE: 4590 if (GET_CODE (op) == TRUNCATE [all...] |
H A D | sched-vis.c | 295 case TRUNCATE:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 237 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); 714 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom); 715 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom); 716 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom); 717 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom); 718 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom); 1190 setTargetDAGCombine(ISD::TRUNCATE); 1195 setTargetDAGCombine(ISD::TRUNCATE); 3616 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue); 3756 return DAG.getNode(ISD::TRUNCATE, d [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 458 if (Opcode == ISD::TRUNCATE) { 642 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); 776 case ISD::TRUNCATE: { 966 RISBG.Input.getOpcode() != ISD::TRUNCATE) 1072 RxSBG[I].Input.getOpcode() != ISD::TRUNCATE)
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H A D | SystemZISelLowering.cpp | 1284 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); 2248 if (C.Op0.getOpcode() == ISD::TRUNCATE && 2624 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi); 2625 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul); 3307 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift); 3516 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1); 3588 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp); 3633 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); 3699 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); 3758 Op = DAG.getNode(ISD::TRUNCATE, D [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1874 Ret = DAG.getNode(ISD::TRUNCATE, dl, ProxyRegTruncates[i].getValue(), Ret); 2220 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select); 2259 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD); 2604 Elt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Elt); 4695 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS); 4697 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS); 4897 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); 5010 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); 5040 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 490 setTargetDAGCombine(ISD::TRUNCATE); 2437 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ); 2457 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl)); 2992 if (N0.getOpcode() == ISD::TRUNCATE) { 3001 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg); 3104 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); 3216 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); 3237 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); 3263 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, 3274 return DAG.getNode(ISD::TRUNCATE, S [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1044 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1045 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 2388 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2409 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 3509 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3515 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3521 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3566 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3571 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3576 Val = DAG.getNode(ISD::TRUNCATE, D [all...] |