/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVRegisterBankInfo.cpp | 25 RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo &TRI) argument
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H A D | RISCVRegisterBankInfo.h | 34 RISCVRegisterBankInfo(const TargetRegisterInfo &TRI);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsOptionRecord.h | 46 const MCRegisterInfo *TRI = Context.getRegisterInfo(); local 47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); 48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); 49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); 50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); 51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); 52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); 53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); 54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); 55 COP3RegClass = &(TRI [all...] |
H A D | MipsFrameLowering.cpp | 95 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); local 99 TRI->needsStackRealignment(MF); 104 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); local 106 return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); 116 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); local 126 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) { 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreMachineFunctionInfo.cpp | 39 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); local 43 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); 45 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), 46 TRI.getSpillAlignment(RC), true); 57 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); local 59 FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), 60 TRI.getSpillAlignment(RC), true); 70 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); local 72 unsigned Size = TRI.getSpillSize(RC); 73 unsigned Align = TRI [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBank.cpp | 31 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { 33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); 45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); 52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && 81 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { 82 print(dbgs(), /* IsForDebug */ true, TRI); local 87 const TargetRegisterInfo *TRI) const { 97 if (!TRI || ContainedRegClasses.empty()) 99 assert(ContainedRegClasses.size() == TRI [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | LivePhysRegs.h | 49 const TargetRegisterInfo *TRI = nullptr; member in class:llvm::LivePhysRegs 58 LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) { argument 59 LiveRegs.setUniverse(TRI.getNumRegs()); 66 void init(const TargetRegisterInfo &TRI) { argument 67 this->TRI = &TRI; 69 LiveRegs.setUniverse(TRI.getNumRegs()); 80 assert(TRI [all...] |
H A D | LiveRegUnits.h | 31 const TargetRegisterInfo *TRI = nullptr; member in class:llvm::LiveRegUnits 39 LiveRegUnits(const TargetRegisterInfo &TRI) { argument 40 init(TRI); 50 const TargetRegisterInfo *TRI) { 63 if (!TRI->isConstantPhysReg(Reg)) 74 void init(const TargetRegisterInfo &TRI) { argument 75 this->TRI = &TRI; 77 Units.resize(TRI.getNumRegUnits()); 88 for (MCRegUnitIterator Unit(Reg, TRI); Uni 47 accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 48 if (MF->getSubtarget().getRegisterInfo() != TRI) { 49 TRI = MF->getSubtarget().getRegisterInfo(); 50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 55 assert(TRI && "no register info set"); 62 CalleeSavedAliases.assign(TRI->getNumRegs(), 0); 64 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) 80 unsigned NumPSets = TRI->getNumRegPressureSets(); 115 unsigned Cost = TRI->getCostPerUse(PhysReg); 135 unsigned Cost = TRI->getCostPerUse(PhysReg); 148 TRI [all...] |
H A D | AllocationOrder.cpp | 35 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); local 37 if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix)) 45 dbgs() << ' ' << printReg(Hints[I], TRI);
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H A D | RegisterCoalescer.h | 27 const TargetRegisterInfo &TRI; member in class:llvm::CoalescerPair 58 CoalescerPair(const TargetRegisterInfo &tri) : TRI(tri) {} 64 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {}
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H A D | LiveRegMatrix.cpp | 56 TRI = MF.getSubtarget().getRegisterInfo(); 60 unsigned NumRegUnits = TRI->getNumRegUnits(); 80 static bool foreachUnit(const TargetRegisterInfo *TRI, argument 84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " 106 << printReg(PhysReg, TRI) << ':'); 111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { 112 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); 123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " fro [all...] |
H A D | RegUsageInfoCollector.cpp | 103 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); local 128 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs()); 148 for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF)) 149 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 155 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { 162 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) 182 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { 184 dbgs() << printReg(PReg, TRI) << " "; 198 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); local 207 const MCPhysReg *CSRegs = TRI [all...] |
H A D | TargetRegisterInfo.cpp | 89 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, argument 91 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { 103 } else if (!TRI) 105 else if (Reg < TRI->getNumRegs()) { 107 printLowerCase(TRI->getName(Reg), OS); 112 if (TRI) 113 OS << ':' << TRI->getSubRegIndexName(SubIdx); 120 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { argument 121 return Printable([Unit, TRI](raw_ostream &OS) { 122 // Generic printout when TRI i [all...] |
H A D | MachineCopyPropagation.cpp | 100 const TargetRegisterInfo &TRI) { 103 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { 112 void invalidateRegister(unsigned Reg, const TargetRegisterInfo &TRI) { argument 117 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { 129 for (MCRegUnitIterator RUI(InvalidReg, &TRI); RUI.isValid(); ++RUI) 134 void clobberRegister(unsigned Reg, const TargetRegisterInfo &TRI) { argument 135 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { 140 markRegsUnavailable(I->second.DefRegs, TRI); 144 markRegsUnavailable({MI->getOperand(0).getReg()}, TRI); 152 void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI) { argument 99 markRegsUnavailable(ArrayRef<unsigned> Regs, const TargetRegisterInfo &TRI) argument 176 findCopyForUnit(unsigned RegUnit, const TargetRegisterInfo &TRI, bool MustBeAvailable = false) argument 186 findCopyDefViaUnit(unsigned RegUnit, const TargetRegisterInfo &TRI) argument 197 findAvailBackwardCopy(MachineInstr &I, unsigned Reg, const TargetRegisterInfo &TRI) argument 218 findAvailCopy(MachineInstr &DestCopy, unsigned Reg, const TargetRegisterInfo &TRI) argument 249 const TargetRegisterInfo *TRI; member in class:__anon1751::MachineCopyPropagation 333 isNopCopy(const MachineInstr &PreviousCopy, unsigned Src, unsigned Def, const TargetRegisterInfo *TRI) argument [all...] |
H A D | RDFRegisters.cpp | 29 : TRI(tri) { 30 RegInfos.resize(TRI.getNumRegs()); 32 BitVector BadRC(TRI.getNumRegs()); 33 for (const TargetRegisterClass *RC : TRI.regclasses()) { 46 UnitInfos.resize(TRI.getNumRegUnits()); 48 for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) { 51 MCRegUnitRootIterator R(U, &TRI); 59 for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) { 75 for (const uint32_t *RM : TRI.getRegMasks()) 85 BitVector PU(TRI [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | RegisterBank.h | 65 bool verify(const TargetRegisterInfo &TRI) const; 81 void dump(const TargetRegisterInfo *TRI = nullptr) const; 86 /// TRI is then used to print the name of the register classes that 89 const TargetRegisterInfo *TRI = nullptr) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUMacroFusion.cpp | 46 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); local 49 return FirstMI->definesRegister(Src2->getReg(), TRI);
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H A D | R600ExpandSpecialInstrs.cpp | 86 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 136 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 139 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; 142 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); 166 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && 167 (TRI.getEncodingValue(Src1) & 0xff) < 127) 168 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); 223 Src0 = TRI.getSubReg(Src0, SubRegIndex); 224 Src1 = TRI [all...] |
H A D | SIFixSGPRCopies.cpp | 118 const SIRegisterInfo *TRI; member in class:__anon2111::SIFixSGPRCopies 154 const SIRegisterInfo *TRI) { 161 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) 169 const SIRegisterInfo &TRI, 176 : TRI.getPhysRegClass(SrcReg); 179 // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg()); 183 : TRI.getPhysRegClass(DstReg); 190 const SIRegisterInfo &TRI) { 191 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && 192 TRI 153 hasVectorOperands(const MachineInstr &MI, const SIRegisterInfo *TRI) argument 168 getCopyRegClasses(const MachineInstr &Copy, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) argument 188 isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument 195 isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument 202 tryChangeVGPRtoSGPRinCopy(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII) argument 240 foldVGPRCopyIntoRegSequence(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII, MachineRegisterInfo &MRI) argument [all...] |
H A D | SILowerSGPRSpills.cpp | 49 const SIRegisterInfo *TRI = nullptr; member in class:__anon2123::SILowerSGPRSpills 94 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); local 97 if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) { 103 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 106 TRI); 126 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); local 133 if (!TFI->restoreCalleeSavedRegisters(RestoreBlock, I, CSI, TRI)) { 136 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 138 TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC, TRI); 209 const TargetRegisterClass *RC = TRI [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64PBQPRegAlloc.h | 27 const TargetRegisterInfo *TRI; member in class:llvm::A57ChainingConstraint
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMRegisterBankInfo.h | 33 ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCQPXLoadSplat.cpp | 62 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); local 85 if (MI->modifiesRegister(SrcReg, TRI)) { 104 TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg()); 105 Register SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex); 110 MI->substituteRegister(SrcReg, SplatReg, 0, *TRI); 134 if (MI->modifiesRegister(SplatReg, TRI) || 136 MI->readsRegister(SplatReg, TRI))) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMIChecking.cpp | 34 const TargetRegisterInfo *TRI; member in struct:__anon2204::BPFMIPreEmitChecking 61 TRI = MF->getSubtarget<BPFSubtarget>().getRegisterInfo(); 106 static bool hasLiveDefs(const MachineInstr &MI, const TargetRegisterInfo *TRI) { argument 149 for (MCSuperRegIterator SR(I, TRI); SR.isValid(); ++SR) 165 if (hasLiveDefs(MI, TRI)) {
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