Lines Matching refs:TRI
29 : TRI(tri) {
30 RegInfos.resize(TRI.getNumRegs());
32 BitVector BadRC(TRI.getNumRegs());
33 for (const TargetRegisterClass *RC : TRI.regclasses()) {
46 UnitInfos.resize(TRI.getNumRegUnits());
48 for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {
51 MCRegUnitRootIterator R(U, &TRI);
59 for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) {
75 for (const uint32_t *RM : TRI.getRegMasks())
85 BitVector PU(TRI.getNumRegUnits());
87 for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
90 for (MCRegUnitIterator U(i, &TRI); U.isValid(); ++U)
108 for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
121 for (MCRegAliasIterator AI(Reg, &TRI, false); AI.isValid(); ++AI)
135 MCRegUnitMaskIterator UMA(RA.Reg, &TRI);
136 MCRegUnitMaskIterator UMB(RB.Reg, &TRI);
181 for (MCSubRegIndexIterator SI(RR.Reg, &TRI); SI.isValid(); ++SI) {
182 LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex());
199 unsigned NumRegs = TRI.getNumRegs();
228 if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg))
229 return RegisterRef(R, TRI.composeSubRegIndexLaneMask(Idx, RR.Mask));
230 if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) {
234 LaneBitmask M = TRI.reverseComposeSubRegIndexLaneMask(Idx, RR.Mask);