/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 74 unsigned Lane, const TargetRegisterClass *TRC); 97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC); 133 const TargetRegisterClass *TRC) { 139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 141 return TRC->contains(Reg); 270 const TargetRegisterClass *TRC = local 272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 435 const TargetRegisterClass *TRC) { 436 Register Out = MRI->createVirtualRegister(TRC); 132 usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC) argument 432 createExtractSubreg( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument
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H A D | ARMISelLowering.cpp | 9505 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass local 9524 Register NewVReg1 = MRI->createVirtualRegister(TRC); 9530 Register NewVReg2 = MRI->createVirtualRegister(TRC); 9536 Register NewVReg3 = MRI->createVirtualRegister(TRC); 9554 Register NewVReg1 = MRI->createVirtualRegister(TRC); 9559 Register NewVReg2 = MRI->createVirtualRegister(TRC); 9564 Register NewVReg3 = MRI->createVirtualRegister(TRC); 9569 Register NewVReg4 = MRI->createVirtualRegister(TRC); 9575 Register NewVReg5 = MRI->createVirtualRegister(TRC); 9590 Register NewVReg1 = MRI->createVirtualRegister(TRC); 9619 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass local 10172 const TargetRegisterClass *TRC = nullptr; local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 2330 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); 2331 MRI->constrainRegClass(FirstReg, TRC); 2332 MRI->constrainRegClass(SecondReg, TRC);
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H A D | ARMBaseInstrInfo.cpp | 3299 const TargetRegisterClass *TRC = MRI->getRegClass(Reg); local 3300 Register NewReg = MRI->createVirtualRegister(TRC); 3322 MRI->setRegClass(UseMI.getOperand(0).getReg(), TRC);
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/freebsd-11-stable/usr.sbin/lpr/lpd/ |
H A D | printjob.c | 1500 #define TRC(q) (((q)-' ')&0177) macro 1514 d = dropit(c = TRC(cc = *sp++)); 1539 case TRC('_'): 1540 case TRC(';'): 1541 case TRC(','): 1542 case TRC('g'): 1543 case TRC('j'): 1544 case TRC('p'): 1545 case TRC('q'): 1546 case TRC(' [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 499 const TargetRegisterClass *TRC = 517 TRC == MRI->getRegClass(SrcReg)) { 523 VRBase = MRI->createVirtualRegister(TRC); 537 VRBase = MRI->createVirtualRegister(TRC); 654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 656 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyAsmPrinter.cpp | 59 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); local 62 if (TRI->isTypeLegalForClass(*TRC, T))
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/freebsd-11-stable/contrib/llvm-project/clang/include/clang/AST/ |
H A D | ASTNodeTraverser.h | 387 if (const Expr *TRC = D->getTrailingRequiresClause()) 388 Visit(TRC);
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H A D | Decl.h | 2385 if (auto *TRC = getTrailingRequiresClause()) 2386 AC.push_back(TRC);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 502 const TargetRegisterClass &TRC = *getRegClass(Reg); local 503 return TRC.getLaneMask();
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H A D | RegAllocPBQP.cpp | 604 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); local 612 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
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H A D | LiveDebugVariables.cpp | 1204 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); local 1205 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.h | 1053 /// \brief Returns true if a reg:subreg pair P has a TRC class 1055 const TargetRegisterClass &TRC, 1059 return RC == &TRC; 1061 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); 1054 isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.h | 72 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86AvoidStoreForwardingBlocks.cpp | 566 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, local 568 return TRI->getRegSizeInBits(*TRC) / 8;
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/ |
H A D | SemaTemplateVariadic.cpp | 940 if (Expr *TRC = D.getTrailingRequiresClause()) 941 if (TRC->containsUnexpandedParameterPack())
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H A D | SemaLookup.cpp | 5117 /// \param TRC A TypoRecoveryCallback functor that will be used to build an 5137 TypoDiagnosticGenerator TDG, TypoRecoveryCallback TRC, CorrectTypoKind Mode, 5165 return createDelayedTypo(std::move(Consumer), std::move(TDG), std::move(TRC)); 5505 TypoRecoveryCallback TRC) { 5511 State.RecoveryHandler = std::move(TRC);
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/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/ |
H A D | DeclTemplate.cpp | 207 if (const Expr *TRC = FD->getTrailingRequiresClause()) 208 AC.push_back(TRC);
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/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Sema/ |
H A D | DeclSpec.h | 2441 void setTrailingRequiresClause(Expr *TRC) { 2442 TrailingRequiresClause = TRC;
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H A D | Sema.h | 3586 TypoRecoveryCallback TRC); 3715 TypoRecoveryCallback TRC, CorrectTypoKind Mode,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCMIPeephole.cpp | 776 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 local 779 MRI->setRegClass(DominatorReg, TRC);
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H A D | PPCISelDAGToDAG.cpp | 321 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1); variable 323 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 1987 const TargetRegisterClass *TRC; local 1989 TRC = &Hexagon::PredRegsRegClass; 1991 TRC = &Hexagon::IntRegsRegClass; 1993 TRC = &Hexagon::DoubleRegsRegClass; 1998 Register NewReg = MRI.createVirtualRegister(TRC);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 1669 const TargetRegisterClass *TRC = local 1672 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 316 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF); local 318 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
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