/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 172 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 828 MVT SrcVT = SrcEVT.getSimpleVT(); 830 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits()) 844 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || 845 SrcVT == MVT::i8 || SrcVT == MVT::i1) { 870 switch (SrcVT.SimpleTy) { 935 if (!PPCEmitIntExt(SrcVT, SrcReg 960 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local 978 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local 1019 PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg, bool IsSigned) argument 1190 MVT DstVT, SrcVT; local 1804 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument 1875 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, 191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg); 193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg); 194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, 196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, 1000 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local 1003 if (SrcVT != MVT::f32 || DestVT != MVT::f64) 1079 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local 1082 if (SrcVT ! 1213 MVT SrcVT = ArgVT; local 1221 MVT SrcVT = ArgVT; local 1785 EVT SrcVT, DestVT; local 1832 emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument 1851 emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument 1866 emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument 1875 emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument 1897 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument 1911 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT); 233 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 264 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill, 268 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill, 272 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill, 1183 MVT SrcVT = RetVT; local 1210 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); 1308 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); 2881 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); 2882 if (SrcVT 2921 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); local 3093 MVT SrcVT = ArgVT; local 3103 MVT SrcVT = ArgVT; local 4112 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4219 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4340 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4422 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool IsZExt) argument 4531 optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT) argument 4589 MVT SrcVT; local 4703 MVT SrcVT = VT; local 4769 MVT SrcVT = RetVT; local 4848 MVT RetVT, SrcVT; local [all...] |
H A D | AArch64ISelLowering.cpp | 5088 EVT SrcVT = In2.getValueType(); local 5090 if (SrcVT.bitsLT(VT)) 5092 else if (SrcVT.bitsGT(VT)) 6622 EVT SrcVT = Src.ShuffleVec.getValueType(); local 6624 if (SrcVT.getSizeInBits() == VT.getSizeInBits()) 6629 EVT EltVT = SrcVT.getVectorElementType(); 6633 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) { 6634 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits()); 6643 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits()); 8379 EVT SrcVT local 9616 isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const argument 11165 EVT SrcVT = Src->getValueType(0); local 12233 EVT SrcVT = N0.getOperand(0).getValueType(); local 12363 const EVT SrcVT = Src->getValueType(0); local [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 490 EVT SrcVT; local 492 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); 494 SrcVT = N.getOperand(0).getValueType(); 496 if (!IsLoadStore && SrcVT == MVT::i8) 498 else if (!IsLoadStore && SrcVT == MVT::i16) 500 else if (SrcVT == MVT::i32) 502 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); 507 EVT SrcVT = N.getOperand(0).getValueType(); local 508 if (!IsLoadStore && SrcVT == MVT::i8) 510 else if (!IsLoadStore && SrcVT [all...] |
H A D | AArch64TargetTransformInfo.cpp | 427 auto SrcVT = TLI->getValueType(DL, Src); local 437 if (DstVT.getSizeInBits() < SrcVT.getSizeInBits()) 452 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 708 EVT SrcVT = LD->getMemoryVT(); local 709 EVT SrcEltVT = SrcVT.getScalarType(); 710 unsigned NumElem = SrcVT.getVectorNumElements(); 714 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) { 740 unsigned RemainingBytes = SrcVT.getStoreSize(); 1079 EVT SrcVT = Src.getValueType(); local 1080 int NumSrcElements = SrcVT.getVectorNumElements(); 1082 // *_EXTEND_VECTOR_INREG SrcVT can be smaller than VT - so insert the vector 1084 if (SrcVT.bitsLE(VT)) { 1085 assert((VT.getSizeInBits() % SrcVT 1114 EVT SrcVT = Src.getValueType(); local 1139 EVT SrcVT = Src.getValueType(); local [all...] |
H A D | TargetLowering.cpp | 630 EVT SrcVT = Src.getValueType(); local 632 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); 641 if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0 && 644 unsigned NumSrcElts = SrcVT.getVectorNumElements(); 667 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; 1680 EVT SrcVT = Src.getValueType(); local 1681 unsigned InBits = SrcVT.getScalarSizeInBits(); 1682 unsigned InElts = SrcVT.isVector() ? SrcVT 1713 EVT SrcVT = Src.getValueType(); local 1761 EVT SrcVT = Src.getValueType(); local 1894 EVT SrcVT = Src.getValueType(); local 2196 EVT SrcVT = Src.getValueType(); local [all...] |
H A D | FastISel.cpp | 1507 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local 1510 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || 1520 if (!TLI.isTypeLegal(SrcVT)) 1530 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 1557 MVT SrcVT = SrcEVT.getSimpleVT(); 1566 if (SrcVT == DstVT) { 1567 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); 1579 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); 1913 EVT SrcVT local [all...] |
H A D | LegalizeDAG.cpp | 722 EVT SrcVT = LD->getMemoryVT(); local 723 unsigned SrcWidth = SrcVT.getSizeInBits(); 728 if (SrcWidth != SrcVT.getStoreSizeInBits() && 736 (SrcVT != MVT::i1 || 741 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 746 // way. A zext load from NVT thus automatically gives zext from SrcVT. 761 Result, DAG.getValueType(SrcVT)); 766 DAG.getValueType(SrcVT)); 772 assert(!SrcVT.isVector() && "Unsupported extload!"); 850 SrcVT [all...] |
H A D | LegalizeFloatTypes.cpp | 1560 EVT SrcVT = Src.getValueType(); local 1567 if (SrcVT.bitsLE(MVT::i32)) { 1576 if (SrcVT.bitsLE(MVT::i64)) { 1580 } else if (SrcVT.bitsLE(MVT::i128)) { 1597 SrcVT = Src.getValueType(); 1605 switch (SrcVT.getSimpleVT().SimpleTy) { 1624 Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.h | 74 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 76 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
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H A D | RISCVISelLowering.cpp | 320 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { argument 321 if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() || 322 !SrcVT.isInteger() || !DstVT.isInteger()) 324 unsigned SrcBits = SrcVT.getSizeInBits(); 343 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { argument 344 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 205 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 1355 MVT SrcVT = SrcEVT.getSimpleVT(); 1371 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || 1372 SrcVT == MVT::i1) { 1386 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) 1394 switch (SrcVT.SimpleTy) { 1436 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg 2585 EVT SrcVT, DestVT; local 2603 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument [all...] |
H A D | ARMISelLowering.h | 355 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 522 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 281 EVT SrcVT = Src.getValueType(); local 285 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)),
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H A D | X86FastISel.cpp | 97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 703 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 706 unsigned Src, EVT SrcVT, 708 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 1222 EVT SrcVT = TLI.getValueType(DL, RV->getType()); local 1225 if (SrcVT != DstVT) { 1226 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) 1234 if (SrcVT 705 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument 2531 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local 3644 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local [all...] |
H A D | X86ISelLowering.cpp | 5116 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 5124 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && 6410 EVT SrcVT = Op.getOperand(0).getValueType(); 6411 unsigned NumSrcElts = SrcVT.getVectorNumElements(); 7326 EVT SrcVT = SrcVec.getValueType(); 7327 unsigned NumSrcElts = SrcVT.getVectorNumElements(); 7328 unsigned NumZeros = (NumBitsPerElt / SrcVT.getScalarSizeInBits()) - 1; 7449 MVT SrcVT = Src.getSimpleValueType(); 7450 if (!SrcVT.isVector()) 7453 if (NumSizeInBits != SrcVT [all...] |
H A D | X86ISelLowering.h | 819 ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const override; 1157 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 1230 std::pair<SDValue, SDValue> BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
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H A D | X86ISelDAGToDAG.cpp | 1037 MVT SrcVT = N->getOperand(0).getSimpleValueType(); local 1041 if (SrcVT.isVector() || DstVT.isVector()) 1048 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT); 1065 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; 1090 MVT SrcVT = N->getOperand(1).getSimpleValueType(); local 1094 if (SrcVT.isVector() || DstVT.isVector()) 1101 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT); 1118 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT; 1138 assert(SrcVT == MemVT && "Unexpected VT!");
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TypePromotion.cpp | 975 EVT SrcVT = TLI->getValueType(DL, I->getType()); local 976 if (SrcVT.isSimple() && TLI->isTypeLegal(SrcVT.getSimpleVT())) 979 if (TLI->getTypeAction(ICmp->getContext(), SrcVT) != 983 EVT PromotedVT = TLI->getTypeToTransformTo(ICmp->getContext(), SrcVT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 684 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); local 685 if (!DstVT || !SrcVT) 689 unsigned SrcNumElems = SrcVT->getNumElements(); 721 Type *MidTy = VectorType::get(SrcVT->getElementType(), FanIn);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 820 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { argument 827 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; 2509 EVT SrcVT = Src.getValueType(); local 2511 if (SrcVT == MVT::i16) { 2521 assert(SrcVT == MVT::i64 && "operation should be legal"); 2546 EVT SrcVT = Src.getValueType(); local 2548 if (SrcVT == MVT::i16) { 2558 assert(SrcVT == MVT::i64 && "operation should be legal"); 2715 EVT SrcVT = Src.getValueType(); local 2716 if (Subtarget->has16BitInsts() && SrcVT 2738 EVT SrcVT = Src.getValueType(); local 2998 EVT SrcVT = Src.getValueType(); local 3248 EVT SrcVT = Src.getValueType(); local 3853 EVT SrcVT = Src.getValueType(); local 3878 EVT SrcVT = Src.getValueType(); local 3921 EVT SrcVT = Src.getValueType(); local [all...] |
H A D | SIISelLowering.h | 226 EVT SrcVT) const override;
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 2476 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { 2477 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && 2486 EVT DestVT, EVT SrcVT) const { 2487 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && 2489 return isFPExtFree(DestVT, SrcVT); 2557 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, argument 3359 ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const { 3358 isDesirableToCombineBuildVectorToShuffleTruncate( ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const argument
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