/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.h | 120 class SrcOp { class in namespace:llvm 130 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} function in class:llvm::SrcOp 131 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} function in class:llvm::SrcOp 132 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} function in class:llvm::SrcOp 133 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} function in class:llvm::SrcOp 137 SrcOp(unsigned) = delete; 138 SrcOp(int) = delete; 139 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} function in class:llvm::SrcOp 140 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} function in class:llvm::SrcOp 169 llvm_unreachable("Unrecognised SrcOp [all...] |
H A D | CSEMIRBuilder.h | 63 void profileSrcOp(const SrcOp &Op, GISelInstProfileBuilder &B) const; 65 void profileSrcOps(ArrayRef<SrcOp> Ops, GISelInstProfileBuilder &B) const { 66 for (const SrcOp &Op : Ops) 73 ArrayRef<SrcOp> SrcOps, Optional<unsigned> Flags, 95 ArrayRef<SrcOp> SrcOps,
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H A D | ConstantFoldingMIRBuilder.h | 29 ArrayRef<SrcOp> SrcOps, 50 const SrcOp &Src0 = SrcOps[0]; 51 const SrcOp &Src1 = SrcOps[1]; 61 const SrcOp &Src0 = SrcOps[0]; 62 const SrcOp &Src1 = SrcOps[1];
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H A D | LegalizationArtifactCombiner.h | 300 unsigned SrcOp = SrcDef->getOpcode(); local 301 if (isArtifactCast(SrcOp)) { 302 ConvertOp = SrcOp;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.cpp | 164 const SrcOp &Size, 215 const SrcOp &Op0, 216 const SrcOp &Op1) { 241 const SrcOp &Op0, 274 const SrcOp &Op) { 361 const SrcOp &Addr, 368 const SrcOp &Addr, 380 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val, 381 const SrcOp &Addr, 395 const SrcOp [all...] |
H A D | CSEMIRBuilder.cpp | 70 void CSEMIRBuilder::profileSrcOp(const SrcOp &Op, 73 case SrcOp::SrcType::Ty_Predicate: 91 ArrayRef<SrcOp> SrcOps, 139 ArrayRef<SrcOp> SrcOps, 169 const SrcOp &Src0 = SrcOps[0]; 170 const SrcOp &Src1 = SrcOps[1];
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H A D | LegalizerHelper.cpp | 1351 SrcOp Src(SrcReg); 2380 SmallVector<SrcOp, 4> SrcOps; 2396 SmallVector<SrcOp, 4> SrcOps; 3102 SrcOp Lo(Register(0)), Hi(Register(0));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Linker/ |
H A D | IRMover.cpp | 1227 MDNode *SrcOp = SrcModFlags->getOperand(I); local 1229 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); 1230 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); 1240 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { 1241 DstModFlags->addOperand(SrcOp); 1248 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); 1249 DstModFlags->addOperand(SrcOp); 1259 DstModFlags->setOperand(DstIndex, SrcOp); 1260 Flags[ID].first = SrcOp; 1267 SrcOp [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SILowerControlFlow.cpp | 465 for (const auto &SrcOp : Def->explicit_operands()) 466 if (SrcOp.isReg() && SrcOp.isUse() && 467 (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec)) 468 Src.push_back(SrcOp);
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H A D | SIPeepholeSDWA.cpp | 163 const MachineOperand *SrcOp) const; 331 const MachineOperand *SrcOp) const { 333 const auto *MI = SrcOp->getParent(); 334 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { 338 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) {
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H A D | SIInstrInfo.cpp | 1432 const MachineOperand &SrcOp = MI.getOperand(1); local 1434 assert(!SrcOp.isFPImm()); 1435 if (SrcOp.isImm()) { 1436 APInt Imm(64, SrcOp.getImm()); 1444 assert(SrcOp.isReg()); 1446 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) 1449 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) 1596 const MachineOperand &SrcOp = MI.getOperand(I); local 1597 assert(!SrcOp.isFPImm()); 1598 if (SrcOp [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonRDFOpt.cpp | 139 const MachineOperand &SrcOp = MI->getOperand(1); local 141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg()));
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H A D | HexagonExpandCondsets.cpp | 213 MachineInstr *genCondTfrFor(MachineOperand &SrcOp, 619 /// Generate a conditional transfer, copying the value SrcOp to the 623 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, argument 627 MachineInstr *MI = SrcOp.getParent(); 637 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); 642 if (SrcOp.isReg()) { 643 unsigned SrcState = getRegState(SrcOp); 644 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) 649 .addReg(SrcOp.getReg(), SrcState, SrcOp [all...] |
H A D | HexagonFrameLowering.cpp | 2305 MachineOperand &SrcOp = SI.getOperand(2); local 2307 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), 2308 SrcOp.getSubReg() }; 2330 .add(SrcOp); 2337 if (unsigned SR = SrcOp.getSubReg()) 2338 SrcOp.setReg(HRI.getSubReg(FoundR, SR)); 2340 SrcOp.setReg(FoundR); 2341 SrcOp.setSubReg(0); 2343 SrcOp.setIsKill(false);
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H A D | HexagonInstrInfo.cpp | 1098 const MachineOperand &SrcOp = MI.getOperand(2); local 1099 assert(SrcOp.getSubReg() == 0); 1109 .addReg(SrcOp.getReg(), getRegState(SrcOp))
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H A D | HexagonBitSimplify.cpp | 2535 const MachineOperand &SrcOp = MI->getOperand(1); 2536 if (SrcOp.getReg() == R)
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenInstruction.cpp | 284 std::pair<unsigned,unsigned> SrcOp = (FirstIsDest ? RHSOp : LHSOp); local 292 if (SrcOp.first < Ops.NumDefs) 300 if (!Ops[SrcOp.first].Constraints[SrcOp.second].isNone()) 318 Ops[SrcOp.first].Constraints[SrcOp.second] = NewConstraint;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineVerifier.cpp | 1279 const MachineOperand &SrcOp = MI->getOperand(1); local 1280 if (!SrcOp.isReg()) { 1292 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits(); 1301 const MachineOperand &SrcOp = MI->getOperand(2); local 1302 if (!SrcOp.isReg()) { 1314 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits(); 1529 const MachineOperand &SrcOp = MI->getOperand(1); local 1531 LLT SrcTy = MRI->getType(SrcOp.getReg()); 1542 unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI); 1547 if (!DstOp.getSubReg() && !SrcOp [all...] |
H A D | MachineScheduler.cpp | 1689 const MachineOperand &SrcOp = Copy->getOperand(1); local 1690 Register SrcReg = SrcOp.getReg(); 1691 if (!Register::isVirtualRegister(SrcReg) || !SrcOp.readsReg())
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstructionCombining.cpp | 2196 Value *SrcOp = BCI->getOperand(0); local 2222 ? Builder.CreateInBoundsGEP(SrcEltType, SrcOp, {Ops[1], Ops[2]}) 2223 : Builder.CreateGEP(SrcEltType, SrcOp, {Ops[1], Ops[2]}); 2240 if (!isa<BitCastInst>(SrcOp) && GEP.accumulateConstantOffset(DL, Offset)) { 2246 if (isa<AllocaInst>(SrcOp) || isAllocationFn(SrcOp, &TLI)) { 2259 return new AddrSpaceCastInst(SrcOp, GEPType); 2260 return new BitCastInst(SrcOp, GEPType); 2270 ? Builder.CreateInBoundsGEP(SrcEltType, SrcOp, NewIndices) 2271 : Builder.CreateGEP(SrcEltType, SrcOp, NewIndice [all...] |
H A D | InstCombineCasts.cpp | 1118 if (auto *SrcOp = dyn_cast<Instruction>(Src)) 1119 if (SrcOp->hasOneUse()) 1120 replaceAllDbgUsesWith(*SrcOp, *Res, CI, DT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 3287 Value *SrcOp = LI->getOperand(0); local 3288 Type *SrcTy = SrcOp->getType(); 3297 if (Value *V = SimplifyICmpInst(Pred, SrcOp, 3304 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), 3317 SrcOp, RI->getOperand(0), Q, 3333 SrcOp, Trunc, Q, MaxRecurse-1)) 3376 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), 3391 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, Q, MaxRecurse-1)) 3423 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp, 3432 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp, [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 161 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, 163 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, 1742 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1745 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT, 1747 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode()); 1750 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT, 1755 SrcOp.getValueType().getTypeForEVT(*DAG.getContext())); 1763 unsigned SrcSize = SrcOp.getValueSizeInBits(); 1774 Store = DAG.getTruncStore(Chain, dl, SrcOp, FIPtr, PtrInfo, 1779 DAG.getStore(Chain, dl, SrcOp, FIPt [all...] |
H A D | SelectionDAG.cpp | 2540 SDValue SrcOp = Op.getOperand(i); 2541 Known2 = computeKnownBits(SrcOp, Depth + 1); 2544 if (SrcOp.getValueSizeInBits() != BitWidth) { 2545 assert(SrcOp.getValueSizeInBits() > BitWidth && 3537 SDValue SrcOp = Op.getOperand(i); 3541 if (SrcOp.getValueSizeInBits() != VTBits) { 3542 assert(SrcOp.getValueSizeInBits() > VTBits && 3544 unsigned ExtraBits = SrcOp.getValueSizeInBits() - VTBits;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 7925 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, 7931 SrcOp = DAG.getBitcast(ShVT, SrcOp); 7934 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal)); 7937 static SDValue LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, const SDLoc &dl, 7943 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 23286 SDValue SrcOp, uint64_t ShiftAmt, 23292 if (VT != SrcOp.getSimpleValueType()) 23293 SrcOp = DAG.getBitcast(VT, SrcOp); [all...] |