Searched refs:ShiftAmount (Results 1 - 25 of 26) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Utils/
H A DRISCVMatInt.cpp68 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); local
69 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
73 Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.h48 unsigned ShiftAmount) const;
H A DMipsSEISelDAGToDAG.cpp283 unsigned ShiftAmount = 0) const {
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
297 const Align Alignment(1ULL << ShiftAmount);
H A DMipsTargetStreamer.h142 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp222 unsigned ShiftAmount = countTrailingZeros(MaxAlignment); local
227 .addImm(ShiftAmount);
230 .addImm(ShiftAmount);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h188 template <unsigned ShiftAmount = 0>
H A DMipsTargetStreamer.cpp265 int16_t ShiftAmount, SMLoc IDLoc,
267 if (ShiftAmount >= 32) {
268 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
272 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
264 emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
H A DMipsMCCodeEmitter.cpp767 template <unsigned ShiftAmount>
778 OffBits >>= ShiftAmount; local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp354 unsigned ShiftAmount; member in struct:__anon2053::AArch64Operand::ShiftedImmOp
511 return ShiftedImm.ShiftAmount;
797 unsigned Shift = ShiftedImm.ShiftAmount;
1817 unsigned ShiftAmount = 0,
1825 Op->Reg.ShiftExtend.Amount = ShiftAmount;
1836 unsigned ShiftAmount = 0,
1841 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,
1881 unsigned ShiftAmount,
1886 Op->ShiftedImm.ShiftAmount = ShiftAmount;
1880 CreateShiftedImm(const MCExpr *Val, unsigned ShiftAmount, SMLoc S, SMLoc E, MCContext &Ctx) argument
2649 int64_t ShiftAmount = Parser.getTok().getIntVal(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp970 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
975 if (ShiftAmount >= 8) {
995 ShiftAmount -= 8;
998 if (Opc == ISD::SRL && ShiftAmount) {
1002 ShiftAmount -= 1;
1005 while (ShiftAmount--)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp5638 unsigned ShiftAmount = Width - 1; local
5640 ShiftAmount = C->countTrailingZeros();
5644 Upper = C->ashr(ShiftAmount) + 1;
5647 Lower = C->ashr(ShiftAmount);
5659 unsigned ShiftAmount = Width - 1; local
5661 ShiftAmount = C->countTrailingZeros();
5662 Lower = C->lshr(ShiftAmount);
5676 unsigned ShiftAmount = C->countLeadingOnes() - 1; local
5677 Lower = C->shl(ShiftAmount);
5681 unsigned ShiftAmount local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1851 uint64_t ShiftAmount = V.getConstantOperandVal(1); local
1852 if (ShiftAmount == Power)
1854 Ops[1] = CurDAG->getConstant(ShiftAmount - Power,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1125 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); local
1127 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
1128 ShiftAmount);
H A DLegalizeIntegerTypes.cpp721 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT); local
723 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
725 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
729 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
3121 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy); local
3123 ShiftAmount);
3125 ShiftAmount);
H A DTargetLowering.cpp5821 unsigned ShiftAmount = OuterBitSize - InnerBitSize;
5823 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) {
5829 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy);
6641 SDValue ShiftAmount =
6644 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
6817 SDValue ShiftAmount =
6820 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
6931 SDValue ShiftAmount = DAG.getConstant(
6934 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
H A DLegalizeDAG.cpp1541 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1547 if (ShiftAmount > 0) {
1548 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT);
1550 } else if (ShiftAmount < 0) {
1551 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT);
H A DDAGCombiner.cpp9600 SDValue ShiftAmount = DAG.getConstant(ShCt, DL, VT); local
9603 return DAG.getNode(ShiftOpcode, DL, VT, NotX, ShiftAmount);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp474 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; local
476 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0))
487 unsigned Elt = ShiftAmount / DestWidth;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2200 SDValue &Src, int &ShiftAmount,
2234 ShiftAmount = countTrailingZeros(NonZeroBits);
2235 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount);
2242 if (ShlImm - ShiftAmount != 0 && !BiggerPattern)
2244 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
2198 isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, SDValue &Src, int &ShiftAmount, int &MaskWidth) argument
H A DAArch64ISelLowering.cpp8830 uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1); local
8832 if (ShiftAmount == Log2_32(LoadBytes))
10086 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, argument
10098 ShiftAmount = N->getConstantOperandVal(1);
10754 int64_t ShiftAmount; local
10764 ShiftAmount = SplatValue.getSExtValue();
10766 ShiftAmount = CVN->getSExtValue();
10805 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
10808 DAG.getConstant(-ShiftAmount, d
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp309 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); local
332 while (ShiftAmount--) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp402 unsigned &ShiftAmount);
5070 const MCExpr *ShiftAmount; local
5073 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5077 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5153 const MCExpr *ShiftAmount; local
5155 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5159 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5215 const MCExpr *ShiftAmount; local
5217 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1322 template <unsigned Bits, unsigned ShiftAmount = 0>
1330 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())))
1334 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
2786 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); local
2787 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff;
2789 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp14590 unsigned ShiftAmount = TrueConst->logBase2(); local
14591 if (ShiftAmount)
14596 if (ShiftAmount)
14598 DAG.getConstant(ShiftAmount, dl, MVT::i32));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4691 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32); local
4692 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);

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