Searched refs:SRL (Results 1 - 25 of 63) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h36 SRL = 0x27, enumerator in enum:llvm::LPAC::AluCode
94 case SRL:
113 .Case("srl", SRL)
136 case ISD::SRL:
137 return AluCode::SRL;
H A DLanaiMemAluCombiner.cpp222 return LPAC::SRL;
/freebsd-11-stable/crypto/openssl/crypto/sha/asm/
H A Dsha512-mips.pl88 $SRL="dsrl"; # shift right logical
103 $SRL="srl"; # shift right logical
197 $SRL $h,$e,@Sigma1[0]
201 $SRL $tmp0,$e,@Sigma1[1]
205 $SRL $tmp0,$e,@Sigma1[2]
212 $SRL $h,$a,@Sigma0[0]
217 $SRL $tmp0,$a,@Sigma0[1]
221 $SRL $tmp0,$a,@Sigma0[2]
248 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
254 $SRL
[all...]
H A Dsha512-sparcv9.pl61 $SRL="srlx"; # shift right logical
87 $SRL="srl"; # shift right logical
225 $SRL $e,@Sigma1[0],$h !! $i
229 $SRL $e,@Sigma1[1],$tmp0
233 $SRL $e,@Sigma1[2],$tmp0
240 $SRL $a,@Sigma0[0],$h
245 $SRL $a,@Sigma0[1],$tmp0
249 $SRL $a,@Sigma0[2],$tmp0
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp255 // normally expanded to the sequence SRA + SRL + ADD + SRA.
292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand.
318 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand.
333 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand.
337 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split.
452 { ISD::SRL, MVT::v16i16, 1 }, // psrlw.
470 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
471 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
472 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
499 { ISD::SRL, MV
[all...]
H A DX86ISelDAGToDAG.cpp704 case ISD::SRL:
857 case ISD::SRL: {
868 case ISD::SRL: NewOpc = X86ISD::VSRLV; break;
1635 if (Shift.getOpcode() != ISD::SRL ||
1649 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
1771 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
1830 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
1859 if (Shift.getOpcode() != ISD::SRL ||
1885 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
2007 case ISD::SRL
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp90 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
367 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res,
419 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
431 return DAG.getNode(ISD::SRL, dl, NVT,
712 ShiftOp = ISD::SRL;
788 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
1011 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
1169 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
1304 case ISD::SRL:
1909 case ISD::SRL
[all...]
H A DTargetLowering.cpp1337 if (Op0.getOpcode() == ISD::SRL) {
1347 Opc = ISD::SRL;
1390 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL &&
1417 case ISD::SRL: {
1449 unsigned Opc = ISD::SRL;
1485 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1));
1522 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags));
1530 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA));
1805 case ISD::SRL:
1806 // Shrink SRL b
[all...]
H A DDAGCombiner.cpp1278 else if (Opc == ISD::SRL)
1548 case ISD::SRL: return visitSRL(N);
1670 case ISD::SRL:
2061 if (!C || ShiftOp.getOpcode() != ISD::SRL)
2080 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
3002 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3005 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
3256 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
3847 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
3956 return DAG.getNode(ISD::SRL, D
10425 SDValue SRL = N0; local
[all...]
H A DLegalizeDAG.cpp584 ISD::SRL, dl, Value.getValueType(), Value,
596 ISD::SRL, dl, Value.getValueType(), Value,
1178 case ISD::SRL:
1549 SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst);
2625 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, SHVT));
2632 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, SHVT));
2639 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, SHVT));
2652 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2676 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2677 Tmp1 = DAG.getNode(ISD::SRL, d
[all...]
H A DLegalizeVectorOps.cpp107 /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
387 case ISD::SRL:
788 SDValue Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
1222 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) &&
1239 TLI.isOperationLegalOrCustom(ISD::SRL, VT) &&
1335 // Make sure that the SINT_TO_FP and SRL instructions are available.
1340 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) {
1367 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Src, HalfWord);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp136 case ISD::SRL: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp242 case LPAC::SRL:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp326 TwoOperandOpcode == SystemZ::SRL ||
/freebsd-11-stable/crypto/openssl/crypto/bn/asm/
H A Dmips.pl62 $SRL="dsrl";
77 $SRL="srl";
899 $SRL $at,$a1,$t1
914 $SRL $DH,$a2,4*$BNSZ # bits
923 $SRL $HH,$a0,4*$BNSZ # bits
924 $SRL $QT,4*$BNSZ # q=0xffffffff
931 $SRL $at,$a1,4*$BNSZ # bits
956 $SRL $HH,$a0,4*$BNSZ # bits
957 $SRL $QT,4*$BNSZ # q=0xffffffff
964 $SRL
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp372 setOperationAction(ISD::SRL, VT, Expand);
489 setTargetDAGCombine(ISD::SRL);
1823 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
2452 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2632 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2636 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2645 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2677 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);
2685 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,
2700 SDValue Sign = DAG.getNode(ISD::SRL, D
[all...]
H A DR600ISelLowering.cpp811 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
812 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
852 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
853 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
856 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1106 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr,
1270 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr,
1420 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt);
1477 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1522 Ptr = DAG.getNode(ISD::SRL, D
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp805 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
945 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
2352 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2353 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2402 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2403 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2446 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2477 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2584 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2586 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, D
2728 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp607 } else if (Opcode == ISD::SRL) {
737 Op0.getOperand(0).getOpcode() == ISD::SRL) {
739 Op1.getOperand(0).getOpcode() != ISD::SRL) {
745 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
747 Op1.getOperand(0).getOpcode() != ISD::SRL) {
756 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
769 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
1255 case ISD::SRL:
3678 case ISD::SRL:
4445 if ( Op0.getOpcode() == ISD::SRL
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp401 case ISD::SRL:
1610 // Handle the SRL + ANY_EXTEND case.
1612 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, SrlImm)) {
1613 // Extend the incoming operand of the SRL to 64-bit.
1619 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL,
1624 // Use the type of SRL node.
1626 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, SrlImm)) {
1680 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
1703 // SRL Value2, ShiftImm
1712 if (N->getOpcode() != ISD::SRL)
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp78 setOperationAction(ISD::SRL, MVT::i8, Custom);
81 setOperationAction(ISD::SRL, MVT::i16, Custom);
343 case ISD::SRL:
986 case ISD::SRL:
998 if (Opc == ISD::SRL && ShiftAmount) {
1206 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp83 setOperationAction(ISD::SRL, MVT::i8, Custom);
86 setOperationAction(ISD::SRL, MVT::i16, Custom);
294 case ISD::SRL:
322 case ISD::SRL:
689 case ISD::SRL:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp109 setOperationAction(ISD::SRL, T, Custom);
161 setOperationAction(ISD::SRL, T, Custom);
735 SDValue WordIdx = DAG.getNode(ISD::SRL, dl, MVT::i32,
1550 case ISD::SRL:
1576 case ISD::SRL: return LowerHvxShift(Op, DAG);

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