Searched refs:SMULO (Results 1 - 16 of 16) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h258 SMULO, UMULO, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp296 case ISD::SMULO: return "smulo";
H A DLegalizeVectorOps.cpp452 case ISD::SMULO:
943 case ISD::SMULO:
H A DLegalizeIntegerTypes.cpp145 case ISD::SMULO:
1151 if (N->getOpcode() == ISD::SMULO) {
1916 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
3052 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
H A DLegalizeVectorTypes.cpp161 case ISD::SMULO:
956 case ISD::SMULO:
2767 case ISD::SMULO:
H A DTargetLowering.cpp7201 } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) {
7203 DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
7472 bool isSigned = Node->getOpcode() == ISD::SMULO;
H A DSelectionDAG.cpp2842 case ISD::SMULO:
3732 case ISD::SMULO:
9327 Opcode == ISD::UMULO || Opcode == ISD::SMULO) &&
H A DLegalizeDAG.cpp3499 case ISD::SMULO: {
H A DDAGCombiner.cpp1537 case ISD::SMULO:
4299 bool IsSigned = (ISD::SMULO == N->getOpcode());
H A DSelectionDAGBuilder.cpp6641 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp326 case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1675 setOperationAction(ISD::SMULO, MVT::i64, Custom);
2930 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2936 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2938 bool isSigned = (opcode == ISD::SMULO);
3057 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp669 setOperationAction(ISD::SMULO, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp381 setOperationAction(ISD::SMULO, MVT::i32, Custom);
382 setOperationAction(ISD::SMULO, MVT::i64, Custom);
2234 case ISD::SMULO:
2237 bool IsSigned = Op.getOpcode() == ISD::SMULO;
2340 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
3193 case ISD::SMULO:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4448 case ISD::SMULO:
5219 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5270 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1931 setOperationAction(ISD::SMULO, VT, Custom);
21988 case ISD::SMULO:
22278 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
22833 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
22886 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
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