Searched refs:S0 (Results 1 - 25 of 45) sorted by relevance

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/freebsd-11-stable/cddl/contrib/opensolaris/lib/libdtrace/common/
H A Ddt_lex.l91 * S0 - D program clause and expression lexing
104 %s S0 S1 S2 S3 S4
139 <S0>auto return (DT_KEY_AUTO);
140 <S0>break return (DT_KEY_BREAK);
141 <S0>case return (DT_KEY_CASE);
142 <S0>char return (DT_KEY_CHAR);
143 <S0>const return (DT_KEY_CONST);
144 <S0>continue return (DT_KEY_CONTINUE);
145 <S0>counter return (DT_KEY_COUNTER);
146 <S0>defaul
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/ADT/
H A DStringSwitch.h88 StringSwitch &Cases(StringLiteral S0, StringLiteral S1, T Value) { argument
89 return Case(S0, Value).Case(S1, Value);
92 StringSwitch &Cases(StringLiteral S0, StringLiteral S1, StringLiteral S2, argument
94 return Case(S0, Value).Cases(S1, S2, Value);
97 StringSwitch &Cases(StringLiteral S0, StringLiteral S1, StringLiteral S2, argument
99 return Case(S0, Value).Cases(S1, S2, S3, Value);
102 StringSwitch &Cases(StringLiteral S0, StringLiteral S1, StringLiteral S2, argument
104 return Case(S0, Value).Cases(S1, S2, S3, S4, Value);
107 StringSwitch &Cases(StringLiteral S0, StringLiteral S1, StringLiteral S2, argument
110 return Case(S0, Valu
113 Cases(StringLiteral S0, StringLiteral S1, StringLiteral S2, StringLiteral S3, StringLiteral S4, StringLiteral S5, StringLiteral S6, T Value) argument
119 Cases(StringLiteral S0, StringLiteral S1, StringLiteral S2, StringLiteral S3, StringLiteral S4, StringLiteral S5, StringLiteral S6, StringLiteral S7, T Value) argument
125 Cases(StringLiteral S0, StringLiteral S1, StringLiteral S2, StringLiteral S3, StringLiteral S4, StringLiteral S5, StringLiteral S6, StringLiteral S7, StringLiteral S8, T Value) argument
132 Cases(StringLiteral S0, StringLiteral S1, StringLiteral S2, StringLiteral S3, StringLiteral S4, StringLiteral S5, StringLiteral S6, StringLiteral S7, StringLiteral S8, StringLiteral S9, T Value) argument
161 CasesLower(StringLiteral S0, StringLiteral S1, T Value) argument
165 CasesLower(StringLiteral S0, StringLiteral S1, StringLiteral S2, T Value) argument
170 CasesLower(StringLiteral S0, StringLiteral S1, StringLiteral S2, StringLiteral S3, T Value) argument
175 CasesLower(StringLiteral S0, StringLiteral S1, StringLiteral S2, StringLiteral S3, StringLiteral S4, T Value) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DMergedLoadStoreMotion.cpp119 PHINode *getPHIOperand(BasicBlock *BB, StoreInst *S0, StoreInst *S1);
122 bool canSinkStoresAndGEPs(StoreInst *S0, StoreInst *S1) const;
208 /// Create a PHI node in BB for the operands of S0 and S1
210 PHINode *MergedLoadStoreMotion::getPHIOperand(BasicBlock *BB, StoreInst *S0, argument
213 Value *Opd1 = S0->getValueOperand();
220 NewPN->applyMergedLocation(S0->getDebugLoc(), S1->getDebugLoc());
221 NewPN->addIncoming(Opd1, S0->getParent());
229 bool MergedLoadStoreMotion::canSinkStoresAndGEPs(StoreInst *S0, argument
231 auto *A0 = dyn_cast<Instruction>(S0->getPointerOperand());
234 (A0->getParent() == S0
243 sinkStoresAndGEPs(BasicBlock *BB, StoreInst *S0, StoreInst *S1) argument
314 auto *S0 = dyn_cast<StoreInst>(I); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16FrameLowering.cpp87 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
105 .addReg(Mips::S0);
120 // Registers RA, S0,S1 are the callee saved registers and they
145 // Registers RA,S0,S1 are the callee saved registers and they will be restored
174 SavedRegs.set(Mips::S0);
H A DMips16RegisterInfo.cpp106 FrameReg = Mips::S0;
H A DMipsRegisterInfo.cpp193 Reserved.set(Mips::S0);
288 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
H A DMicroMipsSizeReduction.cpp382 Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
576 Reg == Mips::S0 || Reg == Mips::S1 || Reg == Mips::S2 ||
/freebsd-11-stable/lib/libc/mips/gen/
H A Dmakecontext.c86 mc->mc_regs[S0] = (intptr_t)ucp;
/freebsd-11-stable/sys/dev/patm/
H A Didt77252reg.h107 #define IDT_MKCMD_RUTIL(S0, S1, A) \
108 (IDT_CMD_RUTIL | ((S1) << 9) | ((S0) << 8) | (A))
109 #define IDT_MKCMD_WUTIL(S0, S1, A) \
110 (IDT_CMD_WUTIL | ((S1) << 9) | ((S0) << 8) | (A))
/freebsd-11-stable/sys/mips/include/
H A Dregnum.h81 #define S0 16 macro
/freebsd-11-stable/crypto/openssl/crypto/sha/asm/
H A Dsha512p8-ppc.pl83 ($Ki,$Func,$S0,$S1,$s0,$s1,$lemask)=map("v$_",(24..31));
104 vshasigma${sz} $S0,$a,1,0 ; Sigma0(a)
113 vaddu${sz}m $S0,$S0,$Func ; Sigma0(a)+Maj(a,b,c)
117 vaddu${sz}m $h,$h,$S0 ; h+=Sigma0(a)+Maj(a,b,c)
/freebsd-11-stable/sys/crypto/sha2/
H A Dsha256c.c106 #define S0(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) macro
115 h += S0(a) + Maj(a, b, c);
H A Dsha512c.c133 #define S0(x) (ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39)) macro
142 h += S0(a) + Maj(a, b, c);
/freebsd-11-stable/crypto/heimdal/appl/ftp/ftp/
H A Dmain.c434 S0:
442 sb++; goto S0;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoadStoreVectorizer.cpp942 StoreInst *S0 = cast<StoreInst>(Chain[0]); local
960 unsigned AS = S0->getPointerAddressSpace();
964 unsigned Alignment = getAlignment(S0);
1023 if (S0->getPointerAddressSpace() != DL.getAllocaAddrSpace()) {
1029 unsigned NewAlign = getOrEnforceKnownAlignment(S0->getPointerOperand(),
1031 DL, S0, nullptr, &DT);
1080 Builder.CreateBitCast(S0->getPointerOperand(), VecTy->getPointerTo(AS)),
/freebsd-11-stable/usr.sbin/moused/
H A Dmoused.c466 #define S0 0 /* start */ macro
487 /* S0 */
488 { { S0, S2, S1, S3, S0 }, 0, ~(MOUSE_BUTTON1DOWN | MOUSE_BUTTON3DOWN), FALSE },
494 { { S0, S9, S9, S3, S3 }, MOUSE_BUTTON2DOWN, ~0, FALSE },
496 { { S0, S2, S1, S3, S0 }, MOUSE_BUTTON1DOWN, ~0, TRUE },
498 { { S0, S2, S5, S7, S5 }, MOUSE_BUTTON1DOWN, ~0, FALSE },
500 { { S0, S6, S1, S7, S6 }, MOUSE_BUTTON3DOWN, ~0, FALSE },
502 { { S0, S
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp272 SUnit &S0 = DAG->SUnits[i]; local
273 MachineInstr &L0 = *S0.getInstr();
302 SDep A(&S0, SDep::Artificial);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
H A DAArch64PBQPRegAlloc.cpp96 case AArch64::S0:
/freebsd-11-stable/sys/mips/mips/
H A Dexception.S296 SAVE_REG(s0, S0, sp) ;\
356 RESTORE_REG(s0, S0, sp) ;\
455 SAVE_U_PCB_REG(s0, S0, k1)
548 RESTORE_U_PCB_REG(s0, S0, k1)
721 SAVE_U_PCB_REG(s0, S0, k1)
803 RESTORE_U_PCB_REG(s0, S0, k1)
H A Dswtch.S117 RESTORE_U_PCB_REG(s0, S0, k1)
/freebsd-11-stable/contrib/tnftp/src/
H A Dmain.c847 S0:
856 goto S0;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp158 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
/freebsd-11-stable/sys/compat/svr4/
H A Dsvr4_termios.c302 undefined_flag2(c_oflag,B,SDLY,B,S0,B,S1);
402 undefined_flag2(c_oflag,B,SDLY,B,S0,B,S1);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp131 {codeview::RegisterId::ARM64_S0, AArch64::S0},

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