1/*- 2 * Copyright (c) 2003 3 * Fraunhofer Institute for Open Communication Systems (FhG Fokus). 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Author: Hartmut Brandt <harti@freebsd.org> 28 * 29 * $FreeBSD$ 30 * 31 * Register definitions for the IDT77252 chip. 32 */ 33 34#define PCI_VENDOR_IDT 0x111D 35#define PCI_DEVICE_IDT77252 3 36#define PCI_DEVICE_IDT77v252 4 37#define PCI_DEVICE_IDT77v222 5 38 39#define IDT_PCI_REG_MEMBASE 0x14 40 41#define IDT_NOR_D0 0x00 /* R/W Data register 0 */ 42#define IDT_NOR_D1 0x04 /* R/W Data register 1 */ 43#define IDT_NOR_D2 0x08 /* R/W Data register 2 */ 44#define IDT_NOR_D3 0x0C /* R/W Data register 3 */ 45#define IDT_NOR_CMD 0x10 /* R/W Command */ 46#define IDT_NOR_CFG 0x14 /* R/W Configuration */ 47#define IDT_NOR_STAT 0x18 /* R/W Status */ 48#define IDT_NOR_RSQB 0x1C /* R/W Receive status queue base */ 49#define IDT_NOR_RSQT 0x20 /* R Receive status queue tail */ 50#define IDT_NOR_RSQH 0x24 /* R/W Receive status queue tail */ 51#define IDT_NOR_CDC 0x28 /* R/W Cell drop counter */ 52#define IDT_NOR_VPEC 0x2C /* R/W VPI/VCI Lookup error counter */ 53#define IDT_NOR_ICC 0x30 /* R/W Invalid cell counter */ 54#define IDT_NOR_RAWCT 0x34 /* R Raw cell tail */ 55#define IDT_NOR_TMR 0x38 /* R Timer */ 56#define IDT_NOR_TSTB 0x3C /* R/W Transmit schedule table base */ 57#define IDT_NOR_TSQB 0x40 /* R/W Transmit Status queue base */ 58#define IDT_NOR_TSQT 0x44 /* R/W Transmit Status queue tail */ 59#define IDT_NOR_TSQH 0x48 /* R/W Transmit Status queue head */ 60#define IDT_NOR_GP 0x4C /* R/W General purpose */ 61#define IDT_NOR_VPM 0x50 /* R/W VPI/VCI mask */ 62#define IDT_NOR_RXFD 0x54 /* R/W Receive FIFO descriptor */ 63#define IDT_NOR_RXFT 0x58 /* R/W Receive FIFO tail */ 64#define IDT_NOR_RXFH 0x5C /* R/W Receive FIFO head */ 65#define IDT_NOR_RAWHND 0x60 /* R/W Raw cell handle */ 66#define IDT_NOR_RXSTAT 0x64 /* R Receive connection state */ 67#define IDT_NOR_ABRSTD 0x68 /* R/W ABR & VBR Schedule table descriptor */ 68#define IDT_NOR_ABRRQ 0x6C /* R/W ABR Ready queue pointer */ 69#define IDT_NOR_VBRRQ 0x70 /* R/W VBR Ready queue pointer */ 70#define IDT_NOR_RTBL 0x74 /* R/W Rate table descriptor */ 71#define IDT_NOR_MXDFCT 0x78 /* R/W Maximum deficit counter */ 72#define IDT_NOR_TXSTAT 0x7C /* R/W Transmit connection state */ 73#define IDT_NOR_TCMDQ 0x80 /* W Transmit command queue */ 74#define IDT_NOR_IRCP 0x84 /* R/W Inactive receive connection pointer */ 75#define IDT_NOR_FBQP0 0x88 /* R/W Free buffer queue 0 pointer */ 76#define IDT_NOR_FBQP1 0x8C /* R/W Free buffer queue 1 pointer */ 77#define IDT_NOR_FBQP2 0x90 /* R/W Free buffer queue 2 pointer */ 78#define IDT_NOR_FBQP3 0x94 /* R/W Free buffer queue 3 pointer */ 79#define IDT_NOR_FBQS0 0x98 /* R/W Free buffer queue 0 size */ 80#define IDT_NOR_FBQS1 0x9C /* R/W Free buffer queue 1 size */ 81#define IDT_NOR_FBQS2 0xA0 /* R/W Free buffer queue 2 size */ 82#define IDT_NOR_FBQS3 0xA4 /* R/W Free buffer queue 3 size */ 83#define IDT_NOR_FBQWP0 0xA8 /* R/W Free buffer queue 0 write pointer */ 84#define IDT_NOR_FBQWP1 0xAC /* R/W Free buffer queue 1 write pointer */ 85#define IDT_NOR_FBQWP2 0xB0 /* R/W Free buffer queue 2 write pointer */ 86#define IDT_NOR_FBQWP3 0xB4 /* R/W Free buffer queue 3 write pointer */ 87#define IDT_NOR_NOW 0xB8 /* R Current transmit schedule table addr */ 88#define IDT_NOR_DNOW 0xBC /* R Dynamic Now register */ 89#define IDT_NOR_END 0xC0 90 91/* 92 * Command (IDT_NOR_CMD) 93 */ 94#define IDT_CMD_NOP 0x00000000 /* No operation */ 95#define IDT_CMD_OPCL 0x20000000 /* Open/Close connection */ 96#define IDT_CMD_WSRAM 0x40000000 /* Write SRAM */ 97#define IDT_CMD_RSRAM 0x50000000 /* Read SRAM */ 98#define IDT_CMD_WFBQ 0x60000000 /* Write free buffer queue */ 99#define IDT_CMD_RUTIL 0x80000000 /* Read utility bus */ 100#define IDT_CMD_WUTIL 0x90000000 /* Write utility bus */ 101 102#define IDT_MKCMD_OPEN(VC) (IDT_CMD_OPCL | (1 << 19) | ((V) << 4)) 103#define IDT_MKCMD_CLOSE(VC) (IDT_CMD_OPCL | (0 << 19) | ((V) << 4)) 104#define IDT_MKCMD_WSRAM(A, S) (IDT_CMD_WSRAM | ((A) << 2) | (S)) 105#define IDT_MKCMD_RSRAM(A) (IDT_CMD_RSRAM | ((A) << 2)) 106#define IDT_MKCMD_WFBQ(Q) (IDT_CMD_WFBQ | (Q)) 107#define IDT_MKCMD_RUTIL(S0, S1, A) \ 108 (IDT_CMD_RUTIL | ((S1) << 9) | ((S0) << 8) | (A)) 109#define IDT_MKCMD_WUTIL(S0, S1, A) \ 110 (IDT_CMD_WUTIL | ((S1) << 9) | ((S0) << 8) | (A)) 111 112/* 113 * Configuration register (CFG) 114 */ 115#define IDT_CFG_SWRST 0x80000000 /* software reset */ 116#define IDT_CFG_LOOP 0x40000000 /* internal loopback enable */ 117#define IDT_CFG_RXPTH 0x20000000 /* receive path enable */ 118#define IDT_CFG_IDLECLP 0x10000000 /* set CLP in null cells */ 119#define IDT_CFG_TXFIFO9 0x00000000 /* Tx FIFO 9 cells */ 120#define IDT_CFG_TXFIFO1 0x04000000 /* Tx FIFO 1 cells */ 121#define IDT_CFG_TXFIFO2 0x08000000 /* Tx FIFO 2 cells */ 122#define IDT_CFG_TXFIFO4 0x0C000000 /* Tx FIFO 4 cells */ 123#define IDT_CFG_NOIDLE 0x02000000 /* don't send idle cells */ 124#define IDT_CFG_RXQ128 0x00000000 /* Rx Status Queue 128 entries */ 125#define IDT_CFG_RXQ256 0x00400000 /* Rx Status Queue 256 entries */ 126#define IDT_CFG_RXQ512 0x00800000 /* Rx Status Queue 512 entries */ 127#define IDT_CFG_ICAPT 0x00200000 /* Invalid cell accept */ 128#define IDT_CFG_IGGFC 0x00100000 /* Ignore GFC field */ 129#define IDT_CFG_VP0 0x00000000 /* 0 VPI bits */ 130#define IDT_CFG_VP1 0x00040000 /* 1 VPI bit */ 131#define IDT_CFG_VP2 0x00080000 /* 2 VPI bits */ 132#define IDT_CFG_VP8 0x000C0000 /* 8 VPI bits */ 133#define IDT_CFG_CTS1K 0x00000000 /* Rx Connection table 1024 entries */ 134#define IDT_CFG_CTS4K 0x00010000 /* Rx Connection table 4096 entries */ 135#define IDT_CFG_CTS16K 0x00020000 /* Rx Connection table 16384 entries */ 136#define IDT_CFG_CTS512 0x00030000 /* Rx Connection table 512 entries */ 137#define IDT_CFG_VPECA 0x00008000 /* VPI/VCI error cell accept */ 138#define IDT_CFG_RXINONE 0x00000000 /* No interrupt on receive */ 139#define IDT_CFG_RXIIMM 0x00001000 /* immediate interrupt */ 140#define IDT_CFG_RXI28 0x00002000 /* every 0x2800 clocks */ 141#define IDT_CFG_RXI4F 0x00003000 /* every 0x4F00 clocks */ 142#define IDT_CFG_RXI74 0x00004000 /* every 0x7400 clocks */ 143#define IDT_CFG_RAWIE 0x00000800 /* raw cell queue interrupt enable */ 144#define IDT_CFG_RQFIE 0x00000400 /* Rx status queue almost full IE */ 145#define IDT_CFG_CACHE 0x00000100 /* begin DMA on cache line */ 146#define IDT_CFG_TIMOIE 0x00000080 /* timer roll over interrupt enable */ 147#define IDT_CFG_FBIE 0x00000040 /* free buffer queue interrupt enable */ 148#define IDT_CFG_TXENB 0x00000020 /* Tx enable */ 149#define IDT_CFG_TXINT 0x00000010 /* Tx status interrupt enable */ 150#define IDT_CFG_TXUIE 0x00000008 /* Tx underrun interrupt enable */ 151#define IDT_CFG_UMODE 0x00000004 /* utopia byte mode */ 152#define IDT_CFG_TXSFI 0x00000002 /* Tx status full interrupt enable */ 153#define IDT_CFG_PHYIE 0x00000001 /* PHY interrupt enable */ 154 155/* 156 * Status register (STAT) 157 */ 158#define IDT_STAT_FRAC3(S) (((S) >> 28) & 0xf) /* FBQ3 valid */ 159#define IDT_STAT_FRAC2(S) (((S) >> 24) & 0xf) /* FBQ2 valid */ 160#define IDT_STAT_FRAC1(S) (((S) >> 20) & 0xf) /* FBQ1 valid */ 161#define IDT_STAT_FRAC0(S) (((S) >> 16) & 0xf) /* FBQ0 valid */ 162#define IDT_STAT_TSIF 0x00008000 /* Tx status indicator flag */ 163#define IDT_STAT_TXICP 0x00004000 /* Tx incomplete PDU */ 164#define IDT_STAT_TSQF 0x00001000 /* Tx status queue full */ 165#define IDT_STAT_TMROF 0x00000800 /* Timer overflow */ 166#define IDT_STAT_PHYI 0x00000400 /* PHY interrupt */ 167#define IDT_STAT_CMDBZ 0x00000200 /* command busy */ 168#define IDT_STAT_FBQ3A 0x00000100 /* FBQ 3 attention flag */ 169#define IDT_STAT_FBQ2A 0x00000080 /* FBQ 2 attention flag */ 170#define IDT_STAT_RSQF 0x00000040 /* Rx status queue full */ 171#define IDT_STAT_EPDU 0x00000020 /* end of CS-PDU */ 172#define IDT_STAT_RAWCF 0x00000010 /* raw cell flag */ 173#define IDT_STAT_FBQ1A 0x00000008 /* FBQ 1 attention flag */ 174#define IDT_STAT_FBQ0A 0x00000004 /* FBQ 0 attention flag */ 175#define IDT_STAT_RSQAF 0x00000002 /* Rx status queue almost full */ 176 177/* 178 * Cell drop count (CDC) 179 */ 180#define IDT_CDC_RMID 0x00400000 /* RM cell ID error */ 181#define IDT_CDC_CTE 0x00200000 /* Rx connection table error */ 182#define IDT_CDC_NFB 0x00100000 /* No free buffers */ 183#define IDT_CDC_OAMCRC 0x00080000 /* bad OAM CRC */ 184#define IDT_CDC_RMCRC 0x00040000 /* bad RM CRC */ 185#define IDT_CDC_RMFIFO 0x00020000 /* RM FIFO full */ 186#define IDT_CDC_RXFIFO 0x00010000 /* Rx FIFO full */ 187#define IDT_CDC(S) ((S) & 0xffff) /* cell drop counter */ 188 189/* 190 * VPI/VCI lookup error count (VPEC) 191 */ 192#define IDT_VPEC(S) ((S) & 0xffff) 193 194/* 195 * Invalid cell count (ICC) 196 */ 197#define IDT_ICC(S) ((S) & 0xffff) 198 199/* 200 * General purpose register 201 */ 202#define IDT_GP_TXNCC(S) (((S) >> 24) & 0xff) /* Tx negative cell count */ 203#define IDT_GP_EEDI 0x00010000 /* EEPROM data in */ 204#define IDT_GP_BIGE 0x00008000 /* big endian enable */ 205#define IDT_GP_RM 0x00000000 /* process RM cells */ 206#define IDT_GP_RM_TEE 0x00002000 /* process RM cells and put in RawQ */ 207#define IDT_GP_RM_RAW 0x00006000 /* put RM cells in RawQ */ 208#define IDT_GP_DLOOP 0x00001000 /* double loopback */ 209#define IDT_GP_PCIPAR 0x00000010 /* force PCI parity error */ 210#define IDT_GP_PCIPERR 0x00000020 /* force PERR */ 211#define IDT_GP_PCISERR 0x00000040 /* force SERR */ 212#define IDT_GP_PHY_RST 0x00000008 /* PHY reset */ 213#define IDT_GP_EESCLK 0x00000004 /* EEPROM clock */ 214#define IDT_GP_EECS 0x00000002 /* EEPROM chip select */ 215#define IDT_GP_EEDO 0x00000001 /* EEPROM data out */ 216 217/* 218 * Receive FIFO descriptor register (RXFD) 219 */ 220#define IDT_RXFD(A, S) (((S) << 24) | ((A) << 2)) 221#define IDT_RXFDS(V) (((V) >> 24) & 0xf) 222#define IDT_RXFDA(V) (((V) & 0x1ffffc) >> 2) 223 224/* 225 * ABR & VBR schedule table descriptor register 226 */ 227#define IDT_ABRSTD(A, S) (((S) << 24) | ((A) << 2)) 228#define IDT_ABRSTDS(V) (((V) >> 24) & 0x7) 229#define IDT_ABRSTDA(V) (((V) & 0x1ffffc) >> 2) 230 231/* 232 * ABR/VBR ready queue register 233 */ 234#define IDT_ABRRQH(V) (((V) >> 16) & 0x3fff) 235#define IDT_ABRRQT(V) (((V) >> 0) & 0x3fff) 236#define IDT_VBRRQH(V) (((V) >> 16) & 0x3fff) 237#define IDT_VBRRQT(V) (((V) >> 0) & 0x3fff) 238 239/* 240 * Maximum deficit limit register 241 */ 242#define IDT_MDFCT_LCI 0x00020000 /* local congestion indicator enable */ 243#define IDT_MDFCT_LNI 0x00010000 /* local no incread enable */ 244 245/* 246 * Transmit command queue register 247 */ 248#define IDT_TCMDQ_NOP() ((0x0 << 24)) /* no operation */ 249#define IDT_TCMDQ_START(C) ((0x1 << 24) | (C)) /* start connection */ 250#define IDT_TCMDQ_ULACR(C, L) ((0x2 << 24) | (C) | ((L) << 16)) 251 /* update LACR */ 252#define IDT_TCMDQ_SLACR(C, L) ((0x3 << 24) | (C) | ((L) << 16)) 253 /* start and update LACR */ 254#define IDT_TCMDQ_UIER(C, L) ((0x4 << 24) | (C) | ((L) << 16)) 255 /* update Int ER */ 256#define IDT_TCMDQ_HALT(C) ((0x5 << 24) | (C)) /* halt connection */ 257 258/* 259 * Free buffer queue size registers 260 */ 261#define IDT_FBQS(T, N, C, S) (((T) << 28) | ((N) << 24) | ((C) << 20) | (S)) 262 263/* 264 * Receive status queue 265 */ 266struct idt_rsqe { 267 uint32_t cid; /* VPI/VCI */ 268 uint32_t handle; /* buffer handle */ 269 uint32_t crc; /* AAL-5 CRC */ 270 uint32_t stat; /* div. flags */ 271}; 272#define IDT_RSQE_SIZE 16 /* bytes */ 273#define IDT_RSQE_VPI(CID) (((CID) >> 16) & 0xff) 274#define IDT_RSQE_VCI(CID) ((CID) & 0xffff) 275#define IDT_RSQE_TYPE(S) (((S) >> 30) & 0x3) 276#define IDT_RSQE_DATA 0x2 277#define IDT_RSQE_IDLE 0x3 278#define IDT_RSQE_VALID 0x80000000 279#define IDT_RSQE_POOL(S) (((S) >> 16) & 0x3) 280#define IDT_RSQE_BUF 0x8000 281#define IDT_RSQE_NZGFC 0x4000 282#define IDT_RSQE_EPDU 0x2000 283#define IDT_RSQE_CBUF 0x1000 284#define IDT_RSQE_EFCIE 0x0800 285#define IDT_RSQE_CLP 0x0400 286#define IDT_RSQE_CRC 0x0200 287#define IDT_RSQE_CNT(S) ((S) & 0x1ff) 288 289#define IDT_RSQH(R) (((R) & 0x1ffc) >> 2) 290#define IDT_RSQT(R) (((R) & 0x1ffc) >> 2) 291 292/* 293 * Transmit status queue 294 */ 295#define IDT_TSQ_SIZE 1024 /* no. of entries */ 296#define IDT_TSQE_SIZE 8 /* bytes */ 297#define IDT_TSQE_SHIFT 3 298struct idt_tsqe { 299 uint32_t stat; 300 uint32_t stamp; 301}; 302#define IDT_TSQE_EMPTY 0x80000000 303#define IDT_TSQE_TYPE(E) (((E) >> 29) & 0x3) 304#define IDT_TSQE_TIMER 0x0 305#define IDT_TSQE_TSR 0x1 306#define IDT_TSQE_IDLE 0x2 307#define IDT_TSQE_TBD 0x3 308#define IDT_TSQE_TAG(E) (((E) >> 24) & 0x1f) 309#define IDT_TSQE_HALTED 0x10 310#define IDT_TSQE_STAMP(E) ((E) & 0xffffff) 311#define IDT_TSQE_TAG_SPACE 32 312 313/* 314 * Raw cell handle 315 */ 316struct idt_rawhnd { 317 uint32_t tail; 318 uint32_t handle; 319}; 320#define IDT_RAWHND_SIZE 8 321 322/* 323 * TST 324 */ 325#define IDT_TST_NULL (0 << 29) /* transmit NULL cell */ 326#define IDT_TST_CBR (1 << 29) /* transmit CBR cell */ 327#define IDT_TST_VBR (2 << 29) /* transmit [AVU]BR cell */ 328#define IDT_TST_BR (3 << 29) /* branch */ 329#define IDT_TST_MASK 0x7ffff 330 331/* 332 * Free buffer queue 333 */ 334#define IDT_FBQ_SIZE 512 /* entries */ 335 336/* 337 * Receive connection table 338 */ 339#define IDT_RCT_FBP2 0x00400000 /* use FBQ 2 */ 340#define IDT_RCT_OPEN 0x00080000 /* connection open */ 341#define IDT_RCT_AAL0 0x00000000 /* AAL 0 */ 342#define IDT_RCT_AAL34 0x00010000 /* AAL 3/4 */ 343#define IDT_RCT_AAL5 0x00020000 /* AAL 5 */ 344#define IDT_RCT_AALRAW 0x00030000 /* raw cells */ 345#define IDT_RCT_AALOAM 0x00040000 /* OAM cells */ 346#define IDT_RCT_RCI 0x00008000 /* raw cell interrupt enable */ 347#define IDT_RCT_IACT_CNT_MASK 0x1c000000 348#define IDT_RCT_IACT_CNT_SHIFT 26 349#define IDT_RCT_ENTRY_SIZE 4 /* words */ 350 351/* 352 * Transmit connection table 353 */ 354#define IDT_TCT_CBR 0x00000000 355#define IDT_TCT_VBR 0x40000000 356#define IDT_TCT_ABR 0x80000000 357#define IDT_TCT_UBR 0x00000000 358#define IDT_TCT_UBR_FLG 0x80000000 /* word8 flag */ 359#define IDT_TCT_HALT 0x80000000 /* connection halted */ 360#define IDT_TCT_IDLE 0x40000000 /* connection idle */ 361#define IDT_TCT_TSIF 0x00004000 362#define IDT_TCT_MAXIDLE 0x7f000000 363#define IDT_TCT_MBS_SHIFT 16 364#define IDT_TCT_CRM_SHIFT 29 365#define IDT_TCT_NAGE_SHIFT 21 366#define IDT_TCT_LMCR_SHIFT 24 367#define IDT_TCT_CDF_SHIFT 20 368#define IDT_TCT_RDF_SHIFT 14 369#define IDT_TCT_AIR_SHIFT 8 370#define IDT_TCT_ACRI_SHIFT 16 371 372/* 373 * Segmentation channel queue 374 */ 375#define IDT_SCQ_SIZE 64 /* number of entries */ 376struct idt_tbd { 377 uint32_t flags; 378 uint32_t addr; 379 uint32_t aal5; 380 uint32_t hdr; 381}; 382#define IDT_TBD_SIZE 16 /* bytes */ 383#define IDT_TBD_SHIFT 4 384#define IDT_TBD_TSR 0x80000000 /* TSR entry */ 385#define IDT_TBD_EPDU 0x40000000 /* end of AAL PDU */ 386#define IDT_TBD_TSIF 0x20000000 /* generate status */ 387#define IDT_TBD_AAL0 0x00000000 /* AAL0 */ 388#define IDT_TBD_AAL34 0x04000000 /* AAL3/4 */ 389#define IDT_TBD_AAL5 0x08000000 /* AAL5 */ 390#define IDT_TBD_AALOAM 0x10000000 /* OAM cells */ 391#define IDT_TBD_GTSI 0x02000000 /* generate transmit status entry */ 392#define IDT_TBD_TAG_SHIFT 20 393#define IDT_TBD_HDR(VPI, VCI, PTI, CLP) \ 394 (((VPI) << 20) | ((VCI) << 4) | ((PTI) << 1) | (CLP)) 395#define IDT_TBD_VPI(H) (((H) >> 20) & 0xff) 396#define IDT_TBD_VCI(H) (((H) >> 4) & 0xffff) 397 398/* 399 * Segmentation channel descriptor 400 */ 401#define IDT_SCD_SIZE 12 /* words */ 402 403/* 404 * Memory map for the different RAM sizes 405 * 406 * 16k 32k 128k 512k 407 * 408 * TxCT 0x00000/4k 0x00000/8x 0x00000/32k 0x00000/128k 409 * RxCT 0x01000/2k 0x02000/4k 0x08000/16k 0x20000/64k 410 * FBQ0 0x01800/1k 0x03000/1k 0x0c000/1k 0x30000/1k 411 * FBQ1 0x01c00/1k 0x03400/1k 0x0c400/1k 0x30400/1k 412 * FBQ2 0x02000/1k 0x03800/1k 0x0c800/1k 0x30800/1k 413 * FBQ3 - - - - 414 * RT 0x02400/4.5k 0x03c00/4.5k 0x0cc00/4.5k 0x30c00/4.5k 415 * SCD 0x03600/597 0x04e00/1621 0x0de00/9358 0x31e00/43036 416 * TST 0x06000/2x2k 0x0c000/2x4k 0x37000/2x8k 0xef000/2x16k 417 * ABR ST 0x07000/2x1k 0x0e000/2x2k 0x3b000/2x8k 0xf7000/2x16k 418 * RxFIFO 0x07800/2k 0x0f000/4k 0x3f000/4k 0xff000/4k 419 * End 0x08000 0x10000 0x40000 0x100000 420 */ 421struct idt_mmap { 422 u_int sram; /* K SRAM */ 423 u_int max_conn; /* connections */ 424 u_int vcbits; /* VPI + VCI bits */ 425 u_int rxtab; /* CFG word for CNTBL field */ 426 u_int rct; /* RCT base */ 427 u_int rtables; /* rate table address */ 428 u_int scd_base; /* SCD area base address */ 429 u_int scd_num; /* number of SCDs */ 430 u_int tst1base; /* base address of TST 1 */ 431 u_int tst_size; /* TST size in words */ 432 u_int abrstd_addr; /* schedule table address */ 433 u_int abrstd_size; /* schedule table size */ 434 u_int abrstd_code; /* schedule table size */ 435 u_int rxfifo_addr; /* address */ 436 u_int rxfifo_size; /* in words */ 437 u_int rxfifo_code; /* size */ 438}; 439#define IDT_MMAP { \ 440 { /* 16k x 32, 512 connections */ \ 441 16, 512, 9, IDT_CFG_CTS512, /* RAM, connections, VC bits */ \ 442 0x01000, /* RCT base */ \ 443 0x02400, /* rate table address */ \ 444 0x03600, 597, /* SCD base and num */ \ 445 0x06000, 2048, /* TST/words, base */ \ 446 0x07000, 2048, 0x1, /* ABR schedule table */ \ 447 0x07800, 2048, 0x2 /* RxFIFO size in words */ \ 448 }, \ 449 { /* 32k x 32, 1024 connections */ \ 450 32, 1024, 10, IDT_CFG_CTS1K, /* RAM, connections, VC bits */ \ 451 0x02000, /* RCT base */ \ 452 0x03c00, /* rate table address */ \ 453 0x04e00, 1621, /* SCD base and num */ \ 454 0x0c000, 4096, /* TST/words, base */ \ 455 0x0e000, 4096, 0x2, /* ABR schedule table */ \ 456 0x0f000, 4096, 0x3 /* RxFIFO size in words */ \ 457 }, \ 458 { /* 128k x 32, 4096 connections */ \ 459 128, 4096, 12, IDT_CFG_CTS4K, /* RAM, connections, VC bits */ \ 460 0x08000, /* RCT base */ \ 461 0x0cc00, /* rate table address */ \ 462 0x0de00, 9358, /* SCD base and num */ \ 463 0x37000, 8192, /* TST/words, base */ \ 464 0x3b000, 16384, 0x4, /* ABR schedule table */ \ 465 0x3f000, 4096, 0x3 /* RxFIFO size in words */ \ 466 }, \ 467 { /* 512k x 32, 512 connections */ \ 468 512, 16384, 14, IDT_CFG_CTS16K, /* RAM, connections, VC bits */\ 469 0x20000, /* RCT base */ \ 470 0x30c00, /* rate table address */ \ 471 0x31e00, 43036, /* SCD base and num */ \ 472 0xef000, 16384, /* TST/words, base */ \ 473 0xf7000, 16384, 0x5, /* ABR schedule table */ \ 474 0xff000, 4096, 0x3 /* RxFIFO size in words */ \ 475 }, \ 476} 477