1276479Sdim//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===// 2249259Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6249259Sdim// 7249259Sdim//===----------------------------------------------------------------------===// 8249259Sdim// 9249259Sdim// This file provides AArch64 specific target descriptions. 10249259Sdim// 11249259Sdim//===----------------------------------------------------------------------===// 12249259Sdim 13249259Sdim#include "AArch64MCTargetDesc.h" 14249259Sdim#include "AArch64ELFStreamer.h" 15249259Sdim#include "AArch64MCAsmInfo.h" 16321369Sdim#include "AArch64WinCOFFStreamer.h" 17344779Sdim#include "MCTargetDesc/AArch64AddressingModes.h" 18353358Sdim#include "MCTargetDesc/AArch64InstPrinter.h" 19353358Sdim#include "TargetInfo/AArch64TargetInfo.h" 20353358Sdim#include "llvm/DebugInfo/CodeView/CodeView.h" 21327952Sdim#include "llvm/MC/MCAsmBackend.h" 22327952Sdim#include "llvm/MC/MCCodeEmitter.h" 23314564Sdim#include "llvm/MC/MCInstrAnalysis.h" 24249259Sdim#include "llvm/MC/MCInstrInfo.h" 25341825Sdim#include "llvm/MC/MCObjectWriter.h" 26249259Sdim#include "llvm/MC/MCRegisterInfo.h" 27249259Sdim#include "llvm/MC/MCStreamer.h" 28249259Sdim#include "llvm/MC/MCSubtargetInfo.h" 29344779Sdim#include "llvm/Support/Endian.h" 30276479Sdim#include "llvm/Support/ErrorHandling.h" 31249259Sdim#include "llvm/Support/TargetRegistry.h" 32249259Sdim 33276479Sdimusing namespace llvm; 34249259Sdim 35249259Sdim#define GET_INSTRINFO_MC_DESC 36344779Sdim#define GET_INSTRINFO_MC_HELPERS 37249259Sdim#include "AArch64GenInstrInfo.inc" 38249259Sdim 39249259Sdim#define GET_SUBTARGETINFO_MC_DESC 40249259Sdim#include "AArch64GenSubtargetInfo.inc" 41249259Sdim 42276479Sdim#define GET_REGINFO_MC_DESC 43276479Sdim#include "AArch64GenRegisterInfo.inc" 44249259Sdim 45276479Sdimstatic MCInstrInfo *createAArch64MCInstrInfo() { 46276479Sdim MCInstrInfo *X = new MCInstrInfo(); 47276479Sdim InitAArch64MCInstrInfo(X); 48249259Sdim return X; 49249259Sdim} 50249259Sdim 51276479Sdimstatic MCSubtargetInfo * 52288943SdimcreateAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 53276479Sdim if (CPU.empty()) 54276479Sdim CPU = "generic"; 55276479Sdim 56288943Sdim return createAArch64MCSubtargetInfoImpl(TT, CPU, FS); 57249259Sdim} 58249259Sdim 59327952Sdimvoid AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { 60353358Sdim // Mapping from CodeView to MC register id. 61353358Sdim static const struct { 62353358Sdim codeview::RegisterId CVReg; 63353358Sdim MCPhysReg Reg; 64353358Sdim } RegMap[] = { 65353358Sdim {codeview::RegisterId::ARM64_W0, AArch64::W0}, 66353358Sdim {codeview::RegisterId::ARM64_W1, AArch64::W1}, 67353358Sdim {codeview::RegisterId::ARM64_W2, AArch64::W2}, 68353358Sdim {codeview::RegisterId::ARM64_W3, AArch64::W3}, 69353358Sdim {codeview::RegisterId::ARM64_W4, AArch64::W4}, 70353358Sdim {codeview::RegisterId::ARM64_W5, AArch64::W5}, 71353358Sdim {codeview::RegisterId::ARM64_W6, AArch64::W6}, 72353358Sdim {codeview::RegisterId::ARM64_W7, AArch64::W7}, 73353358Sdim {codeview::RegisterId::ARM64_W8, AArch64::W8}, 74353358Sdim {codeview::RegisterId::ARM64_W9, AArch64::W9}, 75353358Sdim {codeview::RegisterId::ARM64_W10, AArch64::W10}, 76353358Sdim {codeview::RegisterId::ARM64_W11, AArch64::W11}, 77353358Sdim {codeview::RegisterId::ARM64_W12, AArch64::W12}, 78353358Sdim {codeview::RegisterId::ARM64_W13, AArch64::W13}, 79353358Sdim {codeview::RegisterId::ARM64_W14, AArch64::W14}, 80353358Sdim {codeview::RegisterId::ARM64_W15, AArch64::W15}, 81353358Sdim {codeview::RegisterId::ARM64_W16, AArch64::W16}, 82353358Sdim {codeview::RegisterId::ARM64_W17, AArch64::W17}, 83353358Sdim {codeview::RegisterId::ARM64_W18, AArch64::W18}, 84353358Sdim {codeview::RegisterId::ARM64_W19, AArch64::W19}, 85353358Sdim {codeview::RegisterId::ARM64_W20, AArch64::W20}, 86353358Sdim {codeview::RegisterId::ARM64_W21, AArch64::W21}, 87353358Sdim {codeview::RegisterId::ARM64_W22, AArch64::W22}, 88353358Sdim {codeview::RegisterId::ARM64_W23, AArch64::W23}, 89353358Sdim {codeview::RegisterId::ARM64_W24, AArch64::W24}, 90353358Sdim {codeview::RegisterId::ARM64_W25, AArch64::W25}, 91353358Sdim {codeview::RegisterId::ARM64_W26, AArch64::W26}, 92353358Sdim {codeview::RegisterId::ARM64_W27, AArch64::W27}, 93353358Sdim {codeview::RegisterId::ARM64_W28, AArch64::W28}, 94353358Sdim {codeview::RegisterId::ARM64_W29, AArch64::W29}, 95353358Sdim {codeview::RegisterId::ARM64_W30, AArch64::W30}, 96353358Sdim {codeview::RegisterId::ARM64_WZR, AArch64::WZR}, 97353358Sdim {codeview::RegisterId::ARM64_X0, AArch64::X0}, 98353358Sdim {codeview::RegisterId::ARM64_X1, AArch64::X1}, 99353358Sdim {codeview::RegisterId::ARM64_X2, AArch64::X2}, 100353358Sdim {codeview::RegisterId::ARM64_X3, AArch64::X3}, 101353358Sdim {codeview::RegisterId::ARM64_X4, AArch64::X4}, 102353358Sdim {codeview::RegisterId::ARM64_X5, AArch64::X5}, 103353358Sdim {codeview::RegisterId::ARM64_X6, AArch64::X6}, 104353358Sdim {codeview::RegisterId::ARM64_X7, AArch64::X7}, 105353358Sdim {codeview::RegisterId::ARM64_X8, AArch64::X8}, 106353358Sdim {codeview::RegisterId::ARM64_X9, AArch64::X9}, 107353358Sdim {codeview::RegisterId::ARM64_X10, AArch64::X10}, 108353358Sdim {codeview::RegisterId::ARM64_X11, AArch64::X11}, 109353358Sdim {codeview::RegisterId::ARM64_X12, AArch64::X12}, 110353358Sdim {codeview::RegisterId::ARM64_X13, AArch64::X13}, 111353358Sdim {codeview::RegisterId::ARM64_X14, AArch64::X14}, 112353358Sdim {codeview::RegisterId::ARM64_X15, AArch64::X15}, 113353358Sdim {codeview::RegisterId::ARM64_X16, AArch64::X16}, 114353358Sdim {codeview::RegisterId::ARM64_X17, AArch64::X17}, 115353358Sdim {codeview::RegisterId::ARM64_X18, AArch64::X18}, 116353358Sdim {codeview::RegisterId::ARM64_X19, AArch64::X19}, 117353358Sdim {codeview::RegisterId::ARM64_X20, AArch64::X20}, 118353358Sdim {codeview::RegisterId::ARM64_X21, AArch64::X21}, 119353358Sdim {codeview::RegisterId::ARM64_X22, AArch64::X22}, 120353358Sdim {codeview::RegisterId::ARM64_X23, AArch64::X23}, 121353358Sdim {codeview::RegisterId::ARM64_X24, AArch64::X24}, 122353358Sdim {codeview::RegisterId::ARM64_X25, AArch64::X25}, 123353358Sdim {codeview::RegisterId::ARM64_X26, AArch64::X26}, 124353358Sdim {codeview::RegisterId::ARM64_X27, AArch64::X27}, 125353358Sdim {codeview::RegisterId::ARM64_X28, AArch64::X28}, 126353358Sdim {codeview::RegisterId::ARM64_FP, AArch64::FP}, 127353358Sdim {codeview::RegisterId::ARM64_LR, AArch64::LR}, 128353358Sdim {codeview::RegisterId::ARM64_SP, AArch64::SP}, 129353358Sdim {codeview::RegisterId::ARM64_ZR, AArch64::XZR}, 130353358Sdim {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV}, 131353358Sdim {codeview::RegisterId::ARM64_S0, AArch64::S0}, 132353358Sdim {codeview::RegisterId::ARM64_S1, AArch64::S1}, 133353358Sdim {codeview::RegisterId::ARM64_S2, AArch64::S2}, 134353358Sdim {codeview::RegisterId::ARM64_S3, AArch64::S3}, 135353358Sdim {codeview::RegisterId::ARM64_S4, AArch64::S4}, 136353358Sdim {codeview::RegisterId::ARM64_S5, AArch64::S5}, 137353358Sdim {codeview::RegisterId::ARM64_S6, AArch64::S6}, 138353358Sdim {codeview::RegisterId::ARM64_S7, AArch64::S7}, 139353358Sdim {codeview::RegisterId::ARM64_S8, AArch64::S8}, 140353358Sdim {codeview::RegisterId::ARM64_S9, AArch64::S9}, 141353358Sdim {codeview::RegisterId::ARM64_S10, AArch64::S10}, 142353358Sdim {codeview::RegisterId::ARM64_S11, AArch64::S11}, 143353358Sdim {codeview::RegisterId::ARM64_S12, AArch64::S12}, 144353358Sdim {codeview::RegisterId::ARM64_S13, AArch64::S13}, 145353358Sdim {codeview::RegisterId::ARM64_S14, AArch64::S14}, 146353358Sdim {codeview::RegisterId::ARM64_S15, AArch64::S15}, 147353358Sdim {codeview::RegisterId::ARM64_S16, AArch64::S16}, 148353358Sdim {codeview::RegisterId::ARM64_S17, AArch64::S17}, 149353358Sdim {codeview::RegisterId::ARM64_S18, AArch64::S18}, 150353358Sdim {codeview::RegisterId::ARM64_S19, AArch64::S19}, 151353358Sdim {codeview::RegisterId::ARM64_S20, AArch64::S20}, 152353358Sdim {codeview::RegisterId::ARM64_S21, AArch64::S21}, 153353358Sdim {codeview::RegisterId::ARM64_S22, AArch64::S22}, 154353358Sdim {codeview::RegisterId::ARM64_S23, AArch64::S23}, 155353358Sdim {codeview::RegisterId::ARM64_S24, AArch64::S24}, 156353358Sdim {codeview::RegisterId::ARM64_S25, AArch64::S25}, 157353358Sdim {codeview::RegisterId::ARM64_S26, AArch64::S26}, 158353358Sdim {codeview::RegisterId::ARM64_S27, AArch64::S27}, 159353358Sdim {codeview::RegisterId::ARM64_S28, AArch64::S28}, 160353358Sdim {codeview::RegisterId::ARM64_S29, AArch64::S29}, 161353358Sdim {codeview::RegisterId::ARM64_S30, AArch64::S30}, 162353358Sdim {codeview::RegisterId::ARM64_S31, AArch64::S31}, 163353358Sdim {codeview::RegisterId::ARM64_D0, AArch64::D0}, 164353358Sdim {codeview::RegisterId::ARM64_D1, AArch64::D1}, 165353358Sdim {codeview::RegisterId::ARM64_D2, AArch64::D2}, 166353358Sdim {codeview::RegisterId::ARM64_D3, AArch64::D3}, 167353358Sdim {codeview::RegisterId::ARM64_D4, AArch64::D4}, 168353358Sdim {codeview::RegisterId::ARM64_D5, AArch64::D5}, 169353358Sdim {codeview::RegisterId::ARM64_D6, AArch64::D6}, 170353358Sdim {codeview::RegisterId::ARM64_D7, AArch64::D7}, 171353358Sdim {codeview::RegisterId::ARM64_D8, AArch64::D8}, 172353358Sdim {codeview::RegisterId::ARM64_D9, AArch64::D9}, 173353358Sdim {codeview::RegisterId::ARM64_D10, AArch64::D10}, 174353358Sdim {codeview::RegisterId::ARM64_D11, AArch64::D11}, 175353358Sdim {codeview::RegisterId::ARM64_D12, AArch64::D12}, 176353358Sdim {codeview::RegisterId::ARM64_D13, AArch64::D13}, 177353358Sdim {codeview::RegisterId::ARM64_D14, AArch64::D14}, 178353358Sdim {codeview::RegisterId::ARM64_D15, AArch64::D15}, 179353358Sdim {codeview::RegisterId::ARM64_D16, AArch64::D16}, 180353358Sdim {codeview::RegisterId::ARM64_D17, AArch64::D17}, 181353358Sdim {codeview::RegisterId::ARM64_D18, AArch64::D18}, 182353358Sdim {codeview::RegisterId::ARM64_D19, AArch64::D19}, 183353358Sdim {codeview::RegisterId::ARM64_D20, AArch64::D20}, 184353358Sdim {codeview::RegisterId::ARM64_D21, AArch64::D21}, 185353358Sdim {codeview::RegisterId::ARM64_D22, AArch64::D22}, 186353358Sdim {codeview::RegisterId::ARM64_D23, AArch64::D23}, 187353358Sdim {codeview::RegisterId::ARM64_D24, AArch64::D24}, 188353358Sdim {codeview::RegisterId::ARM64_D25, AArch64::D25}, 189353358Sdim {codeview::RegisterId::ARM64_D26, AArch64::D26}, 190353358Sdim {codeview::RegisterId::ARM64_D27, AArch64::D27}, 191353358Sdim {codeview::RegisterId::ARM64_D28, AArch64::D28}, 192353358Sdim {codeview::RegisterId::ARM64_D29, AArch64::D29}, 193353358Sdim {codeview::RegisterId::ARM64_D30, AArch64::D30}, 194353358Sdim {codeview::RegisterId::ARM64_D31, AArch64::D31}, 195353358Sdim {codeview::RegisterId::ARM64_Q0, AArch64::Q0}, 196353358Sdim {codeview::RegisterId::ARM64_Q1, AArch64::Q1}, 197353358Sdim {codeview::RegisterId::ARM64_Q2, AArch64::Q2}, 198353358Sdim {codeview::RegisterId::ARM64_Q3, AArch64::Q3}, 199353358Sdim {codeview::RegisterId::ARM64_Q4, AArch64::Q4}, 200353358Sdim {codeview::RegisterId::ARM64_Q5, AArch64::Q5}, 201353358Sdim {codeview::RegisterId::ARM64_Q6, AArch64::Q6}, 202353358Sdim {codeview::RegisterId::ARM64_Q7, AArch64::Q7}, 203353358Sdim {codeview::RegisterId::ARM64_Q8, AArch64::Q8}, 204353358Sdim {codeview::RegisterId::ARM64_Q9, AArch64::Q9}, 205353358Sdim {codeview::RegisterId::ARM64_Q10, AArch64::Q10}, 206353358Sdim {codeview::RegisterId::ARM64_Q11, AArch64::Q11}, 207353358Sdim {codeview::RegisterId::ARM64_Q12, AArch64::Q12}, 208353358Sdim {codeview::RegisterId::ARM64_Q13, AArch64::Q13}, 209353358Sdim {codeview::RegisterId::ARM64_Q14, AArch64::Q14}, 210353358Sdim {codeview::RegisterId::ARM64_Q15, AArch64::Q15}, 211353358Sdim {codeview::RegisterId::ARM64_Q16, AArch64::Q16}, 212353358Sdim {codeview::RegisterId::ARM64_Q17, AArch64::Q17}, 213353358Sdim {codeview::RegisterId::ARM64_Q18, AArch64::Q18}, 214353358Sdim {codeview::RegisterId::ARM64_Q19, AArch64::Q19}, 215353358Sdim {codeview::RegisterId::ARM64_Q20, AArch64::Q20}, 216353358Sdim {codeview::RegisterId::ARM64_Q21, AArch64::Q21}, 217353358Sdim {codeview::RegisterId::ARM64_Q22, AArch64::Q22}, 218353358Sdim {codeview::RegisterId::ARM64_Q23, AArch64::Q23}, 219353358Sdim {codeview::RegisterId::ARM64_Q24, AArch64::Q24}, 220353358Sdim {codeview::RegisterId::ARM64_Q25, AArch64::Q25}, 221353358Sdim {codeview::RegisterId::ARM64_Q26, AArch64::Q26}, 222353358Sdim {codeview::RegisterId::ARM64_Q27, AArch64::Q27}, 223353358Sdim {codeview::RegisterId::ARM64_Q28, AArch64::Q28}, 224353358Sdim {codeview::RegisterId::ARM64_Q29, AArch64::Q29}, 225353358Sdim {codeview::RegisterId::ARM64_Q30, AArch64::Q30}, 226353358Sdim {codeview::RegisterId::ARM64_Q31, AArch64::Q31}, 227353358Sdim 228353358Sdim }; 229353358Sdim for (unsigned I = 0; I < array_lengthof(RegMap); ++I) 230353358Sdim MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg)); 231327952Sdim} 232327952Sdim 233288943Sdimstatic MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) { 234249259Sdim MCRegisterInfo *X = new MCRegisterInfo(); 235276479Sdim InitAArch64MCRegisterInfo(X, AArch64::LR); 236327952Sdim AArch64_MC::initLLVMToCVRegMapping(X); 237249259Sdim return X; 238249259Sdim} 239249259Sdim 240261991Sdimstatic MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, 241360784Sdim const Triple &TheTriple, 242360784Sdim const MCTargetOptions &Options) { 243276479Sdim MCAsmInfo *MAI; 244288943Sdim if (TheTriple.isOSBinFormatMachO()) 245360784Sdim MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32); 246327952Sdim else if (TheTriple.isWindowsMSVCEnvironment()) 247327952Sdim MAI = new AArch64MCAsmInfoMicrosoftCOFF(); 248321369Sdim else if (TheTriple.isOSBinFormatCOFF()) 249327952Sdim MAI = new AArch64MCAsmInfoGNUCOFF(); 250276479Sdim else { 251321369Sdim assert(TheTriple.isOSBinFormatELF() && "Invalid target"); 252288943Sdim MAI = new AArch64MCAsmInfoELF(TheTriple); 253276479Sdim } 254276479Sdim 255276479Sdim // Initial state of the frame pointer is SP. 256276479Sdim unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); 257276479Sdim MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); 258261991Sdim MAI->addInitialFrameState(Inst); 259249259Sdim 260249259Sdim return MAI; 261249259Sdim} 262249259Sdim 263288943Sdimstatic MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, 264249259Sdim unsigned SyntaxVariant, 265249259Sdim const MCAsmInfo &MAI, 266249259Sdim const MCInstrInfo &MII, 267288943Sdim const MCRegisterInfo &MRI) { 268249259Sdim if (SyntaxVariant == 0) 269288943Sdim return new AArch64InstPrinter(MAI, MII, MRI); 270276479Sdim if (SyntaxVariant == 1) 271288943Sdim return new AArch64AppleInstPrinter(MAI, MII, MRI); 272276479Sdim 273276479Sdim return nullptr; 274249259Sdim} 275249259Sdim 276288943Sdimstatic MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, 277327952Sdim std::unique_ptr<MCAsmBackend> &&TAB, 278341825Sdim std::unique_ptr<MCObjectWriter> &&OW, 279327952Sdim std::unique_ptr<MCCodeEmitter> &&Emitter, 280327952Sdim bool RelaxAll) { 281341825Sdim return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW), 282341825Sdim std::move(Emitter), RelaxAll); 283249259Sdim} 284249259Sdim 285327952Sdimstatic MCStreamer *createMachOStreamer(MCContext &Ctx, 286327952Sdim std::unique_ptr<MCAsmBackend> &&TAB, 287341825Sdim std::unique_ptr<MCObjectWriter> &&OW, 288327952Sdim std::unique_ptr<MCCodeEmitter> &&Emitter, 289327952Sdim bool RelaxAll, 290288943Sdim bool DWARFMustBeAtTheEnd) { 291341825Sdim return createMachOStreamer(Ctx, std::move(TAB), std::move(OW), 292341825Sdim std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd, 293288943Sdim /*LabelSections*/ true); 294288943Sdim} 295288943Sdim 296327952Sdimstatic MCStreamer * 297327952SdimcreateWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB, 298341825Sdim std::unique_ptr<MCObjectWriter> &&OW, 299327952Sdim std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll, 300327952Sdim bool IncrementalLinkerCompatible) { 301341825Sdim return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW), 302327952Sdim std::move(Emitter), RelaxAll, 303321369Sdim IncrementalLinkerCompatible); 304321369Sdim} 305321369Sdim 306341825Sdimnamespace { 307341825Sdim 308341825Sdimclass AArch64MCInstrAnalysis : public MCInstrAnalysis { 309341825Sdimpublic: 310341825Sdim AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 311341825Sdim 312341825Sdim bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 313341825Sdim uint64_t &Target) const override { 314341825Sdim // Search for a PC-relative argument. 315341825Sdim // This will handle instructions like bcc (where the first argument is the 316341825Sdim // condition code) and cbz (where it is a register). 317341825Sdim const auto &Desc = Info->get(Inst.getOpcode()); 318341825Sdim for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) { 319341825Sdim if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) { 320341825Sdim int64_t Imm = Inst.getOperand(i).getImm() * 4; 321341825Sdim Target = Addr + Imm; 322341825Sdim return true; 323341825Sdim } 324341825Sdim } 325341825Sdim return false; 326341825Sdim } 327344779Sdim 328344779Sdim std::vector<std::pair<uint64_t, uint64_t>> 329344779Sdim findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 330344779Sdim uint64_t GotPltSectionVA, 331344779Sdim const Triple &TargetTriple) const override { 332344779Sdim // Do a lightweight parsing of PLT entries. 333344779Sdim std::vector<std::pair<uint64_t, uint64_t>> Result; 334344779Sdim for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End; 335344779Sdim Byte += 4) { 336344779Sdim uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); 337353358Sdim uint64_t Off = 0; 338353358Sdim // Check for optional bti c that prefixes adrp in BTI enabled entries 339353358Sdim if (Insn == 0xd503245f) { 340353358Sdim Off = 4; 341353358Sdim Insn = support::endian::read32le(PltContents.data() + Byte + Off); 342353358Sdim } 343344779Sdim // Check for adrp. 344344779Sdim if ((Insn & 0x9f000000) != 0x90000000) 345344779Sdim continue; 346353358Sdim Off += 4; 347344779Sdim uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) + 348344779Sdim (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14); 349353358Sdim uint32_t Insn2 = 350353358Sdim support::endian::read32le(PltContents.data() + Byte + Off); 351344779Sdim // Check for: ldr Xt, [Xn, #pimm]. 352344779Sdim if (Insn2 >> 22 == 0x3e5) { 353344779Sdim Imm += ((Insn2 >> 10) & 0xfff) << 3; 354344779Sdim Result.push_back(std::make_pair(PltSectionVA + Byte, Imm)); 355344779Sdim Byte += 4; 356344779Sdim } 357344779Sdim } 358344779Sdim return Result; 359344779Sdim } 360341825Sdim}; 361341825Sdim 362341825Sdim} // end anonymous namespace 363341825Sdim 364314564Sdimstatic MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) { 365341825Sdim return new AArch64MCInstrAnalysis(Info); 366314564Sdim} 367314564Sdim 368276479Sdim// Force static initialization. 369360784Sdimextern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC() { 370314564Sdim for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(), 371353358Sdim &getTheAArch64_32Target(), &getTheARM64Target(), 372353358Sdim &getTheARM64_32Target()}) { 373288943Sdim // Register the MC asm info. 374288943Sdim RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); 375249259Sdim 376288943Sdim // Register the MC instruction info. 377288943Sdim TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); 378249259Sdim 379288943Sdim // Register the MC register info. 380288943Sdim TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo); 381249259Sdim 382288943Sdim // Register the MC subtarget info. 383288943Sdim TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo); 384249259Sdim 385314564Sdim // Register the MC instruction analyzer. 386314564Sdim TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis); 387314564Sdim 388288943Sdim // Register the MC Code Emitter 389288943Sdim TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter); 390249259Sdim 391288943Sdim // Register the obj streamers. 392288943Sdim TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); 393288943Sdim TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer); 394321369Sdim TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer); 395249259Sdim 396288943Sdim // Register the obj target streamer. 397288943Sdim TargetRegistry::RegisterObjectTargetStreamer( 398288943Sdim *T, createAArch64ObjectTargetStreamer); 399249259Sdim 400288943Sdim // Register the asm streamer. 401288943Sdim TargetRegistry::RegisterAsmTargetStreamer(*T, 402288943Sdim createAArch64AsmTargetStreamer); 403288943Sdim // Register the MCInstPrinter. 404288943Sdim TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter); 405288943Sdim } 406280031Sdim 407288943Sdim // Register the asm backend. 408353358Sdim for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(), 409353358Sdim &getTheARM64Target(), &getTheARM64_32Target()}) 410288943Sdim TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend); 411314564Sdim TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(), 412288943Sdim createAArch64beAsmBackend); 413249259Sdim} 414