Searched refs:Registers (Results 1 - 13 of 13) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.h31 msgpack::DocNode Registers; member in class:llvm::AMDGPUPALMetadata
H A DAMDGPUPALMetadata.cpp53 // store as Registers[key]=value in the map.
269 // Registers that code generation sets/modifies metadata for.
290 // Registers not known to code generation.
606 auto Registers = getRegisters(); local
607 if (Registers.getMap().empty())
611 for (auto I : Registers.getMap()) {
634 Registers = RegsObj.getMap();
648 Registers.getMap()[Key] = I.second;
666 if (Registers.isEmpty())
667 Registers
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1133 for (auto &Reg : Registers)
1137 for (auto &Reg : Registers)
1147 for (auto &Reg : Registers)
1161 for (auto &Reg : Registers)
1167 for (auto &Reg : Registers)
1172 for (auto &Reg : Registers) {
1230 Registers.emplace_back(Def, Registers.size() + 1);
1231 Reg = &Registers.back();
1328 for (const CodeGenRegister &R : Registers) {
1586 const auto &Registers = RegBank.getRegisters(); local
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H A DAsmWriterEmitter.cpp502 const std::deque<CodeGenRegister> &Registers) {
504 SmallVector<std::string, 4> AsmNames(Registers.size());
506 for (const auto &Reg : Registers) {
546 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
558 const auto &Registers = Target.getRegBank().getRegisters(); local
561 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
572 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
578 emitRegisterNameString(O, R->getName(), Registers);
580 emitRegisterNameString(O, "", Registers);
501 emitRegisterNameString(raw_ostream &O, StringRef AltName, const std::deque<CodeGenRegister> &Registers) argument
H A DRegisterInfoEmitter.cpp104 const auto &Registers = Bank.getRegisters(); local
107 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
109 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
126 for (const auto &Reg : Registers)
128 assert(Registers.size() == Registers.back().EnumValue &&
130 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
H A DAsmMatcherEmitter.cpp203 RegisterSet Registers; member in struct:__anon2890::ClassInfo
236 // Registers classes are only related to registers classes, and only if
244 std::set_intersection(Registers.begin(), Registers.end(),
245 RHS.Registers.begin(), RHS.Registers.end(),
351 if (Registers.size() != RHS.Registers.size())
352 return Registers.size() < RHS.Registers
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H A DCodeGenRegisters.h215 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
536 // Registers.
537 std::deque<CodeGenRegister> Registers; member in class:llvm::CodeGenRegBank
639 return Registers;
649 // Get a Register's index into the Registers array.
/freebsd-11-stable/contrib/llvm-project/clang/utils/TableGen/
H A DMveEmitter.cpp307 unsigned Registers; member in class:__anon961::MultiVectorType
310 MultiVectorType(unsigned Registers, const VectorType *Element) argument
312 Registers(Registers) {}
314 return Registers * Element->sizeInBits();
316 unsigned registers() const { return Registers; }
319 return Element->cNameBase() + "x" + utostr(Registers);
969 const MultiVectorType *getMultiVectorType(unsigned Registers,
971 std::pair<std::string, unsigned> key(VT->cNameBase(), Registers);
973 MultiVectorTypes[key] = std::make_unique<MultiVectorType>(Registers, V
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp379 static SmallVector<unsigned, 31> Registers = { local
386 for (uint8_t i = 0; i < Registers.size() - 1; i++) {
387 if (Registers[i] == Reg1) {
388 if (Registers[i + 1] == Reg2)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3006 static const MCPhysReg Registers[6][8] = { local
3028 SrcReg = Registers[0][GPRIdx++];
3032 SrcReg = Registers[1][GPRIdx++];
3035 SrcReg = Registers[2][FPRIdx++];
3038 SrcReg = Registers[3][FPRIdx++];
3041 SrcReg = Registers[4][FPRIdx++];
3044 SrcReg = Registers[5][FPRIdx++];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp708 SmallVector<unsigned, 8> Registers; member in class:__anon2168::ARMOperand
909 return Registers;
3561 Op->Registers.push_back(P.second);
4299 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; local
4305 Registers.emplace_back(EReg, Reg);
4322 Registers.emplace_back(EReg, Reg);
4353 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4387 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4413 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4419 Registers
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/freebsd-11-stable/crypto/openssl/crypto/bn/asm/
H A Dpa-risc2.s918 ; Registers to hold 64-bit values to manipulate. The "L" part
H A Dpa-risc2W.s905 ; Registers to hold 64-bit values to manipulate. The "L" part

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