Searched refs:RVLocs (Results 1 - 20 of 20) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp37 const SmallVectorImpl<CCValAssign> &RVLocs,
244 SmallVector<CCValAssign, 16> RVLocs; local
246 CCState RetCCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
365 return lowerCallResult(Chain, Glue, RVLocs, dl, DAG, InVals);
371 const SmallVectorImpl<CCValAssign> &RVLocs,
376 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
377 const CCValAssign &VA = RVLocs[i];
595 SmallVector<CCValAssign, 16> RVLocs; local
596 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
615 SmallVector<CCValAssign, 16> RVLocs; local
370 lowerCallResult(SDValue Chain, SDValue Glue, const SmallVectorImpl<CCValAssign> &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp415 SmallVector<CCValAssign, 16> RVLocs; local
419 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
433 for (unsigned i = 0; i != RVLocs.size(); ++i) {
434 CCValAssign &VA = RVLocs[i];
461 SmallVector<CCValAssign, 16> RVLocs; local
462 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
474 for (auto &Val : RVLocs) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp562 SmallVectorImpl<CCValAssign> &RVLocs,
729 SmallVector<CCValAssign, 16> RVLocs; local
730 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
744 SmallVector<CCValAssign, 16> RVLocs; local
751 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
755 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
761 for (unsigned i = 0; i != RVLocs.size(); ++i) {
762 CCValAssign &VA = RVLocs[i];
942 SmallVector<CCValAssign, 16> RVLocs; local
943 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
561 AnalyzeReturnValues(CCState &State, SmallVectorImpl<CCValAssign> &RVLocs, const SmallVectorImpl<ArgT> &Args) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1317 SmallVector<CCValAssign, 16> RVLocs; local
1318 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1325 if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) {
1328 std::reverse(RVLocs.begin(), RVLocs.end());
1332 for (CCValAssign const &RVLoc : RVLocs) {
1362 SmallVector<CCValAssign, 16> RVLocs; local
1363 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1376 SmallVector<CCValAssign, 16> RVLocs; local
1379 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1062 const SmallVectorImpl<CCValAssign> &RVLocs,
1067 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1068 const CCValAssign &VA = RVLocs[i];
1125 SmallVector<CCValAssign, 16> RVLocs; local
1127 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1229 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
1427 SmallVector<CCValAssign, 16> RVLocs; local
1428 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1449 SmallVector<CCValAssign, 16> RVLocs; local
1452 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1061 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp540 SmallVector<CCValAssign, 16> RVLocs; local
543 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
553 for (unsigned i = 0; i != RVLocs.size(); ++i) {
554 CCValAssign &VA = RVLocs[i];
779 SmallVector<CCValAssign, 16> RVLocs; local
780 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
786 for (unsigned I = 0; I != RVLocs.size(); ++I) {
787 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
788 RVLocs[I].getValVT(), InFlag)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp216 SmallVector<CCValAssign, 16> RVLocs; local
219 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
232 i != RVLocs.size();
234 CCValAssign &VA = RVLocs[i];
254 VA = RVLocs[++i]; // skip ahead to next loc
299 SmallVector<CCValAssign, 16> RVLocs; local
302 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
316 for (unsigned i = 0; i != RVLocs.size(); ++i) {
317 CCValAssign &VA = RVLocs[i];
345 if (i+1 < RVLocs
981 SmallVector<CCValAssign, 16> RVLocs; local
1289 SmallVector<CCValAssign, 16> RVLocs; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp2045 SmallVector<CCValAssign, 16> RVLocs; local
2046 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2050 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2053 MVT DestVT = RVLocs[0].getValVT();
2058 .addReg(RVLocs[0].getLocReg())
2059 .addReg(RVLocs[1].getLocReg()));
2061 UsedRegs.push_back(RVLocs[0].getLocReg());
2062 UsedRegs.push_back(RVLocs[1].getLocReg());
2067 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2068 MVT CopyVT = RVLocs[
2217 SmallVector<CCValAssign, 16> RVLocs; local
2325 SmallVector<CCValAssign, 16> RVLocs; local
[all...]
H A DARMISelLowering.cpp1967 SmallVector<CCValAssign, 16> RVLocs; local
1968 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1973 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1974 CCValAssign VA = RVLocs[i];
1992 VA = RVLocs[++i]; // skip ahead to next loc
2006 VA = RVLocs[++i]; // skip ahead to next loc
2010 VA = RVLocs[++i]; // skip ahead to next loc
2718 SmallVector<CCValAssign, 16> RVLocs; local
2719 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2763 SmallVector<CCValAssign, 16> RVLocs; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1502 SmallVector<CCValAssign, 16> RVLocs; local
1503 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1505 CCValAssign &VA = RVLocs[0];
1506 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1584 SmallVector<CCValAssign, 16> RVLocs; local
1585 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1587 if (RVLocs.size() > 1)
H A DPPCISelLowering.cpp5019 SmallVector<CCValAssign, 16> RVLocs; local
5020 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5029 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5030 CCValAssign &VA = RVLocs[i];
5040 VA = RVLocs[++i]; // skip ahead to next loc
7238 SmallVector<CCValAssign, 16> RVLocs; local
7239 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
7252 SmallVector<CCValAssign, 16> RVLocs; local
7253 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
7264 for (unsigned i = 0, RealResIdx = 0; i != RVLocs
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp181 SmallVector<CCValAssign, 16> RVLocs; local
182 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
199 SmallVector<CCValAssign, 16> RVLocs; local
202 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
215 for (unsigned i = 0; i != RVLocs.size(); ++i) {
216 CCValAssign &VA = RVLocs[i];
324 SmallVector<CCValAssign, 16> RVLocs; local
326 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
335 for (unsigned i = 0; i != RVLocs.size(); ++i) {
337 if (RVLocs[
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1284 SmallVector<CCValAssign, 16> RVLocs; local
1285 MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1292 if (RVLocs.size() != 1)
1295 MVT CopyVT = RVLocs[0].getValVT();
1305 ResultReg).addReg(RVLocs[0].getLocReg());
1306 CLI.InRegs.push_back(RVLocs[0].getLocReg());
H A DMipsISelLowering.cpp3470 SmallVector<CCValAssign, 16> RVLocs; local
3471 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3480 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3481 CCValAssign &VA = RVLocs[i];
3484 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3485 RVLocs[i].getLocVT(), InFlag);
3750 SmallVector<CCValAssign, 16> RVLocs; local
3751 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3783 SmallVector<CCValAssign, 16> RVLocs; local
3787 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DA
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2372 SmallVector<CCValAssign, 16> RVLocs; local
2373 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
2377 for (auto &VA : RVLocs) {
2406 SmallVector<CCValAssign, 16> RVLocs; local
2407 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2429 SmallVector<CCValAssign, 16> RVLocs; local
2432 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2442 for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
2444 CCValAssign &VA = RVLocs[i];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp3546 SmallVector<CCValAssign, 16> RVLocs; local
3547 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs,
3553 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3554 CCValAssign &VA = RVLocs[i];
3596 CLI.NumResultRegs = RVLocs.size();
H A DX86ISelLowering.cpp2569 SmallVector<CCValAssign, 16> RVLocs; local
2570 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2655 SmallVector<CCValAssign, 16> RVLocs; local
2656 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2667 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
2669 CCValAssign &VA = RVLocs[I];
2745 Passv64i1ArgInRegs(dl, DAG, ValToCopy, RegsToPass, VA, RVLocs[++I],
2753 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
2999 SmallVector<CCValAssign, 16> RVLocs; local
3000 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3163 SmallVector<CCValAssign, 16> RVLocs; local
3164 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
3168 if (RVLocs.size() != 1)
3172 MVT CopyVT = RVLocs[0].getValVT();
3181 .addReg(RVLocs[0].getLocReg());
3182 CLI.InRegs.push_back(RVLocs[0].getLocReg());
H A DAArch64ISelLowering.cpp3682 SmallVector<CCValAssign, 16> RVLocs; local
3684 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3689 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3690 CCValAssign VA = RVLocs[i];
4346 SmallVector<CCValAssign, 16> RVLocs; local
4347 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
4363 SmallVector<CCValAssign, 16> RVLocs; local
4364 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4372 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
4374 CCValAssign &VA = RVLocs[
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp2263 SmallVector<CCValAssign, 16> RVLocs;
2264 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2288 SmallVector<CCValAssign, 48> RVLocs; local
2292 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2318 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2320 CCValAssign &VA = RVLocs[I];
2386 SmallVector<CCValAssign, 16> RVLocs; local
2387 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2392 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2393 CCValAssign VA = RVLocs[
[all...]

Completed in 490 milliseconds