Searched refs:RESET_CONTROL (Results 1 - 5 of 5) sorted by relevance
/freebsd-11-stable/sys/arm/cavium/cns11xx/ |
H A D | econa.c | 582 control = system_read_4(econa_softc, RESET_CONTROL); 584 system_write_4(econa_softc, RESET_CONTROL, control); 585 control = system_read_4(econa_softc, RESET_CONTROL); 587 system_write_4(econa_softc, RESET_CONTROL, control); 599 cfg_reg = system_read_4(econa_softc, RESET_CONTROL); 602 system_write_4(econa_softc, RESET_CONTROL, cfg_reg); 608 cfg_reg = system_read_4(econa_softc, RESET_CONTROL); 610 system_write_4(econa_softc, RESET_CONTROL, cfg_reg); 615 cfg_reg = system_read_4(econa_softc, RESET_CONTROL); 618 system_write_4(econa_softc, RESET_CONTROL, cfg_re [all...] |
H A D | econa_reg.h | 176 #define RESET_CONTROL 0x4 macro
|
/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | scorpion_reg_map.h | 293 volatile u_int32_t RESET_CONTROL; /* 0x0 - 0x4 */ member in struct:rtc_reg
|
H A D | osprey_reg_map.h | 597 volatile u_int32_t RESET_CONTROL; /* 0x7000 - 0x7004 */ member in struct:rtc_reg 2447 volatile u_int32_t RESET_CONTROL; /* 0x0 - 0x4 */ member in struct:jupiter_reg_map__rtc_reg_csr
|
H A D | ar9300reg.h | 1103 #define AR_RTC_RC AR_RTC_OFFSET(RESET_CONTROL)
|
Completed in 153 milliseconds