1/*- 2 * Copyright (c) 2009 Yohanes Nugroho <yohanes@gmail.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28#ifndef _ARM_ECONA_REG_H 29#define _ARM_ECONA_REG_H 30 31#define ECONA_SRAM_SIZE 0x10000000 32#define ECONA_DRAM_BASE 0x00000000 /* DRAM (via DDR Control Module) */ 33 34#define ECONA_SDRAM_BASE 0x40000000 35#define ECONA_SDRAM_SIZE 0x1000000 36 37 38#define ECONA_IO_BASE 0x70000000 39#define ECONA_IO_SIZE 0x0E000000 40#define ECONA_PIC_BASE 0x0D000000 41#define ECONA_PIC_SIZE 0x01000000 42 43#define ECONA_UART_BASE 0x08000000 44#define ECONA_UART_SIZE 0x01000000 45#define ECONA_IRQ_UART 0xA 46 47#define ECONA_TIMER_BASE 0x09000000 48#define ECONA_TIMER_SIZE 0x01000000 49#define ECONA_IRQ_TIMER_1 0 50#define ECONA_IRQ_TIMER_2 1 51#define ECONA_IRQ_OHCI 23 52#define ECONA_IRQ_EHCI 24 53 54#define ECONA_NET_BASE 0x00000000 55 56#define ECONA_SYSTEM_BASE 0x07000000 57#define ECONA_SYSTEM_SIZE 0x01000000 58 59#define ECONA_NET_SIZE 0x01000000 60 61#define ECONA_CFI_PBASE 0x10000000 62#define ECONA_CFI_VBASE 0xD0000000 63#define ECONA_CFI_SIZE 0x10000000 64 65#define ECONA_IRQ_STATUS 18 66#define ECONA_IRQ_TSTC 19 67#define ECONA_IRQ_FSRC 20 68#define ECONA_IRQ_TSQE 21 69#define ECONA_IRQ_FSQF 22 70 71#define ECONA_IRQ_SYSTEM 0 72 73#define ECONA_EHCI_PBASE 0xC8000000 74#define ECONA_EHCI_VBASE 0xF8000000 75#define ECONA_EHCI_SIZE 0x8000000 76 77#define ECONA_OHCI_PBASE 0xC0000000 78#define ECONA_OHCI_VBASE 0xF0000000 79#define ECONA_OHCI_SIZE 0x8000000 80 81#define ECONA_USB_SIZE 0xf000000 82 83/*Interrupt controller*/ 84#define INTC_LEVEL_TRIGGER 0 85#define INTC_EDGE_TRIGGER 1 86#define INTC_ACTIVE_HIGH 0 87#define INTC_ACTIVE_LOW 1 88/* 89 * define rising/falling edge for edge trigger mode 90 */ 91#define INTC_RISING_EDGE 0 92#define INTC_FALLING_EDGE 1 93 94#define INTC_INTERRUPT_SOURCE_REG_OFFSET 0x00 95#define INTC_INTERRUPT_MASK_REG_OFFSET 0x04 96#define INTC_INTERRUPT_CLEAR_EDGE_TRIGGER_REG_OFFSET 0x08 97#define INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET 0x0C 98#define INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET 0x10 99#define INTC_INTERRUPT_STATUS_REG_OFFSET 0x14 100#define INTC_FIQ_MODE_SELECT_REG_OFFSET 0x18 101#define INTC_SOFTWARE_INTERRUPT_REG_OFFSET 0x1C 102 103 104/* 105 * define rising/falling edge for edge trigger mode 106 */ 107#define INTC_RISING_EDGE 0 108#define INTC_FALLING_EDGE 1 109 110 111#define TIMER_TM1_COUNTER_REG 0x00 112#define TIMER_TM1_LOAD_REG 0x04 113#define TIMER_TM1_MATCH1_REG 0x08 114#define TIMER_TM1_MATCH2_REG 0x0C 115 116#define TIMER_TM2_COUNTER_REG 0x10 117#define TIMER_TM2_LOAD_REG 0x14 118#define TIMER_TM2_MATCH1_REG 0x18 119#define TIMER_TM2_MATCH2_REG 0x1C 120 121#define TIMER_TM_CR_REG 0x30 122#define TIMER_TM_INTR_STATUS_REG 0x34 123#define TIMER_TM_INTR_MASK_REG 0x38 124 125#define TIMER_TM_REVISION_REG 0x3C 126 127 128#define INTC_TIMER1_BIT_INDEX 0 129 130#define TIMER1_UP_DOWN_COUNT (1<<9) 131#define TIMER2_UP_DOWN_COUNT (1<<10) 132 133#define TIMER1_MATCH1_INTR (1<<0) 134#define TIMER1_MATCH2_INTR (1<<1) 135#define TIMER1_OVERFLOW_INTR (1<<2) 136 137 138#define TIMER2_MATCH1_INTR (1<<3) 139#define TIMER2_MATCH2_INTR (1<<4) 140#define TIMER2_OVERFLOW_INTR (1<<5) 141 142 143#define TIMER_CLOCK_SOURCE_PCLK 0 144#define TIMER_CLOCK_SOURCE_EXT_CLK 1 145 146/* 147 * define interrupt trigger mode 148 */ 149#define INTC_LEVEL_TRIGGER 0 150#define INTC_EDGE_TRIGGER 1 151 152 153#define INTC_TRIGGER_UNKNOWN -1 154 155#define TIMER1_OVERFLOW_INTERRUPT (1<<2) 156#define TIMER2_OVERFLOW_INTERRUPT (1<<5) 157#define TIMER_INTERRUPT_STATUS_REG 0x34 158 159 160#define TIMER1_ENABLE (1<<0) 161#define TIMER1_CLOCK_SOURCE (1<<1) 162#define TIMER1_OVERFLOW_ENABLE (1<<2) 163 164 165#define TIMER2_ENABLE (1<<3) 166#define TIMER2_CLOCK_SOURCE (1<<4) 167#define TIMER2_OVERFLOW_ENABLE (1<<5) 168 169 170#define TIMER_1 1 171 172#define EC_UART_CLOCK 14769200 173#define EC_UART_REGSHIFT 2 174 175#define SYSTEM_CLOCK 0x14 176#define RESET_CONTROL 0x4 177#define GLOBAL_RESET 0x1 178#define NET_INTERFACE_RESET (0x1 << 4) 179 180#endif 181