1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian#ifndef _DEV_ATH_AR9300REG_H 18250003Sadrian#define _DEV_ATH_AR9300REG_H 19250003Sadrian 20250003Sadrian#include "osprey_reg_map.h" 21250003Sadrian#include "wasp_reg_map.h" 22250003Sadrian 23250003Sadrian/****************************************************************************** 24250003Sadrian * MAC Register Map 25250003Sadrian******************************************************************************/ 26250003Sadrian#define AR_MAC_DMA_OFFSET(_x) offsetof(struct mac_dma_reg, _x) 27250003Sadrian 28250003Sadrian/* 29250003Sadrian * MAC DMA Registers 30250003Sadrian */ 31250003Sadrian 32250003Sadrian/* MAC Control Register - only write values of 1 have effect */ 33250003Sadrian#define AR_CR AR_MAC_DMA_OFFSET(MAC_DMA_CR) 34250003Sadrian#define AR_CR_LP_RXE 0x00000004 // Receive LPQ enable 35250003Sadrian#define AR_CR_HP_RXE 0x00000008 // Receive HPQ enable 36250003Sadrian#define AR_CR_RXD 0x00000020 // Receive disable 37250003Sadrian#define AR_CR_SWI 0x00000040 // One-shot software interrupt 38250003Sadrian#define AR_CR_RXE (AR_CR_LP_RXE|AR_CR_HP_RXE) 39250003Sadrian 40250003Sadrian/* MAC configuration and status register */ 41250003Sadrian#define AR_CFG AR_MAC_DMA_OFFSET(MAC_DMA_CFG) 42250003Sadrian#define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words 43250003Sadrian#define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words 44250003Sadrian#define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words 45250003Sadrian#define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words 46250003Sadrian#define AR_CFG_SWRG 0x00000010 // byteswap register access data words 47250003Sadrian#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc) 48250003Sadrian#define AR_CFG_PHOK 0x00000100 // PHY OK status 49250003Sadrian#define AR_CFG_CLK_GATE_DIS 0x00000400 // Clock gating disable 50250003Sadrian#define AR_CFG_EEBS 0x00000200 // EEPROM busy 51250003Sadrian#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue full threshold 52250003Sadrian#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 // Shift for PCI core master request queue full threshold 53250003Sadrian#define AR_CFG_MISSING_TX_INTR_FIX_ENABLE 0x00080000 // See EV 61133 for details. 54250003Sadrian 55250003Sadrian/* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */ 56250003Sadrian#define AR_RXBP_THRESH AR_MAC_DMA_OFFSET(MAC_DMA_RXBUFPTR_THRESH) 57250003Sadrian#define AR_RXBP_THRESH_HP 0x0000000f 58250003Sadrian#define AR_RXBP_THRESH_HP_S 0 59250003Sadrian#define AR_RXBP_THRESH_LP 0x00003f00 60250003Sadrian#define AR_RXBP_THRESH_LP_S 8 61250003Sadrian 62250003Sadrian/* Tx DMA Descriptor Pointer Threshold register */ 63250003Sadrian#define AR_TXDP_THRESH AR_MAC_DMA_OFFSET(MAC_DMA_TXDPPTR_THRESH) 64250003Sadrian 65250003Sadrian/* Mac Interrupt rate threshold register */ 66250003Sadrian#define AR_MIRT AR_MAC_DMA_OFFSET(MAC_DMA_MIRT) 67250003Sadrian#define AR_MIRT_VAL 0x0000ffff // in uS 68250003Sadrian#define AR_MIRT_VAL_S 16 69250003Sadrian 70250003Sadrian/* MAC Global Interrupt enable register */ 71250003Sadrian#define AR_IER AR_MAC_DMA_OFFSET(MAC_DMA_GLOBAL_IER) 72250003Sadrian#define AR_IER_ENABLE 0x00000001 // Global interrupt enable 73250003Sadrian#define AR_IER_DISABLE 0x00000000 // Global interrupt disable 74250003Sadrian 75250003Sadrian/* Mac Tx Interrupt mitigation threshold */ 76250003Sadrian#define AR_TIMT AR_MAC_DMA_OFFSET(MAC_DMA_TIMT) 77250003Sadrian#define AR_TIMT_LAST 0x0000ffff // Last packet threshold 78250003Sadrian#define AR_TIMT_LAST_S 0 79250003Sadrian#define AR_TIMT_FIRST 0xffff0000 // First packet threshold 80250003Sadrian#define AR_TIMT_FIRST_S 16 81250003Sadrian 82250003Sadrian/* Mac Rx Interrupt mitigation threshold */ 83250003Sadrian#define AR_RIMT AR_MAC_DMA_OFFSET(MAC_DMA_RIMT) 84250003Sadrian#define AR_RIMT_LAST 0x0000ffff // Last packet threshold 85250003Sadrian#define AR_RIMT_LAST_S 0 86250003Sadrian#define AR_RIMT_FIRST 0xffff0000 // First packet threshold 87250003Sadrian#define AR_RIMT_FIRST_S 16 88250003Sadrian 89250003Sadrian#define AR_DMASIZE_4B 0x00000000 // DMA size 4 bytes (TXCFG + RXCFG) 90250003Sadrian#define AR_DMASIZE_8B 0x00000001 // DMA size 8 bytes 91250003Sadrian#define AR_DMASIZE_16B 0x00000002 // DMA size 16 bytes 92250003Sadrian#define AR_DMASIZE_32B 0x00000003 // DMA size 32 bytes 93250003Sadrian#define AR_DMASIZE_64B 0x00000004 // DMA size 64 bytes 94250003Sadrian#define AR_DMASIZE_128B 0x00000005 // DMA size 128 bytes 95250003Sadrian#define AR_DMASIZE_256B 0x00000006 // DMA size 256 bytes 96250003Sadrian#define AR_DMASIZE_512B 0x00000007 // DMA size 512 bytes 97250003Sadrian 98250003Sadrian/* MAC Tx DMA size config register */ 99250003Sadrian#define AR_TXCFG AR_MAC_DMA_OFFSET(MAC_DMA_TXCFG) 100250003Sadrian#define AR_TXCFG_DMASZ_MASK 0x00000007 101250003Sadrian#define AR_TXCFG_DMASZ_4B 0 102250003Sadrian#define AR_TXCFG_DMASZ_8B 1 103250003Sadrian#define AR_TXCFG_DMASZ_16B 2 104250003Sadrian#define AR_TXCFG_DMASZ_32B 3 105250003Sadrian#define AR_TXCFG_DMASZ_64B 4 106250003Sadrian#define AR_TXCFG_DMASZ_128B 5 107250003Sadrian#define AR_TXCFG_DMASZ_256B 6 108250003Sadrian#define AR_TXCFG_DMASZ_512B 7 109250003Sadrian#define AR_FTRIG 0x000003F0 // Mask for Frame trigger level 110250003Sadrian#define AR_FTRIG_S 4 // Shift for Frame trigger level 111250003Sadrian#define AR_FTRIG_IMMED 0x00000000 // bytes in PCU TX FIFO before air 112250003Sadrian#define AR_FTRIG_64B 0x00000010 // default 113250003Sadrian#define AR_FTRIG_128B 0x00000020 114250003Sadrian#define AR_FTRIG_192B 0x00000030 115250003Sadrian#define AR_FTRIG_256B 0x00000040 // 5 bits total 116250003Sadrian#define AR_FTRIG_512B 0x00000080 // 5 bits total 117250003Sadrian#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 118250003Sadrian#define AR_TXCFG_RTS_FAIL_EXCESSIVE_RETRIES 0x00080000 119250003Sadrian#define AR_TXCFG_RTS_FAIL_EXCESSIVE_RETRIES_S 19 120250003Sadrian 121250003Sadrian/* MAC Rx DMA size config register */ 122250003Sadrian#define AR_RXCFG AR_MAC_DMA_OFFSET(MAC_DMA_RXCFG) 123250003Sadrian#define AR_RXCFG_CHIRP 0x00000008 // Only double chirps 124250003Sadrian#define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame 125250003Sadrian#define AR_RXCFG_DMASZ_MASK 0x00000007 126250003Sadrian#define AR_RXCFG_DMASZ_4B 0 127250003Sadrian#define AR_RXCFG_DMASZ_8B 1 128250003Sadrian#define AR_RXCFG_DMASZ_16B 2 129250003Sadrian#define AR_RXCFG_DMASZ_32B 3 130250003Sadrian#define AR_RXCFG_DMASZ_64B 4 131250003Sadrian#define AR_RXCFG_DMASZ_128B 5 132250003Sadrian#define AR_RXCFG_DMASZ_256B 6 133250003Sadrian#define AR_RXCFG_DMASZ_512B 7 134250003Sadrian 135250003Sadrian/* MAC Rx jumbo descriptor last address register */ 136250003Sadrian#define AR_RXJLA AR_MAC_DMA_OFFSET(MAC_DMA_RXJLA) 137250003Sadrian 138250003Sadrian 139250003Sadrian/* MAC MIB control register */ 140250003Sadrian#define AR_MIBC AR_MAC_DMA_OFFSET(MAC_DMA_MIBC) 141250003Sadrian#define AR_MIBC_COW 0x00000001 // counter overflow warning 142250003Sadrian#define AR_MIBC_FMC 0x00000002 // freeze MIB counters 143250003Sadrian#define AR_MIBC_CMC 0x00000004 // clear MIB counters 144250003Sadrian#define AR_MIBC_MCS 0x00000008 // MIB counter strobe increment all 145250003Sadrian 146250003Sadrian/* MAC timeout prescale count */ 147250003Sadrian#define AR_TOPS AR_MAC_DMA_OFFSET(MAC_DMA_TOPS) 148250003Sadrian#define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale 149250003Sadrian 150250003Sadrian/* MAC no frame received timeout */ 151250003Sadrian#define AR_RXNPTO AR_MAC_DMA_OFFSET(MAC_DMA_RXNPTO) 152250003Sadrian#define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout 153250003Sadrian 154250003Sadrian/* MAC no frame trasmitted timeout */ 155250003Sadrian#define AR_TXNPTO AR_MAC_DMA_OFFSET(MAC_DMA_TXNPTO) 156250003Sadrian#define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout 157250003Sadrian#define AR_TXNPTO_QCU_MASK 0x000FFC00 // Mask indicating the set of QCUs 158250003Sadrian // for which frame completions will cause 159250003Sadrian // a reset of the no frame transmitted timeout 160250003Sadrian 161250003Sadrian/* MAC receive frame gap timeout */ 162250003Sadrian#define AR_RPGTO AR_MAC_DMA_OFFSET(MAC_DMA_RPGTO) 163250003Sadrian#define AR_RPGTO_MASK 0x000003FF // Mask for receive frame gap timeout 164250003Sadrian 165250003Sadrian/* MAC miscellaneous control/status register */ 166250003Sadrian#define AR_MACMISC AR_MAC_DMA_OFFSET(MAC_DMA_MACMISC) 167250003Sadrian#define AR_MACMISC_PCI_EXT_FORCE 0x00000010 //force msb to 10 to ahb 168250003Sadrian#define AR_MACMISC_DMA_OBS 0x000001E0 // Mask for DMA observation bus mux select 169250003Sadrian#define AR_MACMISC_DMA_OBS_S 5 // Shift for DMA observation bus mux select 170250003Sadrian#define AR_MACMISC_DMA_OBS_LINE_0 0 // Observation DMA line 0 171250003Sadrian#define AR_MACMISC_DMA_OBS_LINE_1 1 // Observation DMA line 1 172250003Sadrian#define AR_MACMISC_DMA_OBS_LINE_2 2 // Observation DMA line 2 173250003Sadrian#define AR_MACMISC_DMA_OBS_LINE_3 3 // Observation DMA line 3 174250003Sadrian#define AR_MACMISC_DMA_OBS_LINE_4 4 // Observation DMA line 4 175250003Sadrian#define AR_MACMISC_DMA_OBS_LINE_5 5 // Observation DMA line 5 176250003Sadrian#define AR_MACMISC_DMA_OBS_LINE_6 6 // Observation DMA line 6 177250003Sadrian#define AR_MACMISC_DMA_OBS_LINE_7 7 // Observation DMA line 7 178250003Sadrian#define AR_MACMISC_DMA_OBS_LINE_8 8 // Observation DMA line 8 179250003Sadrian#define AR_MACMISC_MISC_OBS 0x00000E00 // Mask for MISC observation bus mux select 180250003Sadrian#define AR_MACMISC_MISC_OBS_S 9 // Shift for MISC observation bus mux select 181250003Sadrian#define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 // Mask for MAC observation bus mux select (lsb) 182250003Sadrian#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 // Shift for MAC observation bus mux select (lsb) 183250003Sadrian#define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 // Mask for MAC observation bus mux select (msb) 184250003Sadrian#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 // Shift for MAC observation bus mux select (msb) 185250003Sadrian#define AR_MACMISC_MISC_OBS_BUS_1 1 // MAC observation bus mux select 186250003Sadrian 187250003Sadrian/* MAC Interrupt Config register */ 188250003Sadrian#define AR_INTCFG AR_MAC_DMA_OFFSET(MAC_DMA_INTER) 189250003Sadrian#define AR_INTCFG_REQ 0x00000001 // Interrupt request flag 190250003Sadrian // Indicates whether the DMA engine should generate 191250003Sadrian // an interrupt upon completion of the frame 192250003Sadrian#define AR_INTCFG_MSI_RXOK 0x00000000 // Rx interrupt for MSI logic is RXOK 193250003Sadrian#define AR_INTCFG_MSI_RXINTM 0x00000004 // Rx interrupt for MSI logic is RXINTM 194250003Sadrian#define AR_INTCFG_MSI_RXMINTR 0x00000006 // Rx interrupt for MSI logic is RXMINTR 195250003Sadrian#define AR_INTCFG_MSI_TXOK 0x00000000 // Rx interrupt for MSI logic is TXOK 196250003Sadrian#define AR_INTCFG_MSI_TXINTM 0x00000010 // Rx interrupt for MSI logic is TXINTM 197250003Sadrian#define AR_INTCFG_MSI_TXMINTR 0x00000018 // Rx interrupt for MSI logic is TXMINTR 198250003Sadrian 199250003Sadrian/* MAC DMA Data Buffer length, in bytes */ 200250003Sadrian#define AR_DATABUF AR_MAC_DMA_OFFSET(MAC_DMA_DATABUF) 201250003Sadrian#define AR_DATABUF_MASK 0x00000FFF 202250003Sadrian 203250003Sadrian/* MAC global transmit timeout */ 204250003Sadrian#define AR_GTXTO AR_MAC_DMA_OFFSET(MAC_DMA_GTT) 205250003Sadrian#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 206250003Sadrian#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 207250003Sadrian#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 208250003Sadrian 209250003Sadrian/* MAC global transmit timeout mode */ 210250003Sadrian#define AR_GTTM AR_MAC_DMA_OFFSET(MAC_DMA_GTTM) 211250003Sadrian#define AR_GTTM_USEC 0x00000001 // usec strobe 212250003Sadrian#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 213250003Sadrian#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 214250003Sadrian#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 215250003Sadrian 216250003Sadrian/* MAC carrier sense timeout */ 217250003Sadrian#define AR_CST AR_MAC_DMA_OFFSET(MAC_DMA_CST) 218250003Sadrian#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 219250003Sadrian#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 220250003Sadrian#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 221250003Sadrian 222250003Sadrian/* MAC Indicates the size of High and Low priority rx_dp FIFOs */ 223250003Sadrian#define AR_RXDP_SIZE AR_MAC_DMA_OFFSET(MAC_DMA_RXDP_SIZE) 224250003Sadrian#define AR_RXDP_LP_SZ_MASK 0x0000007f 225250003Sadrian#define AR_RXDP_LP_SZ_S 0 226250003Sadrian#define AR_RXDP_HP_SZ_MASK 0x00001f00 227250003Sadrian#define AR_RXDP_HP_SZ_S 8 228250003Sadrian 229250003Sadrian/* MAC Rx High Priority Queue RXDP Pointer (lower 32 bits) */ 230250003Sadrian#define AR_HP_RXDP AR_MAC_DMA_OFFSET(MAC_DMA_RX_QUEUE_HP_RXDP) 231250003Sadrian 232250003Sadrian/* MAC Rx Low Priority Queue RXDP Pointer (lower 32 bits) */ 233250003Sadrian#define AR_LP_RXDP AR_MAC_DMA_OFFSET(MAC_DMA_RX_QUEUE_LP_RXDP) 234250003Sadrian 235250003Sadrian 236250003Sadrian/* Primary Interrupt Status Register */ 237250003Sadrian#define AR_ISR AR_MAC_DMA_OFFSET(MAC_DMA_ISR_P) 238250003Sadrian#define AR_ISR_HP_RXOK 0x00000001 // At least one frame rx on high-priority queue sans errors 239250003Sadrian#define AR_ISR_LP_RXOK 0x00000002 // At least one frame rx on low-priority queue sans errors 240250003Sadrian#define AR_ISR_RXERR 0x00000004 // Receive error interrupt 241250003Sadrian#define AR_ISR_RXNOPKT 0x00000008 // No frame received within timeout clock 242250003Sadrian#define AR_ISR_RXEOL 0x00000010 // Received descriptor empty interrupt 243250003Sadrian#define AR_ISR_RXORN 0x00000020 // Receive FIFO overrun interrupt 244250003Sadrian#define AR_ISR_TXOK 0x00000040 // Transmit okay interrupt 245250003Sadrian#define AR_ISR_TXERR 0x00000100 // Transmit error interrupt 246250003Sadrian#define AR_ISR_TXNOPKT 0x00000200 // No frame transmitted interrupt 247250003Sadrian#define AR_ISR_TXEOL 0x00000400 // Transmit descriptor empty interrupt 248250003Sadrian#define AR_ISR_TXURN 0x00000800 // Transmit FIFO underrun interrupt 249250003Sadrian#define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC 250250003Sadrian#define AR_ISR_SWI 0x00002000 // Software interrupt 251250003Sadrian#define AR_ISR_RXPHY 0x00004000 // PHY receive error interrupt 252250003Sadrian#define AR_ISR_RXKCM 0x00008000 // Key-cache miss interrupt 253250003Sadrian#define AR_ISR_SWBA 0x00010000 // Software beacon alert interrupt 254250003Sadrian#define AR_ISR_BRSSI 0x00020000 // Beacon threshold interrupt 255250003Sadrian#define AR_ISR_BMISS 0x00040000 // Beacon missed interrupt 256250003Sadrian#define AR_ISR_TXMINTR 0x00080000 // Maximum interrupt transmit rate 257250003Sadrian#define AR_ISR_BNR 0x00100000 // Beacon not ready interrupt 258250003Sadrian#define AR_ISR_RXCHIRP 0x00200000 // Phy received a 'chirp' 259250003Sadrian#define AR_ISR_HCFPOLL 0x00400000 // Received directed HCF poll 260250003Sadrian#define AR_ISR_BCNMISC 0x00800000 // CST, GTT, TIM, CABEND, DTIMSYNC, BCNTO, CABTO, 261250003Sadrian // TSFOOR, DTIM, and TBTT_TIME bits bits from ISR_S2 262250003Sadrian#define AR_ISR_TIM 0x00800000 // TIM interrupt 263250003Sadrian#define AR_ISR_RXMINTR 0x01000000 // Maximum interrupt receive rate 264250003Sadrian#define AR_ISR_QCBROVF 0x02000000 // QCU CBR overflow interrupt 265250003Sadrian#define AR_ISR_QCBRURN 0x04000000 // QCU CBR underrun interrupt 266250003Sadrian#define AR_ISR_QTRIG 0x08000000 // QCU scheduling trigger interrupt 267250003Sadrian#define AR_ISR_GENTMR 0x10000000 // OR of generic timer bits in ISR 5 268250003Sadrian#define AR_ISR_HCFTO 0x20000000 // HCF poll timeout 269250003Sadrian#define AR_ISR_TXINTM 0x40000000 // Tx interrupt after mitigation 270250003Sadrian#define AR_ISR_RXINTM 0x80000000 // Rx interrupt after mitigation 271250003Sadrian 272250003Sadrian/* MAC Secondary interrupt status register 0 */ 273250003Sadrian#define AR_ISR_S0 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S0) 274250003Sadrian#define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) 275250003Sadrian#define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) 276250003Sadrian 277250003Sadrian/* MAC Secondary interrupt status register 1 */ 278250003Sadrian#define AR_ISR_S1 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S1) 279250003Sadrian#define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) 280250003Sadrian#define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) 281250003Sadrian#define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) 282250003Sadrian#define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) 283250003Sadrian 284250003Sadrian/* MAC Secondary interrupt status register 2 */ 285250003Sadrian#define AR_ISR_S2 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S2) 286250003Sadrian#define AR_ISR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) 287250003Sadrian#define AR_ISR_S2_BBPANIC 0x00010000 // Panic watchdog IRQ from BB 288250003Sadrian#define AR_ISR_S2_CST 0x00400000 // Carrier sense timeout 289250003Sadrian#define AR_ISR_S2_GTT 0x00800000 // Global transmit timeout 290250003Sadrian#define AR_ISR_S2_TIM 0x01000000 // TIM 291250003Sadrian#define AR_ISR_S2_CABEND 0x02000000 // CABEND 292250003Sadrian#define AR_ISR_S2_DTIMSYNC 0x04000000 // DTIMSYNC 293250003Sadrian#define AR_ISR_S2_BCNTO 0x08000000 // BCNTO 294250003Sadrian#define AR_ISR_S2_CABTO 0x10000000 // CABTO 295250003Sadrian#define AR_ISR_S2_DTIM 0x20000000 // DTIM 296250003Sadrian#define AR_ISR_S2_TSFOOR 0x40000000 // Rx TSF out of range 297250003Sadrian#define AR_ISR_S2_TBTT_TIME 0x80000000 // TBTT-referenced timer 298250003Sadrian 299250003Sadrian/* MAC Secondary interrupt status register 3 */ 300250003Sadrian#define AR_ISR_S3 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S3) 301250003Sadrian#define AR_ISR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) 302250003Sadrian#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) 303250003Sadrian 304250003Sadrian/* MAC Secondary interrupt status register 4 */ 305250003Sadrian#define AR_ISR_S4 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S4) 306250003Sadrian#define AR_ISR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) 307250003Sadrian#define AR_ISR_S4_RESV0 0xFFFFFC00 // Reserved 308250003Sadrian 309250003Sadrian/* MAC Secondary interrupt status register 5 */ 310250003Sadrian#define AR_ISR_S5 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S5) 311250003Sadrian#define AR_ISR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) 312250003Sadrian#define AR_ISR_S5_TIMER_THRESH 0x0007FE00 // Mask for timer threshold(0-7) 313250003Sadrian#define AR_ISR_S5_TIM_TIMER 0x00000010 // TIM Timer ISR 314250003Sadrian#define AR_ISR_S5_DTIM_TIMER 0x00000020 // DTIM Timer ISR 315250003Sadrian#define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 // ISR for generic timer trigger 7 316250003Sadrian#define AR_ISR_S5_GENTIMER_TRIG_S 0 317250003Sadrian#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 // ISR for generic timer threshold 7 318250003Sadrian#define AR_ISR_S5_GENTIMER_THRESH_S 16 319250003Sadrian 320250003Sadrian/* Primary Interrupt Mask Register */ 321250003Sadrian#define AR_IMR AR_MAC_DMA_OFFSET(MAC_DMA_IMR_P) 322250003Sadrian#define AR_IMR_RXOK_HP 0x00000001 // Receive high-priority interrupt enable mask 323250003Sadrian#define AR_IMR_RXOK_LP 0x00000002 // Receive low-priority interrupt enable mask 324250003Sadrian#define AR_IMR_RXERR 0x00000004 // Receive error interrupt 325250003Sadrian#define AR_IMR_RXNOPKT 0x00000008 // No frame received within timeout clock 326250003Sadrian#define AR_IMR_RXEOL 0x00000010 // Received descriptor empty interrupt 327250003Sadrian#define AR_IMR_RXORN 0x00000020 // Receive FIFO overrun interrupt 328250003Sadrian#define AR_IMR_TXOK 0x00000040 // Transmit okay interrupt 329250003Sadrian#define AR_IMR_TXERR 0x00000100 // Transmit error interrupt 330250003Sadrian#define AR_IMR_TXNOPKT 0x00000200 // No frame transmitted interrupt 331250003Sadrian#define AR_IMR_TXEOL 0x00000400 // Transmit descriptor empty interrupt 332250003Sadrian#define AR_IMR_TXURN 0x00000800 // Transmit FIFO underrun interrupt 333250003Sadrian#define AR_IMR_MIB 0x00001000 // MIB interrupt - see MIBC 334250003Sadrian#define AR_IMR_SWI 0x00002000 // Software interrupt 335250003Sadrian#define AR_IMR_RXPHY 0x00004000 // PHY receive error interrupt 336250003Sadrian#define AR_IMR_RXKCM 0x00008000 // Key-cache miss interrupt 337250003Sadrian#define AR_IMR_SWBA 0x00010000 // Software beacon alert interrupt 338250003Sadrian#define AR_IMR_BRSSI 0x00020000 // Beacon threshold interrupt 339250003Sadrian#define AR_IMR_BMISS 0x00040000 // Beacon missed interrupt 340250003Sadrian#define AR_IMR_TXMINTR 0x00080000 // Maximum interrupt transmit rate 341250003Sadrian#define AR_IMR_BNR 0x00100000 // BNR interrupt 342250003Sadrian#define AR_IMR_RXCHIRP 0x00200000 // RXCHIRP interrupt 343250003Sadrian#define AR_IMR_BCNMISC 0x00800000 // Venice: BCNMISC 344250003Sadrian#define AR_IMR_TIM 0x00800000 // TIM interrupt 345250003Sadrian#define AR_IMR_RXMINTR 0x01000000 // Maximum interrupt receive rate 346250003Sadrian#define AR_IMR_QCBROVF 0x02000000 // QCU CBR overflow interrupt 347250003Sadrian#define AR_IMR_QCBRURN 0x04000000 // QCU CBR underrun interrupt 348250003Sadrian#define AR_IMR_QTRIG 0x08000000 // QCU scheduling trigger interrupt 349250003Sadrian#define AR_IMR_GENTMR 0x10000000 // Generic timer interrupt 350250003Sadrian#define AR_IMR_TXINTM 0x40000000 // Tx interrupt after mitigation 351250003Sadrian#define AR_IMR_RXINTM 0x80000000 // Rx interrupt after mitigation 352250003Sadrian 353250003Sadrian/* MAC Secondary interrupt mask register 0 */ 354250003Sadrian#define AR_IMR_S0 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S0) 355250003Sadrian#define AR_IMR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) 356250003Sadrian#define AR_IMR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) 357250003Sadrian 358250003Sadrian/* MAC Secondary interrupt mask register 1 */ 359250003Sadrian#define AR_IMR_S1 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S1) 360250003Sadrian#define AR_IMR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) 361250003Sadrian#define AR_IMR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) 362250003Sadrian#define AR_IMR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) 363250003Sadrian#define AR_IMR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) 364250003Sadrian 365250003Sadrian/* MAC Secondary interrupt mask register 2 */ 366250003Sadrian#define AR_IMR_S2 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S2) 367250003Sadrian#define AR_IMR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) 368250003Sadrian#define AR_IMR_S2_QCU_TXURN_S 0 // Shift for TXURN (QCU 0-9) 369250003Sadrian#define AR_IMR_S2_BBPANIC 0x00010000 // Panic watchdog IRQ from BB 370250003Sadrian#define AR_IMR_S2_CST 0x00400000 // Carrier sense timeout 371250003Sadrian#define AR_IMR_S2_GTT 0x00800000 // Global transmit timeout 372250003Sadrian#define AR_IMR_S2_TIM 0x01000000 // TIM 373250003Sadrian#define AR_IMR_S2_CABEND 0x02000000 // CABEND 374250003Sadrian#define AR_IMR_S2_DTIMSYNC 0x04000000 // DTIMSYNC 375250003Sadrian#define AR_IMR_S2_BCNTO 0x08000000 // BCNTO 376250003Sadrian#define AR_IMR_S2_CABTO 0x10000000 // CABTO 377250003Sadrian#define AR_IMR_S2_DTIM 0x20000000 // DTIM 378250003Sadrian#define AR_IMR_S2_TSFOOR 0x40000000 // TSF out of range 379250003Sadrian 380250003Sadrian/* MAC Secondary interrupt mask register 3 */ 381250003Sadrian#define AR_IMR_S3 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S3) 382250003Sadrian#define AR_IMR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) 383250003Sadrian#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) 384250003Sadrian#define AR_IMR_S3_QCU_QCBRURN_S 16 // Shift for QCBRURN (QCU 0-9) 385250003Sadrian 386250003Sadrian/* MAC Secondary interrupt mask register 4 */ 387250003Sadrian#define AR_IMR_S4 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S4) 388250003Sadrian#define AR_IMR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) 389250003Sadrian#define AR_IMR_S4_RESV0 0xFFFFFC00 // Reserved 390250003Sadrian 391250003Sadrian/* MAC Secondary interrupt mask register 5 */ 392250003Sadrian#define AR_IMR_S5 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S5) 393250003Sadrian#define AR_IMR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) 394250003Sadrian#define AR_IMR_S5_TIMER_THRESH 0x0000FF00 // Mask for timer threshold(0-7) 395250003Sadrian#define AR_IMR_S5_TIM_TIMER 0x00000010 // TIM Timer Mask 396250003Sadrian#define AR_IMR_S5_DTIM_TIMER 0x00000020 // DTIM Timer Mask 397250003Sadrian#define AR_IMR_S5_GENTIMER7 0x00000080 // Mask for timer 7 trigger 398250003Sadrian#define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 // Mask for generic timer trigger 7-15 399250003Sadrian#define AR_IMR_S5_GENTIMER_TRIG_S 0 400250003Sadrian#define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 // Mask for generic timer threshold 7-15 401250003Sadrian#define AR_IMR_S5_GENTIMER_THRESH_S 16 402250003Sadrian 403250003Sadrian 404250003Sadrian/* Interrupt status registers (read-and-clear access secondary shadow copies) */ 405250003Sadrian 406250003Sadrian/* MAC Primary interrupt status register read-and-clear access */ 407250003Sadrian#define AR_ISR_RAC AR_MAC_DMA_OFFSET(MAC_DMA_ISR_P_RAC) 408250003Sadrian/* MAC Secondary interrupt status register 0 - shadow copy */ 409250003Sadrian#define AR_ISR_S0_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S0_S) 410250003Sadrian#define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) 411250003Sadrian#define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) 412250003Sadrian 413250003Sadrian/* MAC Secondary interrupt status register 1 - shadow copy */ 414250003Sadrian#define AR_ISR_S1_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S1_S) 415250003Sadrian#define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) 416250003Sadrian#define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) 417250003Sadrian#define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) 418250003Sadrian#define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) 419250003Sadrian 420250003Sadrian/* MAC Secondary interrupt status register 2 - shadow copy */ 421250003Sadrian#define AR_ISR_S2_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S2_S) 422250003Sadrian/* MAC Secondary interrupt status register 3 - shadow copy */ 423250003Sadrian#define AR_ISR_S3_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S3_S) 424250003Sadrian/* MAC Secondary interrupt status register 4 - shadow copy */ 425250003Sadrian#define AR_ISR_S4_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S4_S) 426250003Sadrian/* MAC Secondary interrupt status register 5 - shadow copy */ 427250003Sadrian#define AR_ISR_S5_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S5_S) 428250003Sadrian 429250003Sadrian/* MAC DMA Debug Registers */ 430250003Sadrian#define AR_DMADBG_0 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_0) 431250003Sadrian#define AR_DMADBG_1 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_1) 432250003Sadrian#define AR_DMADBG_2 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_2) 433250003Sadrian#define AR_DMADBG_3 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_3) 434250003Sadrian#define AR_DMADBG_4 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_4) 435250003Sadrian#define AR_DMADBG_5 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_5) 436250003Sadrian#define AR_DMADBG_6 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_6) 437250003Sadrian#define AR_DMADBG_7 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_7) 438250003Sadrian#define AR_DMATXDP_QCU_7_0 AR_MAC_DMA_OFFSET(MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0) 439250003Sadrian#define AR_DMATXDP_QCU_9_8 AR_MAC_DMA_OFFSET(MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8) 440250003Sadrian 441250003Sadrian#define AR_DMADBG_RX_STATE 0x00000F00 // Mask for Rx DMA State machine 442250003Sadrian 443250003Sadrian 444250003Sadrian/* 445250003Sadrian * MAC QCU Registers 446250003Sadrian */ 447250003Sadrian#define AR_MAC_QCU_OFFSET(_x) offsetof(struct mac_qcu_reg, _x) 448250003Sadrian 449250003Sadrian#define AR_NUM_QCU 10 // Only use QCU 0-9 for forward QCU compatibility 450250003Sadrian#define AR_QCU_0 0x0001 451250003Sadrian#define AR_QCU_1 0x0002 452250003Sadrian#define AR_QCU_2 0x0004 453250003Sadrian#define AR_QCU_3 0x0008 454250003Sadrian#define AR_QCU_4 0x0010 455250003Sadrian#define AR_QCU_5 0x0020 456250003Sadrian#define AR_QCU_6 0x0040 457250003Sadrian#define AR_QCU_7 0x0080 458250003Sadrian#define AR_QCU_8 0x0100 459250003Sadrian#define AR_QCU_9 0x0200 460250003Sadrian 461250003Sadrian/* MAC Transmit Queue descriptor pointer */ 462250003Sadrian#define AR_Q0_TXDP AR_MAC_QCU_OFFSET(MAC_QCU_TXDP) 463250003Sadrian#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) 464250003Sadrian 465250003Sadrian/* MAC Transmit Status Ring Start Address */ 466250003Sadrian#define AR_Q_STATUS_RING_START AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_START) 467250003Sadrian/* MAC Transmit Status Ring End Address */ 468250003Sadrian#define AR_Q_STATUS_RING_END AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_END) 469250003Sadrian/* Current Address in the Transmit Status Ring pointed to by the MAC */ 470250003Sadrian#define AR_Q_STATUS_RING_CURRENT AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_CURRENT) 471250003Sadrian 472250003Sadrian/* MAC Transmit Queue enable */ 473250003Sadrian#define AR_Q_TXE AR_MAC_QCU_OFFSET(MAC_QCU_TXE) 474250003Sadrian#define AR_Q_TXE_M 0x000003FF // Mask for TXE (QCU 0-9) 475250003Sadrian 476250003Sadrian/* MAC Transmit Queue disable */ 477250003Sadrian#define AR_Q_TXD AR_MAC_QCU_OFFSET(MAC_QCU_TXD) 478250003Sadrian#define AR_Q_TXD_M 0x000003FF // Mask for TXD (QCU 0-9) 479250003Sadrian 480250003Sadrian/* MAC CBR configuration */ 481250003Sadrian#define AR_Q0_CBRCFG AR_MAC_QCU_OFFSET(MAC_QCU_CBR) 482250003Sadrian#define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) 483250003Sadrian#define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF // Mask for CBR interval (us) 484250003Sadrian#define AR_Q_CBRCFG_INTERVAL_S 0 // Shift for CBR interval (us) 485250003Sadrian#define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 // Mask for CBR overflow threshold 486250003Sadrian#define AR_Q_CBRCFG_OVF_THRESH_S 24 // Shift for CBR overflow threshold 487250003Sadrian 488250003Sadrian/* MAC ready_time configuration */ 489250003Sadrian#define AR_Q0_RDYTIMECFG AR_MAC_QCU_OFFSET(MAC_QCU_RDYTIME) 490250003Sadrian#define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) 491250003Sadrian#define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF // Mask for ready_time duration (us) 492250003Sadrian#define AR_Q_RDYTIMECFG_DURATION_S 0 // Shift for ready_time duration (us) 493250003Sadrian#define AR_Q_RDYTIMECFG_EN 0x01000000 // ready_time enable 494250003Sadrian 495250003Sadrian/* MAC OneShotArm set control */ 496250003Sadrian#define AR_Q_ONESHOTARM_SC AR_MAC_QCU_OFFSET(MAC_QCU_ONESHOT_ARM_SC) 497250003Sadrian#define AR_Q_ONESHOTARM_SC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_SC (QCU 0-9) 498250003Sadrian#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 // Reserved 499250003Sadrian 500250003Sadrian/* MAC OneShotArm clear control */ 501250003Sadrian#define AR_Q_ONESHOTARM_CC AR_MAC_QCU_OFFSET(MAC_QCU_ONESHOT_ARM_CC) 502250003Sadrian#define AR_Q_ONESHOTARM_CC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_CC (QCU 0-9) 503250003Sadrian#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 // Reserved 504250003Sadrian 505250003Sadrian/* MAC Miscellaneous QCU settings */ 506250003Sadrian#define AR_Q0_MISC AR_MAC_QCU_OFFSET(MAC_QCU_MISC) 507250003Sadrian#define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) 508250003Sadrian#define AR_Q_MISC_FSP 0x0000000F // Mask for Frame Scheduling Policy 509301640Sadrian#define AR_Q_MISC_FSP_S 0 510250003Sadrian#define AR_Q_MISC_FSP_ASAP 0 // ASAP 511250003Sadrian#define AR_Q_MISC_FSP_CBR 1 // CBR 512250003Sadrian#define AR_Q_MISC_FSP_DBA_GATED 2 // DMA Beacon Alert gated 513250003Sadrian#define AR_Q_MISC_FSP_TIM_GATED 3 // TIM gated 514250003Sadrian#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 // Beacon-sent-gated 515250003Sadrian#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 // Beacon-received-gated 516250003Sadrian#define AR_Q_MISC_ONE_SHOT_EN 0x00000010 // OneShot enable 517250003Sadrian#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 // Disable CBR expired counter incr (empty q) 518250003Sadrian#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 // Disable CBR expired counter incr (empty beacon q) 519250003Sadrian#define AR_Q_MISC_BEACON_USE 0x00000080 // Beacon use indication 520250003Sadrian#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 // CBR expired counter limit enable 521250003Sadrian#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 // Enable TXE cleared on ready_time expired or VEOL 522250003Sadrian#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 // Reset CBR expired counter 523250003Sadrian#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 // DCU frame early termination request control 524250003Sadrian#define AR_Q_MISC_RESV0 0xFFFFF000 // Reserved 525250003Sadrian 526250003Sadrian/* MAC Miscellaneous QCU status */ 527250003Sadrian#define AR_Q0_STS AR_MAC_QCU_OFFSET(MAC_QCU_CNT) 528250003Sadrian#define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) 529250003Sadrian#define AR_Q_STS_PEND_FR_CNT 0x00000003 // Mask for Pending Frame Count 530250003Sadrian#define AR_Q_STS_RESV0 0x000000FC // Reserved 531250003Sadrian#define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 // Mask for CBR expired counter 532250003Sadrian#define AR_Q_STS_RESV1 0xFFFF0000 // Reserved 533250003Sadrian 534250003Sadrian/* MAC ReadyTimeShutdown status */ 535250003Sadrian#define AR_Q_RDYTIMESHDN AR_MAC_QCU_OFFSET(MAC_QCU_RDYTIME_SHDN) 536250003Sadrian#define AR_Q_RDYTIMESHDN_M 0x000003FF // Mask for ReadyTimeShutdown status (QCU 0-9) 537250003Sadrian 538250003Sadrian/* MAC Descriptor CRC check */ 539250003Sadrian#define AR_Q_DESC_CRCCHK AR_MAC_QCU_OFFSET(MAC_QCU_DESC_CRC_CHK) 540250003Sadrian#define AR_Q_DESC_CRCCHK_EN 1 // Enable CRC check on the descriptor fetched from HOST 541250003Sadrian 542250003Sadrian#define AR_MAC_QCU_EOL AR_MAC_QCU_OFFSET(MAC_QCU_EOL) 543250003Sadrian#define AR_MAC_QCU_EOL_DUR_CAL_EN 0x000003FF // Adjusts EOL for frame duration (QCU 0-9) 544250003Sadrian#define AR_MAC_QCU_EOL_DUR_CAL_EN_S 0 545250003Sadrian 546250003Sadrian/* 547250003Sadrian * MAC DCU Registers 548250003Sadrian */ 549250003Sadrian 550250003Sadrian#define AR_MAC_DCU_OFFSET(_x) offsetof(struct mac_dcu_reg, _x) 551250003Sadrian 552250003Sadrian#define AR_NUM_DCU 10 // Only use 10 DCU's for forward QCU/DCU compatibility 553250003Sadrian#define AR_DCU_0 0x0001 554250003Sadrian#define AR_DCU_1 0x0002 555250003Sadrian#define AR_DCU_2 0x0004 556250003Sadrian#define AR_DCU_3 0x0008 557250003Sadrian#define AR_DCU_4 0x0010 558250003Sadrian#define AR_DCU_5 0x0020 559250003Sadrian#define AR_DCU_6 0x0040 560250003Sadrian#define AR_DCU_7 0x0080 561250003Sadrian#define AR_DCU_8 0x0100 562250003Sadrian#define AR_DCU_9 0x0200 563250003Sadrian 564250003Sadrian/* MAC QCU Mask */ 565250003Sadrian#define AR_D0_QCUMASK AR_MAC_DCU_OFFSET(MAC_DCU_QCUMASK) 566250003Sadrian#define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) 567250003Sadrian#define AR_D_QCUMASK 0x000003FF // Mask for QCU Mask (QCU 0-9) 568250003Sadrian#define AR_D_QCUMASK_RESV0 0xFFFFFC00 // Reserved 569250003Sadrian 570250003Sadrian/* DCU transmit filter cmd (w/only) */ 571250003Sadrian#define AR_D_TXBLK_CMD AR_MAC_DCU_OFFSET(MAC_DCU_TXFILTER_DCU0_31_0) 572250003Sadrian#define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) // DCU transmit filter data 573250003Sadrian 574250003Sadrian 575250003Sadrian/* MAC DCU-global IFS settings: SIFS duration */ 576250003Sadrian#define AR_D_GBL_IFS_SIFS AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_SIFS) 577250003Sadrian#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF // Mask for SIFS duration (core clocks) 578250003Sadrian#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF // Reserved 579250003Sadrian 580250003Sadrian/* MAC DCU-global IFS settings: slot duration */ 581250003Sadrian#define AR_D_GBL_IFS_SLOT AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_SLOT) 582250003Sadrian#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF // Mask for Slot duration (core clocks) 583250003Sadrian#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 // Reserved 584250003Sadrian 585250003Sadrian/* MAC Retry limits */ 586250003Sadrian#define AR_D0_RETRY_LIMIT AR_MAC_DCU_OFFSET(MAC_DCU_RETRY_LIMIT) 587250003Sadrian#define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) 588250003Sadrian#define AR_D_RETRY_LIMIT_FR_SH 0x0000000F // Mask for frame short retry limit 589250003Sadrian#define AR_D_RETRY_LIMIT_FR_SH_S 0 // Shift for frame short retry limit 590250003Sadrian#define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 // Mask for station short retry limit 591250003Sadrian#define AR_D_RETRY_LIMIT_STA_SH_S 8 // Shift for station short retry limit 592250003Sadrian#define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 // Mask for station short retry limit 593250003Sadrian#define AR_D_RETRY_LIMIT_STA_LG_S 14 // Shift for station short retry limit 594250003Sadrian#define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 // Reserved 595250003Sadrian 596250003Sadrian/* MAC DCU-global IFS settings: EIFS duration */ 597250003Sadrian#define AR_D_GBL_IFS_EIFS AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_EIFS) 598250003Sadrian#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF // Mask for Slot duration (core clocks) 599250003Sadrian#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 // Reserved 600250003Sadrian 601250003Sadrian/* MAC ChannelTime settings */ 602250003Sadrian#define AR_D0_CHNTIME AR_MAC_DCU_OFFSET(MAC_DCU_CHANNEL_TIME) 603250003Sadrian#define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) 604250003Sadrian#define AR_D_CHNTIME_DUR 0x000FFFFF // Mask for ChannelTime duration (us) 605250003Sadrian#define AR_D_CHNTIME_DUR_S 0 // Shift for ChannelTime duration (us) 606250003Sadrian#define AR_D_CHNTIME_EN 0x00100000 // ChannelTime enable 607250003Sadrian#define AR_D_CHNTIME_RESV0 0xFFE00000 // Reserved 608250003Sadrian 609250003Sadrian/* MAC DCU-global IFS settings: Miscellaneous */ 610250003Sadrian#define AR_D_GBL_IFS_MISC AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_MISC) 611250003Sadrian#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 // Mask forLFSR slice select 612250003Sadrian#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 // Turbo mode indication 613250003Sadrian#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 // Mask for DCU arbiter delay 614250003Sadrian#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 // Random LSFR slice disable 615250003Sadrian#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 // Slot transmission window length mask 616250003Sadrian#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 // Force transmission on slot boundaries 617250003Sadrian#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 // Ignore backoff 618250003Sadrian 619250003Sadrian/* MAC Miscellaneous DCU-specific settings */ 620250003Sadrian#define AR_D0_MISC AR_MAC_DCU_OFFSET(MAC_DCU_MISC) 621250003Sadrian#define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) 622250003Sadrian#define AR_D_MISC_BKOFF_THRESH 0x0000003F // Mask for Backoff threshold setting 623250003Sadrian#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 // End of tx series station RTS/data failure count reset policy 624250003Sadrian#define AR_D_MISC_CW_RESET_EN 0x00000080 // End of tx series CW reset enable 625250003Sadrian#define AR_D_MISC_FRAG_WAIT_EN 0x00000100 // Fragment Starvation Policy 626250003Sadrian#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 // Backoff during a frag burst 627250003Sadrian#define AR_D_MISC_CW_BKOFF_EN 0x00001000 // Use binary exponential CW backoff 628250003Sadrian#define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 // Mask for Virtual collision handling policy 629250003Sadrian#define AR_D_MISC_VIR_COL_HANDLING_S 14 // Shift for Virtual collision handling policy 630250003Sadrian#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 // Normal 631250003Sadrian#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 // Ignore 632250003Sadrian#define AR_D_MISC_BEACON_USE 0x00010000 // Beacon use indication 633250003Sadrian#define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 // Mask for DCU arbiter lockout control 634250003Sadrian#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 // Shift for DCU arbiter lockout control 635250003Sadrian#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 // No lockout 636250003Sadrian#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 // Intra-frame 637250003Sadrian#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 // Global 638250003Sadrian#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 // DCU arbiter lockout ignore control 639250003Sadrian#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 // Sequence number increment disable 640250003Sadrian#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 // Post-frame backoff disable 641250003Sadrian#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 // Virtual coll. handling policy 642250003Sadrian#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 // Initiate Retry procedure on Blown IFS 643250003Sadrian#define AR_D_MISC_RESV0 0xFF000000 // Reserved 644250003Sadrian 645250003Sadrian/* MAC Frame sequence number control/status */ 646250003Sadrian#define AR_D_SEQNUM AR_MAC_DCU_OFFSET(MAC_DCU_SEQ) 647250003Sadrian 648250003Sadrian/* MAC DCU transmit pause control/status */ 649250003Sadrian#define AR_D_TXPSE AR_MAC_DCU_OFFSET(MAC_DCU_PAUSE) 650250003Sadrian#define AR_D_TXPSE_CTRL 0x000003FF // Mask of DCUs to pause (DCUs 0-9) 651250003Sadrian#define AR_D_TXPSE_RESV0 0x0000FC00 // Reserved 652250003Sadrian#define AR_D_TXPSE_STATUS 0x00010000 // Transmit pause status 653250003Sadrian#define AR_D_TXPSE_RESV1 0xFFFE0000 // Reserved 654250003Sadrian 655250003Sadrian/* MAC DCU WOW Keep-Alive Config register */ 656250003Sadrian#define AR_D_WOW_KACFG AR_MAC_DCU_OFFSET(MAC_DCU_WOW_KACFG) 657250003Sadrian 658250003Sadrian/* MAC DCU transmission slot mask */ 659250003Sadrian#define AR_D_TXSLOTMASK AR_MAC_DCU_OFFSET(MAC_DCU_TXSLOT) 660250003Sadrian#define AR_D_TXSLOTMASK_NUM 0x0000000F // slot numbers 661250003Sadrian 662250003Sadrian/* MAC DCU-specific IFS settings */ 663250003Sadrian#define AR_D0_LCL_IFS AR_MAC_DCU_OFFSET(MAC_DCU_LCL_IFS) 664250003Sadrian#define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) 665250003Sadrian#define AR_D9_LCL_IFS AR_DLCL_IFS(9) 666250003Sadrian#define AR_D_LCL_IFS_CWMIN 0x000003FF // Mask for CW_MIN 667250003Sadrian#define AR_D_LCL_IFS_CWMIN_S 0 // Shift for CW_MIN 668250003Sadrian#define AR_D_LCL_IFS_CWMAX 0x000FFC00 // Mask for CW_MAX 669250003Sadrian#define AR_D_LCL_IFS_CWMAX_S 10 // Shift for CW_MAX 670250003Sadrian#define AR_D_LCL_IFS_AIFS 0x0FF00000 // Mask for AIFS 671250003Sadrian#define AR_D_LCL_IFS_AIFS_S 20 // Shift for AIFS 672250003Sadrian /* 673250003Sadrian * Note: even though this field is 8 bits wide the 674250003Sadrian * maximum supported AIFS value is 0xfc. Setting the AIFS value 675250003Sadrian * to 0xfd 0xfe or 0xff will not work correctly and will cause 676250003Sadrian * the DCU to hang. 677250003Sadrian */ 678250003Sadrian#define AR_D_LCL_IFS_RESV0 0xF0000000 // Reserved 679250003Sadrian 680250003Sadrian 681250003Sadrian#define AR_CFG_LED 0x1f04 /* LED control */ 682250003Sadrian#define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ 683250003Sadrian#define AR_CFG_SCLK_RATE_IND_S 0 684250003Sadrian#define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ 685250003Sadrian#define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ 686250003Sadrian#define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ 687250003Sadrian#define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ 688250003Sadrian#define AR_CFG_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 689250003Sadrian#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 690250003Sadrian#define AR_CFG_LED_MODE_SEL 0x00000380 /* LED mode: bits 7..9 */ 691250003Sadrian#define AR_CFG_LED_MODE_SEL_S 7 /* LED mode: bits 7..9 */ 692250003Sadrian#define AR_CFG_LED_POWER 0x00000280 /* Power LED: bit 9=1, bit 7=<LED State> */ 693250003Sadrian#define AR_CFG_LED_POWER_S 7 /* LED mode: bits 7..9 */ 694250003Sadrian#define AR_CFG_LED_NETWORK 0x00000300 /* Network LED: bit 9=1, bit 8=<LED State> */ 695250003Sadrian#define AR_CFG_LED_NETWORK_S 7 /* LED mode: bits 7..9 */ 696250003Sadrian#define AR_CFG_LED_MODE_PROP 0x0 /* Blink prop to filtered tx/rx */ 697250003Sadrian#define AR_CFG_LED_MODE_RPROP 0x1 /* Blink prop to unfiltered tx/rx */ 698250003Sadrian#define AR_CFG_LED_MODE_SPLIT 0x2 /* Blink power for tx/net for rx */ 699250003Sadrian#define AR_CFG_LED_MODE_RAND 0x3 /* Blink randomly */ 700250003Sadrian#define AR_CFG_LED_MODE_POWER_OFF 0x4 /* Power LED OFF */ 701250003Sadrian#define AR_CFG_LED_MODE_POWER_ON 0x5 /* Power LED ON */ 702250003Sadrian#define AR_CFG_LED_MODE_NETWORK_OFF 0x4 /* Network LED OFF */ 703250003Sadrian#define AR_CFG_LED_MODE_NETWORK_ON 0x6 /* Network LED ON */ 704250003Sadrian#define AR_CFG_LED_ASSOC_CTL 0x00000c00 /* LED control: bits 10..11 */ 705250003Sadrian#define AR_CFG_LED_ASSOC_CTL_S 10 /* LED control: bits 10..11 */ 706250003Sadrian#define AR_CFG_LED_ASSOC_NONE 0x0 /* 0x00000000: STA is not associated or trying */ 707250003Sadrian#define AR_CFG_LED_ASSOC_ACTIVE 0x1 /* 0x00000400: STA is associated */ 708250003Sadrian#define AR_CFG_LED_ASSOC_PENDING 0x2 /* 0x00000800: STA is trying to associate */ 709250003Sadrian 710250003Sadrian#define AR_CFG_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode: bit 3 */ 711250003Sadrian#define AR_CFG_LED_BLINK_SLOW_S 3 /* LED slowest blink rate mode: bit 3 */ 712250003Sadrian 713250003Sadrian#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select: bits 4..6 */ 714250003Sadrian#define AR_CFG_LED_BLINK_THRESH_SEL_S 4 /* LED blink threshold select: bits 4..6 */ 715250003Sadrian 716250003Sadrian#define AR_MAC_SLEEP 0x1f00 717250003Sadrian#define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 // mac is now awake 718250003Sadrian#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 // mac is now asleep 719250003Sadrian 720250003Sadrian 721250003Sadrian 722250003Sadrian/****************************************************************************** 723250003Sadrian * Host Interface Register Map 724250003Sadrian******************************************************************************/ 725250003Sadrian// DMA & PCI Registers in PCI space (usable during sleep) 726250003Sadrian 727250003Sadrian#define AR_HOSTIF_REG(_ah, _reg) (AH9300(_ah)->ah_hostifregs._reg) 728250003Sadrian#define AR9300_HOSTIF_OFFSET(_x) offsetof(struct host_intf_reg, _x) 729250003Sadrian#define AR9340_HOSTIF_OFFSET(_x) offsetof(struct host_intf_reg_ar9340, _x) 730250003Sadrian 731250003Sadrian/* Interface Reset Control Register */ 732250003Sadrian#define AR_RC_AHB 0x00000001 // ahb reset 733250003Sadrian#define AR_RC_APB 0x00000002 // apb reset 734250003Sadrian#define AR_RC_HOSTIF 0x00000100 // host interface reset 735250003Sadrian 736250003Sadrian/* PCI express work-arounds */ 737250003Sadrian#define AR_WA_D3_TO_L1_DISABLE (1 << 14) 738250003Sadrian#define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset to POR (power-on-reset) */ 739250003Sadrian#define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16) 740250003Sadrian#define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17) 741250003Sadrian#define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */ 742250003Sadrian#define AR_WA_ANALOG_SHIFT (1 << 20) 743250003Sadrian#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ 744250003Sadrian#define AR_WA_COLD_RESET_OVERRIDE (1 << 13) /* PCI-E Cold reset override */ 745250003Sadrian 746250003Sadrian/* power management state */ 747250003Sadrian#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 //for wow 748250003Sadrian 749250003Sadrian/* CXPL Debug signals which help debug Link Negotiation */ 750250003Sadrian/* CXPL Debug signals which help debug Link Negotiation */ 751250003Sadrian 752250003Sadrian/* XXX check bit feilds */ 753250003Sadrian/* Power Management Control Register */ 754250003Sadrian#define AR_PCIE_PM_CTRL_ENA 0x00080000 755250003Sadrian#define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */ 756250003Sadrian#define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW event */ 757250003Sadrian#define AR_PMCTRL_D3COLD_VAUX 0x00800000 758250003Sadrian#define AR_PMCTRL_PWR_STATE_MASK 0x0F000000 /* Power State Mask */ 759250003Sadrian#define AR_PMCTRL_PWR_STATE_D1D3 0x0F000000 /* Activate D1 and D3 */ 760250003Sadrian#define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */ 761250003Sadrian#define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power management */ 762250003Sadrian#define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */ 763250003Sadrian 764250003Sadrian 765250003Sadrian 766250003Sadrian/* APB and Local Bus Timeout Counters */ 767250003Sadrian#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF 768250003Sadrian#define AR_HOST_TIMEOUT_APB_CNTR_S 0 769250003Sadrian#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 770250003Sadrian#define AR_HOST_TIMEOUT_LCL_CNTR_S 16 771250003Sadrian 772250003Sadrian/* EEPROM Control Register */ 773250003Sadrian#define AR_EEPROM_ABSENT 0x00000100 774250003Sadrian#define AR_EEPROM_CORRUPT 0x00000200 775250003Sadrian#define AR_EEPROM_PROT_MASK 0x03FFFC00 776250003Sadrian#define AR_EEPROM_PROT_MASK_S 10 777250003Sadrian 778250003Sadrian// Protect Bits RP is read protect WP is write protect 779250003Sadrian#define EEPROM_PROTECT_RP_0_31 0x0001 780250003Sadrian#define EEPROM_PROTECT_WP_0_31 0x0002 781250003Sadrian#define EEPROM_PROTECT_RP_32_63 0x0004 782250003Sadrian#define EEPROM_PROTECT_WP_32_63 0x0008 783250003Sadrian#define EEPROM_PROTECT_RP_64_127 0x0010 784250003Sadrian#define EEPROM_PROTECT_WP_64_127 0x0020 785250003Sadrian#define EEPROM_PROTECT_RP_128_191 0x0040 786250003Sadrian#define EEPROM_PROTECT_WP_128_191 0x0080 787250003Sadrian#define EEPROM_PROTECT_RP_192_255 0x0100 788250003Sadrian#define EEPROM_PROTECT_WP_192_255 0x0200 789250003Sadrian#define EEPROM_PROTECT_RP_256_511 0x0400 790250003Sadrian#define EEPROM_PROTECT_WP_256_511 0x0800 791250003Sadrian#define EEPROM_PROTECT_RP_512_1023 0x1000 792250003Sadrian#define EEPROM_PROTECT_WP_512_1023 0x2000 793250003Sadrian#define EEPROM_PROTECT_RP_1024_2047 0x4000 794250003Sadrian#define EEPROM_PROTECT_WP_1024_2047 0x8000 795250003Sadrian 796250003Sadrian/* RF silent */ 797250003Sadrian#define AR_RFSILENT_FORCE 0x01 798250003Sadrian 799250003Sadrian/* MAC silicon Rev ID */ 800250003Sadrian#define AR_SREV_ID 0x000000FF /* Mask to read SREV info */ 801250003Sadrian#define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */ 802250003Sadrian#define AR_SREV_VERSION_S 4 /* Mask to shift Major Rev Info */ 803250003Sadrian#define AR_SREV_REVISION 0x00000007 /* Mask for Chip revision level */ 804250003Sadrian 805250003Sadrian/* Sowl extension to SREV. AR_SREV_ID must be 0xFF */ 806250003Sadrian#define AR_SREV_ID2 0xFFFFFFFF /* Mask to read SREV info */ 807250003Sadrian#define AR_SREV_VERSION2 0xFFFC0000 /* Mask for Chip version */ 808250003Sadrian#define AR_SREV_VERSION2_S 18 /* Mask to shift Major Rev Info */ 809250003Sadrian#define AR_SREV_TYPE2 0x0003F000 /* Mask for Chip type */ 810250003Sadrian#define AR_SREV_TYPE2_S 12 /* Mask to shift Major Rev Info */ 811250003Sadrian#define AR_SREV_TYPE2_CHAIN 0x00001000 /* chain mode (1 = 3 chains, 0 = 2 chains) */ 812250003Sadrian#define AR_SREV_TYPE2_HOST_MODE 0x00002000 /* host mode (1 = PCI, 0 = PCIe) */ 813250003Sadrian/* Jupiter has a different TYPE2 definition. */ 814250003Sadrian#define AR_SREV_TYPE2_JUPITER_CHAIN 0x00001000 /* chain (1 = 2 chains, 0 = 1 chain) */ 815250003Sadrian#define AR_SREV_TYPE2_JUPITER_BAND 0x00002000 /* band (1 = dual band, 0 = single band) */ 816250003Sadrian#define AR_SREV_TYPE2_JUPITER_BT 0x00004000 /* BT (1 = shared BT, 0 = no BT) */ 817250003Sadrian#define AR_SREV_TYPE2_JUPITER_MODE 0x00008000 /* mode (1 = premium, 0 = standard) */ 818250003Sadrian#define AR_SREV_REVISION2 0x00000F00 819250003Sadrian#define AR_SREV_REVISION2_S 8 820250003Sadrian 821250003Sadrian#define AR_RADIO_SREV_MAJOR 0xf0 822250003Sadrian#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 823250003Sadrian#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 824250003Sadrian#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 825250003Sadrian#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 826250003Sadrian 827250003Sadrian#if 0 828250003Sadrian#define AR_AHB_MODE 0x4024 // ahb mode for dma 829250003Sadrian#define AR_AHB_EXACT_WR_EN 0x00000000 // write exact bytes 830250003Sadrian#define AR_AHB_BUF_WR_EN 0x00000001 // buffer write upto cacheline 831250003Sadrian#define AR_AHB_EXACT_RD_EN 0x00000000 // read exact bytes 832250003Sadrian#define AR_AHB_CACHELINE_RD_EN 0x00000002 // read upto end of cacheline 833250003Sadrian#define AR_AHB_PREFETCH_RD_EN 0x00000004 // prefetch upto page boundary 834250003Sadrian#define AR_AHB_PAGE_SIZE_1K 0x00000000 // set page-size as 1k 835250003Sadrian#define AR_AHB_PAGE_SIZE_2K 0x00000008 // set page-size as 2k 836250003Sadrian#define AR_AHB_PAGE_SIZE_4K 0x00000010 // set page-size as 4k 837250003Sadrian#endif 838250003Sadrian 839250003Sadrian#define AR_INTR_RTC_IRQ 0x00000001 // rtc in shutdown state 840250003Sadrian#define AR_INTR_MAC_IRQ 0x00000002 // pending mac interrupt 841250003Sadrian#if 0 842250003Sadrian/* 843250003Sadrian * the following definitions might be differents for WASP so 844250003Sadrian * disable them to avoid improper use 845250003Sadrian */ 846250003Sadrian#define AR_INTR_EEP_PROT_ACCESS 0x00000004 // eeprom protected area access 847250003Sadrian#define AR_INTR_MAC_AWAKE 0x00020000 // mac is awake 848250003Sadrian#define AR_INTR_MAC_ASLEEP 0x00040000 // mac is asleep 849250003Sadrian#endif 850250003Sadrian#define AR_INTR_SPURIOUS 0xFFFFFFFF 851250003Sadrian 852250003Sadrian/* TODO: fill in other values */ 853250003Sadrian 854250003Sadrian/* Synchronous Interrupt Cause Register */ 855250003Sadrian 856250003Sadrian/* Synchronous Interrupt Enable Register */ 857250003Sadrian#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 858250003Sadrian#define AR_INTR_SYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 859250003Sadrian 860250003Sadrian/* 861250003Sadrian * synchronous interrupt signals 862250003Sadrian */ 863250003Sadrianenum { 864250003Sadrian AR9300_INTR_SYNC_RTC_IRQ = 0x00000001, 865250003Sadrian AR9300_INTR_SYNC_MAC_IRQ = 0x00000002, 866250003Sadrian AR9300_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, 867250003Sadrian AR9300_INTR_SYNC_APB_TIMEOUT = 0x00000008, 868250003Sadrian AR9300_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, 869250003Sadrian AR9300_INTR_SYNC_HOST1_FATAL = 0x00000020, 870250003Sadrian AR9300_INTR_SYNC_HOST1_PERR = 0x00000040, 871250003Sadrian AR9300_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, 872250003Sadrian AR9300_INTR_SYNC_RADM_CPL_EP = 0x00000100, 873250003Sadrian AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, 874250003Sadrian AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, 875250003Sadrian AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, 876250003Sadrian AR9300_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, 877250003Sadrian AR9300_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, 878250003Sadrian AR9300_INTR_SYNC_PM_ACCESS = 0x00004000, 879250003Sadrian AR9300_INTR_SYNC_MAC_AWAKE = 0x00008000, 880250003Sadrian AR9300_INTR_SYNC_MAC_ASLEEP = 0x00010000, 881250003Sadrian AR9300_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, 882250003Sadrian AR9300_INTR_SYNC_ALL = 0x0003FFFF, 883250003Sadrian 884250003Sadrian /* 885250003Sadrian * Do not enable and turn on mask for both sync and async interrupt, since 886250003Sadrian * chip can generate interrupt storm. 887250003Sadrian */ 888250003Sadrian AR9300_INTR_SYNC_DEF_NO_HOST1_PERR = (AR9300_INTR_SYNC_HOST1_FATAL | 889250003Sadrian AR9300_INTR_SYNC_RADM_CPL_EP | 890250003Sadrian AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT | 891250003Sadrian AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT | 892250003Sadrian AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR | 893250003Sadrian AR9300_INTR_SYNC_RADM_CPL_TIMEOUT | 894250003Sadrian AR9300_INTR_SYNC_LOCAL_TIMEOUT | 895250003Sadrian AR9300_INTR_SYNC_MAC_SLEEP_ACCESS), 896250003Sadrian AR9300_INTR_SYNC_DEFAULT = (AR9300_INTR_SYNC_DEF_NO_HOST1_PERR | 897250003Sadrian AR9300_INTR_SYNC_HOST1_PERR), 898250003Sadrian 899250003Sadrian AR9300_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, 900250003Sadrian 901250003Sadrian /* WASP */ 902250003Sadrian AR9340_INTR_SYNC_RTC_IRQ = 0x00000001, 903250003Sadrian AR9340_INTR_SYNC_MAC_IRQ = 0x00000002, 904250003Sadrian AR9340_INTR_SYNC_HOST1_FATAL = 0x00000004, 905250003Sadrian AR9340_INTR_SYNC_HOST1_PERR = 0x00000008, 906250003Sadrian AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010, 907250003Sadrian AR9340_INTR_SYNC_MAC_ASLEEP = 0x00000020, 908250003Sadrian AR9340_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00000040, 909250003Sadrian 910250003Sadrian AR9340_INTR_SYNC_DEFAULT = (AR9340_INTR_SYNC_HOST1_FATAL | 911250003Sadrian AR9340_INTR_SYNC_HOST1_PERR | 912250003Sadrian AR9340_INTR_SYNC_LOCAL_TIMEOUT | 913250003Sadrian AR9340_INTR_SYNC_MAC_SLEEP_ACCESS), 914250003Sadrian 915250003Sadrian AR9340_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, 916250003Sadrian}; 917250003Sadrian 918250003Sadrian/* Asynchronous Interrupt Mask Register */ 919250003Sadrian#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 // asynchronous interrupt mask: bits 18..31 920250003Sadrian#define AR_INTR_ASYNC_MASK_GPIO_S 18 // asynchronous interrupt mask: bits 18..31 921250003Sadrian#define AR_INTR_ASYNC_MASK_MCI 0x00000080 922250003Sadrian#define AR_INTR_ASYNC_MASK_MCI_S 7 923250003Sadrian 924250003Sadrian/* Synchronous Interrupt Mask Register */ 925250003Sadrian#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 // synchronous interrupt mask: bits 18..31 926250003Sadrian#define AR_INTR_SYNC_MASK_GPIO_S 18 // synchronous interrupt mask: bits 18..31 927250003Sadrian 928250003Sadrian/* Asynchronous Interrupt Cause Register */ 929250003Sadrian#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 // GPIO interrupts: bits 18..31 930250003Sadrian#define AR_INTR_ASYNC_CAUSE_MCI 0x00000080 931250003Sadrian#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO | AR_INTR_ASYNC_CAUSE_MCI) 932250003Sadrian 933250003Sadrian/* Asynchronous Interrupt Enable Register */ 934250003Sadrian#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 935250003Sadrian#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 936250003Sadrian#define AR_INTR_ASYNC_ENABLE_MCI 0x00000080 937250003Sadrian#define AR_INTR_ASYNC_ENABLE_MCI_S 7 938250003Sadrian 939250003Sadrian/* PCIE PHY Data Register */ 940250003Sadrian 941250003Sadrian/* PCIE PHY Load Register */ 942250003Sadrian#define AR_PCIE_PM_CTRL_ENA 0x00080000 943250003Sadrian 944250003Sadrian#define AR93XX_NUM_GPIO 16 // 0 to 15 945250003Sadrian 946250003Sadrian/* GPIO Output Register */ 947250003Sadrian#define AR_GPIO_OUT_VAL 0x000FFFF 948250003Sadrian#define AR_GPIO_OUT_VAL_S 0 949250003Sadrian 950250003Sadrian/* GPIO Input Register */ 951250003Sadrian#define AR_GPIO_IN_VAL 0x000FFFF 952250003Sadrian#define AR_GPIO_IN_VAL_S 0 953250003Sadrian 954250003Sadrian/* Host GPIO output enable bits */ 955250003Sadrian#define AR_GPIO_OE_OUT_DRV 0x3 // 2 bit field mask, shifted by 2*bitpos 956250003Sadrian#define AR_GPIO_OE_OUT_DRV_NO 0x0 // tristate 957250003Sadrian#define AR_GPIO_OE_OUT_DRV_LOW 0x1 // drive if low 958250003Sadrian#define AR_GPIO_OE_OUT_DRV_HI 0x2 // drive if high 959250003Sadrian#define AR_GPIO_OE_OUT_DRV_ALL 0x3 // drive always 960250003Sadrian 961250003Sadrian/* Host GPIO output enable bits */ 962250003Sadrian 963250003Sadrian/* Host GPIO Interrupt Polarity */ 964250003Sadrian#define AR_GPIO_INTR_POL_VAL 0x0001FFFF // bits 16:0 correspond to gpio 16:0 965250003Sadrian#define AR_GPIO_INTR_POL_VAL_S 0 // bits 16:0 correspond to gpio 16:0 966250003Sadrian 967250003Sadrian/* Host GPIO Input Value */ 968250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 // default value for bt_priority_async 969250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 970250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 // default value for bt_frequency_async 971250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 972250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 // default value for bt_active_async 973250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 974250003Sadrian#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 // default value for rfsilent_bb_l 975250003Sadrian#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 976250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 // 0 == set bt_priority_async to default, 1 == connect bt_prority_async to baseband 977250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 978250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB 0x00000800 // 0 == set bt_frequency_async to default, 1 == connect bt_frequency_async to baseband 979250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB_S 11 980250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 // 0 == set bt_active_async to default, 1 == connect bt_active_async to baseband 981250003Sadrian#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 982250003Sadrian#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 // 0 == set rfsilent_bb_l to default, 1 == connect rfsilent_bb_l to baseband 983250003Sadrian#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 984250003Sadrian#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 985250003Sadrian#define AR_GPIO_JTAG_DISABLE 0x00020000 // 1 == disable JTAG 986250003Sadrian 987250003Sadrian/* GPIO Input Mux1 */ 988250003Sadrian#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 /* bits 8..11: input mux for BT priority input */ 989250003Sadrian#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 /* bits 8..11: input mux for BT priority input */ 990250003Sadrian#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY 0x0000f000 /* bits 12..15: input mux for BT frequency input */ 991250003Sadrian#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY_S 12 /* bits 12..15: input mux for BT frequency input */ 992250003Sadrian#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 /* bits 16..19: input mux for BT active input */ 993250003Sadrian#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 /* bits 16..19: input mux for BT active input */ 994250003Sadrian 995250003Sadrian/* GPIO Input Mux2 */ 996250003Sadrian#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f // bits 0..3: input mux for clk25 input 997250003Sadrian#define AR_GPIO_INPUT_MUX2_CLK25_S 0 // bits 0..3: input mux for clk25 input 998250003Sadrian#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 // bits 4..7: input mux for rfsilent_bb_l input 999250003Sadrian#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 // bits 4..7: input mux for rfsilent_bb_l input 1000250003Sadrian#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 // bits 8..11: input mux for RTC Reset input 1001250003Sadrian#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 // bits 8..11: input mux for RTC Reset input 1002250003Sadrian 1003250003Sadrian/* GPIO Output Mux1 */ 1004250003Sadrian/* GPIO Output Mux2 */ 1005250003Sadrian/* GPIO Output Mux3 */ 1006250003Sadrian 1007250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 1008250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 1009250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 1010250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 1011250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 1012250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 1013250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 1014250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 1015250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 1016250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 1017250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 1018250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 1019250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 1020250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 1021250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 1022250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 1023250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 1024250003Sadrian 1025250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0 0x1d 1026250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 0x1e 1027250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 0x1b 1028250003Sadrian/* The above three seems to be functional values for peacock chip. For some 1029250003Sadrian * reason these are continued for different boards as simple place holders. 1030250003Sadrian * Now continuing to use these and adding the extra definitions for Scropion 1031250003Sadrian */ 1032250003Sadrian#define AR_GPIO_OUTPUT_MUX_AS_SWCOM3 0x26 1033250003Sadrian 1034250003Sadrian#define AR_ENABLE_SMARTANTENNA 0x00000001 1035250003Sadrian 1036250003Sadrian/* Host GPIO Input State */ 1037250003Sadrian 1038250003Sadrian/* Host Spare */ 1039250003Sadrian 1040250003Sadrian/* Host PCIE Core Reset Enable */ 1041250003Sadrian 1042250003Sadrian/* Host CLKRUN */ 1043250003Sadrian 1044250003Sadrian 1045250003Sadrian/* Host EEPROM Status */ 1046250003Sadrian#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 1047250003Sadrian#define AR_EEPROM_STATUS_DATA_VAL_S 0 1048250003Sadrian#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1049250003Sadrian#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 1050250003Sadrian#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1051250003Sadrian#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1052250003Sadrian 1053250003Sadrian/* Host Observation Control */ 1054250003Sadrian 1055250003Sadrian/* Host RF Silent */ 1056250003Sadrian 1057250003Sadrian/* Host GPIO PDPU */ 1058250003Sadrian#define AR_GPIO_PDPU_OPTION 0x03 1059250003Sadrian#define AR_GPIO_PULL_DOWN 0x02 1060250003Sadrian 1061250003Sadrian/* Host GPIO Drive Strength */ 1062250003Sadrian 1063250003Sadrian/* Host Miscellaneous */ 1064250003Sadrian 1065250003Sadrian/* Host PCIE MSI Control Register */ 1066250003Sadrian#define AR_PCIE_MSI_ENABLE 0x00000001 1067250003Sadrian#define AR_PCIE_MSI_HW_DBI_WR_EN 0x02000000 1068250003Sadrian#define AR_PCIE_MSI_HW_INT_PENDING_ADDR 0xFFA0C1FF // bits 8..11: value must be 0x5060 1069250003Sadrian#define AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64 0xFFA0C9FF // bits 8..11: value must be 0x5064 1070250003Sadrian 1071250003Sadrian 1072250003Sadrian#define AR_INTR_PRIO_TX 0x00000001 1073250003Sadrian#define AR_INTR_PRIO_RXLP 0x00000002 1074250003Sadrian#define AR_INTR_PRIO_RXHP 0x00000004 1075250003Sadrian 1076250003Sadrian/* OTP Interface Register */ 1077250003Sadrian#define AR_ENT_OTP AR9300_HOSTIF_OFFSET(HOST_INTF_OTP) 1078250003Sadrian 1079250003Sadrian#define AR_ENT_OTP_DUAL_BAND_DISABLE 0x00010000 1080250003Sadrian#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 1081250003Sadrian#define AR_ENT_OTP_5MHZ_DISABLE 0x00040000 1082250003Sadrian#define AR_ENT_OTP_10MHZ_DISABLE 0x00080000 1083250003Sadrian#define AR_ENT_OTP_49GHZ_DISABLE 0x00100000 1084250003Sadrian#define AR_ENT_OTP_LOOPBACK_DISABLE 0x00200000 1085250003Sadrian#define AR_ENT_OTP_TPC_PERF_DISABLE 0x00400000 1086250003Sadrian#define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000 1087250003Sadrian#define AR_ENT_OTP_SPECTRAL_PRECISION 0x03000000 1088250003Sadrian 1089250003Sadrian/* OTP EFUSE registers */ 1090250003Sadrian#define AR_OTP_EFUSE_OFFSET(_x) offsetof(struct efuse_reg_WLAN, _x) 1091250003Sadrian#define AR_OTP_EFUSE_INTF0 AR_OTP_EFUSE_OFFSET(OTP_INTF0) 1092250003Sadrian#define AR_OTP_EFUSE_INTF5 AR_OTP_EFUSE_OFFSET(OTP_INTF5) 1093250003Sadrian#define AR_OTP_EFUSE_PGENB_SETUP_HOLD_TIME AR_OTP_EFUSE_OFFSET(OTP_PGENB_SETUP_HOLD_TIME) 1094250003Sadrian#define AR_OTP_EFUSE_MEM AR_OTP_EFUSE_OFFSET(OTP_MEM) 1095250003Sadrian 1096250003Sadrian/****************************************************************************** 1097250003Sadrian * RTC Register Map 1098250003Sadrian******************************************************************************/ 1099250003Sadrian 1100250003Sadrian#define AR_RTC_OFFSET(_x) offsetof(struct rtc_reg, _x) 1101250003Sadrian 1102250003Sadrian/* Reset Control */ 1103250003Sadrian#define AR_RTC_RC AR_RTC_OFFSET(RESET_CONTROL) 1104250003Sadrian#define AR_RTC_RC_M 0x00000003 1105250003Sadrian#define AR_RTC_RC_MAC_WARM 0x00000001 1106250003Sadrian#define AR_RTC_RC_MAC_COLD 0x00000002 1107250003Sadrian 1108250003Sadrian/* Crystal Control */ 1109250003Sadrian#define AR_RTC_XTAL_CONTROL AR_RTC_OFFSET(XTAL_CONTROL) 1110250003Sadrian 1111250003Sadrian/* Reg Control 0 */ 1112250003Sadrian#define AR_RTC_REG_CONTROL0 AR_RTC_OFFSET(REG_CONTROL0) 1113250003Sadrian 1114250003Sadrian/* Reg Control 1 */ 1115250003Sadrian#define AR_RTC_REG_CONTROL1 AR_RTC_OFFSET(REG_CONTROL1) 1116250003Sadrian#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 1117250003Sadrian 1118250003Sadrian/* TCXO Detect */ 1119250003Sadrian#define AR_RTC_TCXO_DETECT AR_RTC_OFFSET(TCXO_DETECT) 1120250003Sadrian 1121250003Sadrian/* Crystal Test */ 1122250003Sadrian#define AR_RTC_XTAL_TEST AR_RTC_OFFSET(XTAL_TEST) 1123250003Sadrian 1124250003Sadrian/* Sets the ADC/DAC clock quadrature */ 1125250003Sadrian#define AR_RTC_QUADRATURE AR_RTC_OFFSET(QUADRATURE) 1126250003Sadrian 1127250003Sadrian/* PLL Control */ 1128250003Sadrian#define AR_RTC_PLL_CONTROL AR_RTC_OFFSET(PLL_CONTROL) 1129250003Sadrian#define AR_RTC_PLL_DIV 0x000003ff 1130250003Sadrian#define AR_RTC_PLL_DIV_S 0 1131250003Sadrian#define AR_RTC_PLL_REFDIV 0x00003C00 1132250003Sadrian#define AR_RTC_PLL_REFDIV_S 10 1133250003Sadrian#define AR_RTC_PLL_CLKSEL 0x0000C000 1134250003Sadrian#define AR_RTC_PLL_CLKSEL_S 14 1135250003Sadrian#define AR_RTC_PLL_BYPASS 0x00010000 1136250003Sadrian#define AR_RTC_PLL_BYPASS_S 16 1137250003Sadrian 1138250003Sadrian 1139250003Sadrian/* PLL Control 2: for Hornet */ 1140250003Sadrian#define AR_RTC_PLL_CONTROL2 AR_RTC_OFFSET(PLL_CONTROL2) 1141250003Sadrian 1142250003Sadrian/* PLL Settle */ 1143250003Sadrian#define AR_RTC_PLL_SETTLE AR_RTC_OFFSET(PLL_SETTLE) 1144250003Sadrian 1145250003Sadrian/* Crystal Settle */ 1146250003Sadrian#define AR_RTC_XTAL_SETTLE AR_RTC_OFFSET(XTAL_SETTLE) 1147250003Sadrian 1148250003Sadrian/* Controls CLK_OUT pin clock speed */ 1149250003Sadrian#define AR_RTC_CLOCK_OUT AR_RTC_OFFSET(CLOCK_OUT) 1150250003Sadrian 1151250003Sadrian/* Forces bias block on at all times */ 1152250003Sadrian#define AR_RTC_BIAS_OVERRIDE AR_RTC_OFFSET(BIAS_OVERRIDE) 1153250003Sadrian 1154250003Sadrian/* System Sleep status bits */ 1155250003Sadrian#define AR_RTC_SYSTEM_SLEEP AR_RTC_OFFSET(SYSTEM_SLEEP) 1156250003Sadrian 1157250003Sadrian/* Controls sleep options for MAC */ 1158250003Sadrian#define AR_RTC_MAC_SLEEP_CONTROL AR_RTC_OFFSET(MAC_SLEEP_CONTROL) 1159250003Sadrian 1160250003Sadrian/* Keep Awake Timer */ 1161250003Sadrian#define AR_RTC_KEEP_AWAKE AR_RTC_OFFSET(KEEP_AWAKE) 1162250003Sadrian 1163250003Sadrian/* Create a 32kHz clock derived from HF */ 1164250003Sadrian#define AR_RTC_DERIVED_RTC_CLK AR_RTC_OFFSET(DERIVED_RTC_CLK) 1165250003Sadrian 1166250003Sadrian 1167250003Sadrian/****************************************************************************** 1168250003Sadrian * RTC SYNC Register Map 1169250003Sadrian******************************************************************************/ 1170250003Sadrian 1171250003Sadrian#define AR_RTC_SYNC_OFFSET(_x) offsetof(struct rtc_sync_reg, _x) 1172250003Sadrian 1173250003Sadrian/* reset RTC */ 1174250003Sadrian#define AR_RTC_RESET AR_RTC_SYNC_OFFSET(RTC_SYNC_RESET) 1175250003Sadrian#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 1176250003Sadrian 1177250003Sadrian/* system sleep status */ 1178250003Sadrian#define AR_RTC_STATUS AR_RTC_SYNC_OFFSET(RTC_SYNC_STATUS) 1179250003Sadrian#define AR_RTC_STATUS_M 0x0000003f 1180250003Sadrian#define AR_RTC_STATUS_SHUTDOWN 0x00000001 1181250003Sadrian#define AR_RTC_STATUS_ON 0x00000002 1182250003Sadrian#define AR_RTC_STATUS_SLEEP 0x00000004 1183250003Sadrian#define AR_RTC_STATUS_WAKEUP 0x00000008 1184250003Sadrian#define AR_RTC_STATUS_SLEEP_ACCESS 0x00000010 1185250003Sadrian#define AR_RTC_STATUS_PLL_CHANGING 0x00000020 1186250003Sadrian 1187250003Sadrian/* RTC Derived Register */ 1188250003Sadrian#define AR_RTC_SLEEP_CLK AR_RTC_SYNC_OFFSET(RTC_SYNC_DERIVED) 1189250003Sadrian#define AR_RTC_FORCE_DERIVED_CLK 0x00000002 1190250003Sadrian#define AR_RTC_FORCE_SWREG_PRD 0x00000004 1191250003Sadrian#define AR_RTC_PCIE_RST_PWDN_EN 0x00000008 1192250003Sadrian 1193250003Sadrian/* RTC Force Wake Register */ 1194250003Sadrian#define AR_RTC_FORCE_WAKE AR_RTC_SYNC_OFFSET(RTC_SYNC_FORCE_WAKE) 1195250003Sadrian#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 1196250003Sadrian#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 1197250003Sadrian 1198250003Sadrian/* RTC interrupt cause/clear */ 1199250003Sadrian#define AR_RTC_INTR_CAUSE AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_CAUSE) 1200250003Sadrian/* RTC interrupt enable */ 1201250003Sadrian#define AR_RTC_INTR_ENABLE AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_ENABLE) 1202250003Sadrian/* RTC interrupt mask */ 1203250003Sadrian#define AR_RTC_INTR_MASK AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_MASK) 1204250003Sadrian 1205250003Sadrian 1206250003Sadrian 1207250003Sadrian/****************************************************************************** 1208250003Sadrian * Analog Interface Register Map 1209250003Sadrian******************************************************************************/ 1210250003Sadrian 1211250003Sadrian#define AR_AN_OFFSET(_x) offsetof(struct analog_intf_reg_csr, _x) 1212250003Sadrian 1213250003Sadrian/* XXX */ 1214250003Sadrian#if 1 1215250003Sadrian// AR9280: rf long shift registers 1216250003Sadrian#define AR_AN_RF2G1_CH0 0x7810 1217250003Sadrian#define AR_AN_RF2G1_CH0_OB 0x03800000 1218250003Sadrian#define AR_AN_RF2G1_CH0_OB_S 23 1219250003Sadrian#define AR_AN_RF2G1_CH0_DB 0x1C000000 1220250003Sadrian#define AR_AN_RF2G1_CH0_DB_S 26 1221250003Sadrian 1222250003Sadrian#define AR_AN_RF5G1_CH0 0x7818 1223250003Sadrian#define AR_AN_RF5G1_CH0_OB5 0x00070000 1224250003Sadrian#define AR_AN_RF5G1_CH0_OB5_S 16 1225250003Sadrian#define AR_AN_RF5G1_CH0_DB5 0x00380000 1226250003Sadrian#define AR_AN_RF5G1_CH0_DB5_S 19 1227250003Sadrian 1228250003Sadrian#define AR_AN_RF2G1_CH1 0x7834 1229250003Sadrian#define AR_AN_RF2G1_CH1_OB 0x03800000 1230250003Sadrian#define AR_AN_RF2G1_CH1_OB_S 23 1231250003Sadrian#define AR_AN_RF2G1_CH1_DB 0x1C000000 1232250003Sadrian#define AR_AN_RF2G1_CH1_DB_S 26 1233250003Sadrian 1234250003Sadrian#define AR_AN_RF5G1_CH1 0x783C 1235250003Sadrian#define AR_AN_RF5G1_CH1_OB5 0x00070000 1236250003Sadrian#define AR_AN_RF5G1_CH1_OB5_S 16 1237250003Sadrian#define AR_AN_RF5G1_CH1_DB5 0x00380000 1238250003Sadrian#define AR_AN_RF5G1_CH1_DB5_S 19 1239250003Sadrian 1240250003Sadrian#define AR_AN_TOP2 0x7894 1241250003Sadrian#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 1242250003Sadrian#define AR_AN_TOP2_XPABIAS_LVL_S 30 1243250003Sadrian#define AR_AN_TOP2_LOCALBIAS 0x00200000 1244250003Sadrian#define AR_AN_TOP2_LOCALBIAS_S 21 1245250003Sadrian#define AR_AN_TOP2_PWDCLKIND 0x00400000 1246250003Sadrian#define AR_AN_TOP2_PWDCLKIND_S 22 1247250003Sadrian 1248250003Sadrian#define AR_AN_SYNTH9 0x7868 1249250003Sadrian#define AR_AN_SYNTH9_REFDIVA 0xf8000000 1250250003Sadrian#define AR_AN_SYNTH9_REFDIVA_S 27 1251250003Sadrian 1252250003Sadrian// AR9285 Analog registers 1253250003Sadrian#define AR9285_AN_RF2G1 0x7820 1254250003Sadrian#define AR9285_AN_RF2G2 0x7824 1255250003Sadrian 1256250003Sadrian#define AR9285_AN_RF2G3 0x7828 1257250003Sadrian#define AR9285_AN_RF2G3_OB_0 0x00E00000 1258250003Sadrian#define AR9285_AN_RF2G3_OB_0_S 21 1259250003Sadrian#define AR9285_AN_RF2G3_OB_1 0x001C0000 1260250003Sadrian#define AR9285_AN_RF2G3_OB_1_S 18 1261250003Sadrian#define AR9285_AN_RF2G3_OB_2 0x00038000 1262250003Sadrian#define AR9285_AN_RF2G3_OB_2_S 15 1263250003Sadrian#define AR9285_AN_RF2G3_OB_3 0x00007000 1264250003Sadrian#define AR9285_AN_RF2G3_OB_3_S 12 1265250003Sadrian#define AR9285_AN_RF2G3_OB_4 0x00000E00 1266250003Sadrian#define AR9285_AN_RF2G3_OB_4_S 9 1267250003Sadrian 1268250003Sadrian#define AR9285_AN_RF2G3_DB1_0 0x000001C0 1269250003Sadrian#define AR9285_AN_RF2G3_DB1_0_S 6 1270250003Sadrian#define AR9285_AN_RF2G3_DB1_1 0x00000038 1271250003Sadrian#define AR9285_AN_RF2G3_DB1_1_S 3 1272250003Sadrian#define AR9285_AN_RF2G3_DB1_2 0x00000007 1273250003Sadrian#define AR9285_AN_RF2G3_DB1_2_S 0 1274250003Sadrian#define AR9285_AN_RF2G4 0x782C 1275250003Sadrian#define AR9285_AN_RF2G4_DB1_3 0xE0000000 1276250003Sadrian#define AR9285_AN_RF2G4_DB1_3_S 29 1277250003Sadrian#define AR9285_AN_RF2G4_DB1_4 0x1C000000 1278250003Sadrian#define AR9285_AN_RF2G4_DB1_4_S 26 1279250003Sadrian 1280250003Sadrian#define AR9285_AN_RF2G4_DB2_0 0x03800000 1281250003Sadrian#define AR9285_AN_RF2G4_DB2_0_S 23 1282250003Sadrian#define AR9285_AN_RF2G4_DB2_1 0x00700000 1283250003Sadrian#define AR9285_AN_RF2G4_DB2_1_S 20 1284250003Sadrian#define AR9285_AN_RF2G4_DB2_2 0x000E0000 1285250003Sadrian#define AR9285_AN_RF2G4_DB2_2_S 17 1286250003Sadrian#define AR9285_AN_RF2G4_DB2_3 0x0001C000 1287250003Sadrian#define AR9285_AN_RF2G4_DB2_3_S 14 1288250003Sadrian#define AR9285_AN_RF2G4_DB2_4 0x00003800 1289250003Sadrian#define AR9285_AN_RF2G4_DB2_4_S 11 1290250003Sadrian 1291250003Sadrian#define AR9285_AN_RF2G6 0x7834 1292250003Sadrian#define AR9285_AN_RF2G7 0x7838 1293250003Sadrian#define AR9285_AN_RF2G9 0x7840 1294250003Sadrian#define AR9285_AN_RXTXBB1 0x7854 1295250003Sadrian#define AR9285_AN_TOP2 0x7868 1296250003Sadrian 1297250003Sadrian#define AR9285_AN_TOP3 0x786c 1298250003Sadrian#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 1299250003Sadrian#define AR9285_AN_TOP3_XPABIAS_LVL_S 2 1300250003Sadrian 1301250003Sadrian#define AR9285_AN_TOP4 0x7870 1302250003Sadrian#define AR9285_AN_TOP4_DEFAULT 0x10142c00 1303250003Sadrian#endif 1304250003Sadrian 1305250003Sadrian 1306250003Sadrian/****************************************************************************** 1307250003Sadrian * MAC PCU Register Map 1308250003Sadrian******************************************************************************/ 1309250003Sadrian 1310250003Sadrian#define AR_MAC_PCU_OFFSET(_x) offsetof(struct mac_pcu_reg, _x) 1311250003Sadrian 1312250003Sadrian/* MAC station ID0 - low 32 bits */ 1313250003Sadrian#define AR_STA_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_L32) 1314250003Sadrian/* MAC station ID1 - upper 16 bits */ 1315250003Sadrian#define AR_STA_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_U16) 1316250003Sadrian#define AR_STA_ID1_SADH_MASK 0x0000FFFF // Mask for 16 msb of MAC addr 1317250003Sadrian#define AR_STA_ID1_STA_AP 0x00010000 // Device is AP 1318250003Sadrian#define AR_STA_ID1_ADHOC 0x00020000 // Device is ad-hoc 1319250003Sadrian#define AR_STA_ID1_PWR_SAV 0x00040000 // Power save in generated frames 1320250003Sadrian#define AR_STA_ID1_KSRCHDIS 0x00080000 // Key search disable 1321250003Sadrian#define AR_STA_ID1_PCF 0x00100000 // Observe PCF 1322250003Sadrian#define AR_STA_ID1_USE_DEFANT 0x00200000 // Use default antenna 1323250003Sadrian#define AR_STA_ID1_DEFANT_UPDATE 0x00400000 // Update default ant w/TX antenna 1324250003Sadrian#define AR_STA_ID1_RTS_USE_DEF 0x00800000 // Use default antenna to send RTS 1325250003Sadrian#define AR_STA_ID1_ACKCTS_6MB 0x01000000 // Use 6Mb/s rate for ACK & CTS 1326250003Sadrian#define AR_STA_ID1_BASE_RATE_11B 0x02000000 // Use 11b base rate for ACK & CTS 1327250003Sadrian#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 // default ant for generated frames 1328250003Sadrian#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 // Enable Michael 1329250003Sadrian#define AR_STA_ID1_KSRCH_MODE 0x10000000 // Look-up unique key when !keyID 1330250003Sadrian#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 // Don't replace seq num 1331250003Sadrian#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 // IV endian-ness in CBC nonce 1332250003Sadrian#define AR_STA_ID1_MCAST_KSRCH 0x80000000 // Adhoc key search enable 1333250003Sadrian 1334250003Sadrian/* MAC BSSID low 32 bits */ 1335250003Sadrian#define AR_BSS_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_L32) 1336250003Sadrian/* MAC BSSID upper 16 bits / AID */ 1337250003Sadrian#define AR_BSS_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_U16) 1338250003Sadrian#define AR_BSS_ID1_U16 0x0000FFFF // Mask for upper 16 bits of BSSID 1339250003Sadrian#define AR_BSS_ID1_AID 0x07FF0000 // Mask for association ID 1340250003Sadrian#define AR_BSS_ID1_AID_S 16 // Shift for association ID 1341250003Sadrian 1342250003Sadrian/* 1343250003Sadrian * Added to support dual BSSID/TSF which are needed in the application 1344250003Sadrian * of Mesh networking. See bug 35189. Note that the only function added 1345250003Sadrian * with this BSSID2 is to receive multi/broadcast from BSSID2 as well 1346250003Sadrian */ 1347250003Sadrian/* MAC BSSID low 32 bits */ 1348250003Sadrian#define AR_BSS2_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32) 1349250003Sadrian/* MAC BSSID upper 16 bits / AID */ 1350250003Sadrian#define AR_BSS2_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16) 1351250003Sadrian 1352250003Sadrian/* MAC Beacon average RSSI 1353250003Sadrian * 1354250003Sadrian * This register holds the average RSSI with 1/16 dB resolution. 1355250003Sadrian * The RSSI is averaged over multiple beacons which matched our BSSID. 1356250003Sadrian * Note that AVE_VALUE is 12 bits with 4 bits below the normal 8 bits. 1357250003Sadrian * These lowest 4 bits provide for a resolution of 1/16 dB. 1358250003Sadrian * 1359250003Sadrian */ 1360250003Sadrian#define AR_BCN_RSSI_AVE AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_AVE) 1361250003Sadrian#define AR_BCN_RSSI_AVE_VAL 0x00000FFF // Beacon RSSI value 1362250003Sadrian#define AR_BCN_RSSI_AVE_VAL_S 0 1363250003Sadrian 1364250003Sadrian/* MAC ACK & CTS time-out */ 1365250003Sadrian#define AR_TIME_OUT AR_MAC_PCU_OFFSET(MAC_PCU_ACK_CTS_TIMEOUT) 1366250003Sadrian#define AR_TIME_OUT_ACK 0x00003FFF // Mask for ACK time-out 1367250003Sadrian#define AR_TIME_OUT_ACK_S 0 1368250003Sadrian#define AR_TIME_OUT_CTS 0x3FFF0000 // Mask for CTS time-out 1369250003Sadrian#define AR_TIME_OUT_CTS_S 16 1370250003Sadrian 1371250003Sadrian/* beacon RSSI warning / bmiss threshold */ 1372250003Sadrian#define AR_RSSI_THR AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_CTL) 1373250003Sadrian#define AR_RSSI_THR_VAL 0x000000FF // Beacon RSSI warning threshold 1374250003Sadrian#define AR_RSSI_THR_VAL_S 0 1375250003Sadrian#define AR_RSSI_THR_BM_THR 0x0000FF00 // Mask for Missed beacon threshold 1376250003Sadrian#define AR_RSSI_THR_BM_THR_S 8 // Shift for Missed beacon threshold 1377250003Sadrian#define AR_RSSI_BCN_WEIGHT 0x1F000000 // RSSI average weight 1378250003Sadrian#define AR_RSSI_BCN_WEIGHT_S 24 1379250003Sadrian#define AR_RSSI_BCN_RSSI_RST 0x20000000 // Reset RSSI value 1380250003Sadrian 1381250003Sadrian/* MAC transmit latency register */ 1382250003Sadrian#define AR_USEC AR_MAC_PCU_OFFSET(MAC_PCU_USEC_LATENCY) 1383250003Sadrian#define AR_USEC_USEC 0x000000FF // Mask for clock cycles in 1 usec 1384250003Sadrian#define AR_USEC_USEC_S 0 // Shift for clock cycles in 1 usec 1385250003Sadrian#define AR_USEC_TX_LAT 0x007FC000 // tx latency to start of SIGNAL (usec) 1386250003Sadrian#define AR_USEC_TX_LAT_S 14 // tx latency to start of SIGNAL (usec) 1387250003Sadrian#define AR_USEC_RX_LAT 0x1F800000 // rx latency to start of SIGNAL (usec) 1388250003Sadrian#define AR_USEC_RX_LAT_S 23 // rx latency to start of SIGNAL (usec) 1389250003Sadrian 1390250003Sadrian#define AR_SLOT_HALF 13 1391250003Sadrian#define AR_SLOT_QUARTER 21 1392250003Sadrian 1393250003Sadrian#define AR_USEC_RX_LATENCY 0x1f800000 1394250003Sadrian#define AR_USEC_RX_LATENCY_S 23 1395250003Sadrian#define AR_RX_LATENCY_FULL 37 1396250003Sadrian#define AR_RX_LATENCY_HALF 74 1397250003Sadrian#define AR_RX_LATENCY_QUARTER 148 1398250003Sadrian#define AR_RX_LATENCY_FULL_FAST_CLOCK 41 1399250003Sadrian#define AR_RX_LATENCY_HALF_FAST_CLOCK 82 1400250003Sadrian#define AR_RX_LATENCY_QUARTER_FAST_CLOCK 163 1401250003Sadrian 1402250003Sadrian#define AR_USEC_TX_LATENCY 0x007fc000 1403250003Sadrian#define AR_USEC_TX_LATENCY_S 14 1404250003Sadrian#define AR_TX_LATENCY_FULL 54 1405250003Sadrian#define AR_TX_LATENCY_HALF 108 1406250003Sadrian#define AR_TX_LATENCY_QUARTER 216 1407250003Sadrian#define AR_TX_LATENCY_FULL_FAST_CLOCK 54 1408250003Sadrian#define AR_TX_LATENCY_HALF_FAST_CLOCK 119 1409250003Sadrian#define AR_TX_LATENCY_QUARTER_FAST_CLOCK 238 1410250003Sadrian 1411250003Sadrian#define AR_USEC_HALF 19 1412250003Sadrian#define AR_USEC_QUARTER 9 1413250003Sadrian#define AR_USEC_HALF_FAST_CLOCK 21 1414250003Sadrian#define AR_USEC_QUARTER_FAST_CLOCK 10 1415250003Sadrian 1416250003Sadrian#define AR_EIFS_HALF 175 1417250003Sadrian#define AR_EIFS_QUARTER 340 1418250003Sadrian 1419250003Sadrian#define AR_RESET_TSF AR_MAC_PCU_OFFSET(MAC_PCU_RESET_TSF) 1420250003Sadrian#define AR_RESET_TSF_ONCE 0x01000000 // reset tsf once ; self-clears bit 1421250003Sadrian#define AR_RESET_TSF2_ONCE 0x02000000 // reset tsf2 once ; self-clears bit 1422250003Sadrian 1423250003Sadrian/* MAC CFP Interval (TU/msec) */ 1424250003Sadrian#define AR_CFP_PERIOD 0x8024 /* MAC CFP Interval (TU/msec) */ 1425250003Sadrian#define AR_TIMER0 0x8028 /* MAC Next beacon time (TU/msec) */ 1426250003Sadrian#define AR_TIMER1 0x802c /* MAC DMA beacon alert time (1/8 TU) */ 1427250003Sadrian#define AR_TIMER2 0x8030 /* MAC Software beacon alert (1/8 TU) */ 1428250003Sadrian#define AR_TIMER3 0x8034 /* MAC ATIM window time */ 1429250003Sadrian 1430250003Sadrian/* MAC maximum CFP duration */ 1431250003Sadrian#define AR_MAX_CFP_DUR AR_MAC_PCU_OFFSET(MAC_PCU_MAX_CFP_DUR) 1432250003Sadrian#define AR_CFP_VAL 0x0000FFFF // CFP value in uS 1433250003Sadrian 1434250003Sadrian/* MAC receive filter register */ 1435250003Sadrian#define AR_RX_FILTER AR_MAC_PCU_OFFSET(MAC_PCU_RX_FILTER) 1436250003Sadrian#define AR_RX_FILTER_ALL 0x00000000 // Disallow all frames 1437250003Sadrian#define AR_RX_UCAST 0x00000001 // Allow unicast frames 1438250003Sadrian#define AR_RX_MCAST 0x00000002 // Allow multicast frames 1439250003Sadrian#define AR_RX_BCAST 0x00000004 // Allow broadcast frames 1440250003Sadrian#define AR_RX_CONTROL 0x00000008 // Allow control frames 1441250003Sadrian#define AR_RX_BEACON 0x00000010 // Allow beacon frames 1442250003Sadrian#define AR_RX_PROM 0x00000020 // Promiscuous mode all packets 1443250003Sadrian#define AR_RX_PROBE_REQ 0x00000080 // Any probe request frameA 1444250003Sadrian#define AR_RX_MY_BEACON 0x00000200 // Any beacon frame with matching BSSID 1445250003Sadrian#define AR_RX_COMPR_BAR 0x00000400 // Compressed directed block ack request 1446250003Sadrian#define AR_RX_COMPR_BA 0x00000800 // Compressed directed block ack 1447250003Sadrian#define AR_RX_UNCOM_BA_BAR 0x00001000 // Uncompressed directed BA or BAR 1448250003Sadrian#define AR_RX_HWBCNPROC_EN 0x00020000 // Enable hw beacon processing (see AR_HWBCNPROC1) 1449250003Sadrian#define AR_RX_CONTROL_WRAPPER 0x00080000 // Control wrapper. Jupiter only. 1450250003Sadrian#define AR_RX_4ADDRESS 0x00100000 // 4-Address frames 1451250003Sadrian 1452250003Sadrian#define AR_PHY_ERR_MASK_REG AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT) 1453250003Sadrian 1454250003Sadrian 1455250003Sadrian/* MAC multicast filter lower 32 bits */ 1456250003Sadrian#define AR_MCAST_FIL0 AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_L32) 1457250003Sadrian/* MAC multicast filter upper 32 bits */ 1458250003Sadrian#define AR_MCAST_FIL1 AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_U32) 1459250003Sadrian 1460250003Sadrian/* MAC PCU diagnostic switches */ 1461250003Sadrian#define AR_DIAG_SW AR_MAC_PCU_OFFSET(MAC_PCU_DIAG_SW) 1462250003Sadrian#define AR_DIAG_CACHE_ACK 0x00000001 // disable ACK when no valid key 1463250003Sadrian#define AR_DIAG_ACK_DIS 0x00000002 // disable ACK generation 1464250003Sadrian#define AR_DIAG_CTS_DIS 0x00000004 // disable CTS generation 1465250003Sadrian#define AR_DIAG_ENCRYPT_DIS 0x00000008 // disable encryption 1466250003Sadrian#define AR_DIAG_DECRYPT_DIS 0x00000010 // disable decryption 1467250003Sadrian#define AR_DIAG_RX_DIS 0x00000020 // disable receive 1468250003Sadrian#define AR_DIAG_LOOP_BACK 0x00000040 // enable loopback 1469250003Sadrian#define AR_DIAG_CORR_FCS 0x00000080 // corrupt FCS 1470250003Sadrian#define AR_DIAG_CHAN_INFO 0x00000100 // dump channel info 1471250003Sadrian#define AR_DIAG_FRAME_NV0 0x00020000 // accept w/protocol version !0 1472250003Sadrian#define AR_DIAG_OBS_PT_SEL1 0x000C0000 // observation point select 1473250003Sadrian#define AR_DIAG_OBS_PT_SEL1_S 18 // Shift for observation point select 1474250003Sadrian#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 // force rx_clear high 1475250003Sadrian#define AR_DIAG_IGNORE_VIRT_CS 0x00200000 // ignore virtual carrier sense 1476250003Sadrian#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 // force channel idle high 1477250003Sadrian#define AR_DIAG_EIFS_CTRL_ENA 0x00800000 // use framed and ~wait_wep if 0 1478250003Sadrian#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 // dual chain channel info 1479250003Sadrian#define AR_DIAG_RX_ABORT 0x02000000 // abort rx 1480250003Sadrian#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 // saturate cycle cnts (no shift) 1481250003Sadrian#define AR_DIAG_OBS_PT_SEL2 0x08000000 // Mask for observation point sel 1482250003Sadrian#define AR_DIAG_OBS_PT_SEL2_S 27 1483250003Sadrian#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 // force rx_clear (ctl) low (i.e. busy) 1484250003Sadrian#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 // force rx_clear (ext) low (i.e. busy) 1485250003Sadrian 1486250003Sadrian/* MAC local clock lower 32 bits */ 1487250003Sadrian#define AR_TSF_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF_L32) 1488250003Sadrian/* MAC local clock upper 32 bits */ 1489250003Sadrian#define AR_TSF_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF_U32) 1490250003Sadrian 1491250003Sadrian/* 1492250003Sadrian * Secondary TSF support added for dual BSSID/TSF 1493250003Sadrian * which is needed in the application of DirectConnect or 1494250003Sadrian * Mesh networking 1495250003Sadrian */ 1496250003Sadrian/* MAC local clock lower 32 bits */ 1497250003Sadrian#define AR_TSF2_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32) 1498250003Sadrian/* MAC local clock upper 32 bits */ 1499250003Sadrian#define AR_TSF2_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32) 1500250003Sadrian 1501250003Sadrian/* ADDAC test register */ 1502250003Sadrian#define AR_TST_ADDAC AR_MAC_PCU_OFFSET(MAC_PCU_TST_ADDAC) 1503250003Sadrian 1504250003Sadrian#define AR_TST_ADDAC_TST_MODE 0x1 1505250003Sadrian#define AR_TST_ADDAC_TST_MODE_S 0 1506250003Sadrian#define AR_TST_ADDAC_TST_LOOP_ENA 0x2 1507250003Sadrian#define AR_TST_ADDAC_TST_LOOP_ENA_S 1 1508250003Sadrian#define AR_TST_ADDAC_BEGIN_CAPTURE 0x80000 1509250003Sadrian#define AR_TST_ADDAC_BEGIN_CAPTURE_S 19 1510250003Sadrian 1511250003Sadrian/* default antenna register */ 1512250003Sadrian#define AR_DEF_ANTENNA AR_MAC_PCU_OFFSET(MAC_PCU_DEF_ANTENNA) 1513250003Sadrian 1514250003Sadrian/* MAC AES mute mask */ 1515250003Sadrian#define AR_AES_MUTE_MASK0 AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_0) 1516250003Sadrian#define AR_AES_MUTE_MASK0_FC 0x0000FFFF // frame ctrl mask bits 1517250003Sadrian#define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 // qos ctrl mask bits 1518250003Sadrian#define AR_AES_MUTE_MASK0_QOS_S 16 1519250003Sadrian 1520250003Sadrian/* MAC AES mute mask 1 */ 1521250003Sadrian#define AR_AES_MUTE_MASK1 AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_1) 1522250003Sadrian#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF // seq + frag mask bits 1523250003Sadrian#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 // frame ctrl mask for mgmt frames (Sowl) 1524250003Sadrian#define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1525250003Sadrian 1526250003Sadrian/* control clock domain */ 1527250003Sadrian#define AR_GATED_CLKS AR_MAC_PCU_OFFSET(MAC_PCU_GATED_CLKS) 1528250003Sadrian#define AR_GATED_CLKS_TX 0x00000002 1529250003Sadrian#define AR_GATED_CLKS_RX 0x00000004 1530250003Sadrian#define AR_GATED_CLKS_REG 0x00000008 1531250003Sadrian 1532250003Sadrian/* MAC PCU observation bus 2 */ 1533250003Sadrian#define AR_OBS_BUS_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_2) 1534250003Sadrian#define AR_OBS_BUS_SEL_1 0x00040000 1535250003Sadrian#define AR_OBS_BUS_SEL_2 0x00080000 1536250003Sadrian#define AR_OBS_BUS_SEL_3 0x000C0000 1537250003Sadrian#define AR_OBS_BUS_SEL_4 0x08040000 1538250003Sadrian#define AR_OBS_BUS_SEL_5 0x08080000 1539250003Sadrian 1540250003Sadrian/* MAC PCU observation bus 1 */ 1541250003Sadrian#define AR_OBS_BUS_1 AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_1) 1542250003Sadrian#define AR_OBS_BUS_1_PCU 0x00000001 1543250003Sadrian#define AR_OBS_BUS_1_RX_END 0x00000002 1544250003Sadrian#define AR_OBS_BUS_1_RX_WEP 0x00000004 1545250003Sadrian#define AR_OBS_BUS_1_RX_BEACON 0x00000008 1546250003Sadrian#define AR_OBS_BUS_1_RX_FILTER 0x00000010 1547250003Sadrian#define AR_OBS_BUS_1_TX_HCF 0x00000020 1548250003Sadrian#define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1549250003Sadrian#define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1550250003Sadrian#define AR_OBS_BUS_1_TX_HOLD 0x00000100 1551250003Sadrian#define AR_OBS_BUS_1_TX_FRAME 0x00000200 1552250003Sadrian#define AR_OBS_BUS_1_RX_FRAME 0x00000400 1553250003Sadrian#define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1554250003Sadrian#define AR_OBS_BUS_1_WEP_STATE 0x0003F000 1555250003Sadrian#define AR_OBS_BUS_1_WEP_STATE_S 12 1556250003Sadrian#define AR_OBS_BUS_1_RX_STATE 0x01F00000 1557250003Sadrian#define AR_OBS_BUS_1_RX_STATE_S 20 1558250003Sadrian#define AR_OBS_BUS_1_TX_STATE 0x7E000000 1559250003Sadrian#define AR_OBS_BUS_1_TX_STATE_S 25 1560250003Sadrian 1561250003Sadrian/* MAC PCU dynamic MIMO power save */ 1562250003Sadrian#define AR_PCU_SMPS AR_MAC_PCU_OFFSET(MAC_PCU_DYM_MIMO_PWR_SAVE) 1563250003Sadrian#define AR_PCU_SMPS_MAC_CHAINMASK 0x00000001 // Use the Rx Chainmask of MAC's setting 1564250003Sadrian#define AR_PCU_SMPS_HW_CTRL_EN 0x00000002 // Enable hardware control of dynamic MIMO PS 1565250003Sadrian#define AR_PCU_SMPS_SW_CTRL_HPWR 0x00000004 // Software controlled High power chainmask setting 1566250003Sadrian#define AR_PCU_SMPS_LPWR_CHNMSK 0x00000070 // Low power setting of Rx Chainmask 1567250003Sadrian#define AR_PCU_SMPS_LPWR_CHNMSK_S 4 1568250003Sadrian#define AR_PCU_SMPS_HPWR_CHNMSK 0x00000700 // High power setting of Rx Chainmask 1569250003Sadrian#define AR_PCU_SMPS_HPWR_CHNMSK_S 8 1570250003Sadrian#define AR_PCU_SMPS_LPWR_CHNMSK_VAL 0x1 1571250003Sadrian 1572250003Sadrian/* MAC PCU frame start time trigger for the AP's Downlink Traffic in TDMA mode */ 1573250003Sadrian#define AR_TDMA_TXSTARTTRIG_LSB AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB) 1574250003Sadrian#define AR_TDMA_TXSTARTTRIG_MSB AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB) 1575250003Sadrian 1576250003Sadrian/* MAC Time stamp of the last beacon received */ 1577250003Sadrian#define AR_LAST_TSTP AR_MAC_PCU_OFFSET(MAC_PCU_LAST_BEACON_TSF) 1578250003Sadrian/* MAC current NAV value */ 1579250003Sadrian#define AR_NAV AR_MAC_PCU_OFFSET(MAC_PCU_NAV) 1580250003Sadrian/* MAC RTS exchange success counter */ 1581250003Sadrian#define AR_RTS_OK AR_MAC_PCU_OFFSET(MAC_PCU_RTS_SUCCESS_CNT) 1582250003Sadrian/* MAC RTS exchange failure counter */ 1583250003Sadrian#define AR_RTS_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_RTS_FAIL_CNT) 1584250003Sadrian/* MAC ACK failure counter */ 1585250003Sadrian#define AR_ACK_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_ACK_FAIL_CNT) 1586250003Sadrian/* MAC FCS check failure counter */ 1587250003Sadrian#define AR_FCS_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_FCS_FAIL_CNT) 1588250003Sadrian/* MAC Valid beacon value */ 1589250003Sadrian#define AR_BEACON_CNT AR_MAC_PCU_OFFSET(MAC_PCU_BEACON_CNT) 1590250003Sadrian 1591250003Sadrian/* MAC PCU tdma slot alert control */ 1592250003Sadrian#define AR_TDMA_SLOT_ALERT_CNTL AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_SLOT_ALERT_CNTL) 1593250003Sadrian 1594250003Sadrian/* MAC PCU Basic MCS set for MCS 0 to 31 */ 1595250003Sadrian#define AR_BASIC_SET AR_MAC_PCU_OFFSET(MAC_PCU_BASIC_SET) 1596250003Sadrian#define ALL_RATE 0xff 1597250003Sadrian 1598250003Sadrian/* MAC_PCU_ _SEQ */ 1599250003Sadrian#define AR_MGMT_SEQ AR_MAC_PCU_OFFSET(MAC_PCU_MGMT_SEQ) 1600250003Sadrian#define AR_MGMT_SEQ_MIN 0xFFF /* sequence minimum value*/ 1601250003Sadrian#define AR_MGMT_SEQ_MIN_S 0 1602250003Sadrian#define AR_MIN_HW_SEQ 0 1603250003Sadrian#define AR_MGMT_SEQ_MAX 0xFFF0000 /* sequence maximum value*/ 1604250003Sadrian#define AR_MGMT_SEQ_MAX_S 16 1605250003Sadrian#define AR_MAX_HW_SEQ 0xFF 1606250003Sadrian/*MAC PCU Key Cache Antenna 1 */ 1607250003Sadrian#define AR_TX_ANT_1 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_1) 1608250003Sadrian/*MAC PCU Key Cache Antenna 2 */ 1609250003Sadrian#define AR_TX_ANT_2 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_2) 1610250003Sadrian/*MAC PCU Key Cache Antenna 3 */ 1611250003Sadrian#define AR_TX_ANT_3 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_3) 1612250003Sadrian/*MAC PCU Key Cache Antenna 4 */ 1613250003Sadrian#define AR_TX_ANT_4 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_4) 1614250003Sadrian 1615250003Sadrian 1616250003Sadrian/* Extended range mode */ 1617250003Sadrian#define AR_XRMODE AR_MAC_PCU_OFFSET(MAC_PCU_XRMODE) 1618250003Sadrian/* Extended range mode delay */ 1619250003Sadrian#define AR_XRDEL AR_MAC_PCU_OFFSET(MAC_PCU_XRDEL) 1620250003Sadrian/* Extended range mode timeout */ 1621250003Sadrian#define AR_XRTO AR_MAC_PCU_OFFSET(MAC_PCU_XRTO) 1622250003Sadrian/* Extended range mode chirp */ 1623250003Sadrian#define AR_XRCRP AR_MAC_PCU_OFFSET(MAC_PCU_XRCRP) 1624250003Sadrian/* Extended range stomp */ 1625250003Sadrian#define AR_XRSTMP AR_MAC_PCU_OFFSET(MAC_PCU_XRSTMP) 1626250003Sadrian 1627250003Sadrian 1628250003Sadrian/* Enhanced sleep control 1 */ 1629250003Sadrian#define AR_SLEEP1 AR_MAC_PCU_OFFSET(MAC_PCU_SLP1) 1630250003Sadrian#define AR_SLEEP1_ASSUME_DTIM 0x00080000 // Assume DTIM on missed beacon 1631250003Sadrian#define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 // Cab timeout(TU) mask 1632250003Sadrian#define AR_SLEEP1_CAB_TIMEOUT_S 21 // Cab timeout(TU) shift 1633250003Sadrian 1634250003Sadrian/* Enhanced sleep control 2 */ 1635250003Sadrian#define AR_SLEEP2 AR_MAC_PCU_OFFSET(MAC_PCU_SLP2) 1636250003Sadrian#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 // Beacon timeout(TU) mask 1637250003Sadrian#define AR_SLEEP2_BEACON_TIMEOUT_S 21 // Beacon timeout(TU) shift 1638250003Sadrian 1639250003Sadrian/*MAC_PCU_SELF_GEN_DEFAULT*/ 1640250003Sadrian#define AR_SELFGEN AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_DEFAULT) 1641250003Sadrian#define AR_MMSS 0x00000007 1642250003Sadrian#define AR_MMSS_S 0 1643250003Sadrian#define AR_SELFGEN_MMSS_NO RESTRICTION 0 1644250003Sadrian#define AR_SELFGEN_MMSS_ONEOVER4_us 1 1645250003Sadrian#define AR_SELFGEN_MMSS_ONEOVER2_us 2 1646250003Sadrian#define AR_SELFGEN_MMSS_ONE_us 3 1647250003Sadrian#define AR_SELFGEN_MMSS_TWO_us 4 1648250003Sadrian#define AR_SELFGEN_MMSS_FOUR_us 5 1649250003Sadrian#define AR_SELFGEN_MMSS_EIGHT_us 6 1650250003Sadrian#define AR_SELFGEN_MMSS_SIXTEEN_us 7 1651250003Sadrian 1652250003Sadrian#define AR_CEC 0x00000018 1653250003Sadrian#define AR_CEC_S 3 1654250003Sadrian/* Although in original standard 0 is for 1 stream and 1 is for 2 stream */ 1655250003Sadrian/* due to H/W resaon, Here should set 1 for 1 stream and 2 for 2 stream */ 1656250003Sadrian#define AR_SELFGEN_CEC_ONE_SPACETIMESTREAM 1 1657250003Sadrian#define AR_SELFGEN_CEC_TWO_SPACETIMESTREAM 2 1658250003Sadrian 1659250003Sadrian/* BSSID mask lower 32 bits */ 1660250003Sadrian#define AR_BSSMSKL AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_L32) 1661250003Sadrian/* BSSID mask upper 16 bits */ 1662250003Sadrian#define AR_BSSMSKU AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_U16) 1663250003Sadrian 1664250003Sadrian/* Transmit power control for gen frames */ 1665250003Sadrian#define AR_TPC AR_MAC_PCU_OFFSET(MAC_PCU_TPC) 1666250003Sadrian#define AR_TPC_ACK 0x0000003f // ack frames mask 1667250003Sadrian#define AR_TPC_ACK_S 0x00 // ack frames shift 1668250003Sadrian#define AR_TPC_CTS 0x00003f00 // cts frames mask 1669250003Sadrian#define AR_TPC_CTS_S 0x08 // cts frames shift 1670250003Sadrian#define AR_TPC_CHIRP 0x003f0000 // chirp frames mask 1671250003Sadrian#define AR_TPC_CHIRP_S 16 // chirp frames shift 1672250003Sadrian#define AR_TPC_RPT 0x3f000000 // rpt frames mask 1673250003Sadrian#define AR_TPC_RPT_S 24 // rpt frames shift 1674250003Sadrian 1675250003Sadrian/* Profile count transmit frames */ 1676250003Sadrian#define AR_TFCNT AR_MAC_PCU_OFFSET(MAC_PCU_TX_FRAME_CNT) 1677250003Sadrian/* Profile count receive frames */ 1678250003Sadrian#define AR_RFCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_FRAME_CNT) 1679250003Sadrian/* Profile count receive clear */ 1680250003Sadrian#define AR_RCCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_CNT) 1681250003Sadrian/* Profile count cycle counter */ 1682250003Sadrian#define AR_CCCNT AR_MAC_PCU_OFFSET(MAC_PCU_CYCLE_CNT) 1683250003Sadrian 1684250003Sadrian/* Quiet time programming for TGh */ 1685250003Sadrian#define AR_QUIET1 AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1) 1686250003Sadrian#define AR_QUIET1_NEXT_QUIET_S 0 // TSF of next quiet period (TU) 1687250003Sadrian#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1688250003Sadrian#define AR_QUIET1_QUIET_ENABLE 0x00010000 // Enable Quiet time operation 1689250003Sadrian#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 // ack/cts in quiet period 1690250003Sadrian#define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 1691250003Sadrian#define AR_QUIET2 AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_2) 1692250003Sadrian#define AR_QUIET2_QUIET_PERIOD_S 0 // Periodicity of quiet period (TU) 1693250003Sadrian#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1694250003Sadrian#define AR_QUIET2_QUIET_DUR_S 16 // quiet period (TU) 1695250003Sadrian#define AR_QUIET2_QUIET_DUR 0xffff0000 1696250003Sadrian 1697250003Sadrian/* locate no_ack in qos */ 1698250003Sadrian#define AR_QOS_NO_ACK AR_MAC_PCU_OFFSET(MAC_PCU_QOS_NO_ACK) 1699250003Sadrian#define AR_QOS_NO_ACK_TWO_BIT 0x0000000f // 2 bit sentinel for no-ack 1700250003Sadrian#define AR_QOS_NO_ACK_TWO_BIT_S 0 1701250003Sadrian#define AR_QOS_NO_ACK_BIT_OFF 0x00000070 // offset for no-ack 1702250003Sadrian#define AR_QOS_NO_ACK_BIT_OFF_S 4 1703250003Sadrian#define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 // from end of header 1704250003Sadrian#define AR_QOS_NO_ACK_BYTE_OFF_S 7 1705250003Sadrian 1706250003Sadrian/* Phy errors to be filtered */ 1707250003Sadrian#define AR_PHY_ERR AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK) 1708250003Sadrian /* XXX validate! XXX */ 1709250003Sadrian#define AR_PHY_ERR_DCHIRP 0x00000008 // Bit 3 enables double chirp 1710250003Sadrian#define AR_PHY_ERR_RADAR 0x00000020 // Bit 5 is Radar signal 1711250003Sadrian#define AR_PHY_ERR_OFDM_TIMING 0x00020000 // Bit 17 is AH_FALSE detect for OFDM 1712250003Sadrian#define AR_PHY_ERR_CCK_TIMING 0x02000000 // Bit 25 is AH_FALSE detect for CCK 1713250003Sadrian 1714250003Sadrian/* MAC PCU extended range latency */ 1715250003Sadrian#define AR_XRLAT AR_MAC_PCU_OFFSET(MAC_PCU_XRLAT) 1716250003Sadrian 1717250003Sadrian/* MAC PCU Receive Buffer settings */ 1718250003Sadrian#define AR_RXFIFO_CFG AR_MAC_PCU_OFFSET(MAC_PCU_RXBUF) 1719250003Sadrian#define AR_RXFIFO_CFG_REG_RD_ENA_S 11 1720250003Sadrian#define AR_RXFIFO_CFG_REG_RD_ENA (0x1 << AR_RXFIFO_CFG_REG_RD_ENA_S) 1721250003Sadrian 1722250003Sadrian/* MAC PCU QoS control */ 1723250003Sadrian#define AR_MIC_QOS_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_CONTROL) 1724250003Sadrian/* MAC PCU Michael QoS select */ 1725250003Sadrian#define AR_MIC_QOS_SELECT AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_SELECT) 1726250003Sadrian 1727250003Sadrian/* PCU Miscellaneous Mode */ 1728250003Sadrian#define AR_PCU_MISC AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE) 1729250003Sadrian#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 // force bssid to match 1730250003Sadrian#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 // tx/rx mic key are together 1731250003Sadrian#define AR_PCU_TX_ADD_TSF 0x00000008 // add tx_tsf + int_tsf 1732250003Sadrian#define AR_PCU_CCK_SIFS_MODE 0x00000010 // assume 11b sifs programmed 1733250003Sadrian#define AR_PCU_RX_ANT_UPDT 0x00000800 // KC_RX_ANT_UPDATE 1734250003Sadrian#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 // enforce txop / tbtt 1735250003Sadrian#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 // count bmiss's when sleeping 1736250003Sadrian#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 // use rx_clear to count sifs 1737250003Sadrian#define AR_PCU_FORCE_QUIET_COLL 0x00040000 // kill xmit for channel change 1738250003Sadrian#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1739250003Sadrian#define AR_PCU_BT_ANT_PREVENT_RX_S 20 1740250003Sadrian#define AR_PCU_TBTT_PROTECT 0x00200000 // no xmit upto tbtt + 20 uS 1741250003Sadrian#define AR_PCU_CLEAR_VMF 0x01000000 // clear vmf mode (fast cc) 1742250003Sadrian#define AR_PCU_CLEAR_BA_VALID 0x04000000 // clear ba state 1743250003Sadrian#define AR_PCU_SEL_EVM 0x08000000 // select EVM data or PLCP header 1744250003Sadrian#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000 /* always perform key search */ 1745250003Sadrian/* count of filtered ofdm */ 1746250003Sadrian#define AR_FILT_OFDM AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_OFDM_CNT) 1747250003Sadrian#define AR_FILT_OFDM_COUNT 0x00FFFFFF // count of filtered ofdm 1748250003Sadrian 1749250003Sadrian/* count of filtered cck */ 1750250003Sadrian#define AR_FILT_CCK AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_CCK_CNT) 1751250003Sadrian#define AR_FILT_CCK_COUNT 0x00FFFFFF // count of filtered cck 1752250003Sadrian 1753250003Sadrian/* MAC PCU PHY error counter 1 */ 1754250003Sadrian#define AR_PHY_ERR_1 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1) 1755250003Sadrian#define AR_PHY_ERR_1_COUNT 0x00FFFFFF // phy errs that pass mask_1 1756250003Sadrian/* MAC PCU PHY error mask 1 */ 1757250003Sadrian#define AR_PHY_ERR_MASK_1 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1_MASK) 1758250003Sadrian 1759250003Sadrian/* MAC PCU PHY error counter 2 */ 1760250003Sadrian#define AR_PHY_ERR_2 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2) 1761250003Sadrian#define AR_PHY_ERR_2_COUNT 0x00FFFFFF // phy errs that pass mask_2 1762250003Sadrian/* MAC PCU PHY error mask 2 */ 1763250003Sadrian#define AR_PHY_ERR_MASK_2 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2_MASK) 1764250003Sadrian 1765250003Sadrian#define AR_PHY_COUNTMAX (3 << 22) // Max counted before intr 1766250003Sadrian#define AR_MIBCNT_INTRMASK (3 << 22) // Mask top 2 bits of counters 1767250003Sadrian 1768250003Sadrian/* interrupt if rx_tsf-int_tsf */ 1769250003Sadrian#define AR_TSFOOR_THRESHOLD AR_MAC_PCU_OFFSET(MAC_PCU_TSF_THRESHOLD) 1770250003Sadrian#define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF // field width 1771250003Sadrian 1772250003Sadrian/* MAC PCU PHY error counter 3 */ 1773250003Sadrian#define AR_PHY_ERR_3 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3) 1774250003Sadrian#define AR_PHY_ERR_3_COUNT 0x00FFFFFF // phy errs that pass mask_3 1775250003Sadrian/* MAC PCU PHY error mask 3 */ 1776250003Sadrian#define AR_PHY_ERR_MASK_3 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3_MASK) 1777250003Sadrian 1778250003Sadrian/* Bluetooth coexistance mode */ 1779250003Sadrian#define AR_BT_COEX_MODE AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE) 1780250003Sadrian#define AR_BT_TIME_EXTEND 0x000000ff 1781250003Sadrian#define AR_BT_TIME_EXTEND_S 0 1782250003Sadrian#define AR_BT_TXSTATE_EXTEND 0x00000100 1783250003Sadrian#define AR_BT_TXSTATE_EXTEND_S 8 1784250003Sadrian#define AR_BT_TX_FRAME_EXTEND 0x00000200 1785250003Sadrian#define AR_BT_TX_FRAME_EXTEND_S 9 1786250003Sadrian#define AR_BT_MODE 0x00000c00 1787250003Sadrian#define AR_BT_MODE_S 10 1788250003Sadrian#define AR_BT_QUIET 0x00001000 1789250003Sadrian#define AR_BT_QUIET_S 12 1790250003Sadrian#define AR_BT_QCU_THRESH 0x0001e000 1791250003Sadrian#define AR_BT_QCU_THRESH_S 13 1792250003Sadrian#define AR_BT_RX_CLEAR_POLARITY 0x00020000 1793250003Sadrian#define AR_BT_RX_CLEAR_POLARITY_S 17 1794250003Sadrian#define AR_BT_PRIORITY_TIME 0x00fc0000 1795250003Sadrian#define AR_BT_PRIORITY_TIME_S 18 1796250003Sadrian#define AR_BT_FIRST_SLOT_TIME 0xff000000 1797250003Sadrian#define AR_BT_FIRST_SLOT_TIME_S 24 1798250003Sadrian 1799250003Sadrian/* BlueTooth coexistance WLAN weights */ 1800250003Sadrian#define AR_BT_COEX_WL_WEIGHTS0 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS0) 1801250003Sadrian#define AR_BT_BT_WGHT 0x0000ffff 1802250003Sadrian#define AR_BT_BT_WGHT_S 0 1803250003Sadrian#define AR_BT_WL_WGHT 0xffff0000 1804250003Sadrian#define AR_BT_WL_WGHT_S 16 1805250003Sadrian 1806250003Sadrian/* HCF timeout: Slotted behavior */ 1807250003Sadrian#define AR_HCFTO AR_MAC_PCU_OFFSET(MAC_PCU_HCF_TIMEOUT) 1808250003Sadrian 1809250003Sadrian/* BlueTooth mode 2: Slotted behavior */ 1810250003Sadrian#define AR_BT_COEX_MODE2 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE2) 1811250003Sadrian#define AR_BT_BCN_MISS_THRESH 0x000000ff 1812250003Sadrian#define AR_BT_BCN_MISS_THRESH_S 0 1813250003Sadrian#define AR_BT_BCN_MISS_CNT 0x0000ff00 1814250003Sadrian#define AR_BT_BCN_MISS_CNT_S 8 1815250003Sadrian#define AR_BT_HOLD_RX_CLEAR 0x00010000 1816250003Sadrian#define AR_BT_HOLD_RX_CLEAR_S 16 1817250003Sadrian#define AR_BT_SLEEP_ALLOW_BT 0x00020000 1818250003Sadrian#define AR_BT_SLEEP_ALLOW_BT_S 17 1819250003Sadrian#define AR_BT_PROTECT_AFTER_WAKE 0x00080000 1820250003Sadrian#define AR_BT_PROTECT_AFTER_WAKE_S 19 1821250003Sadrian#define AR_BT_DISABLE_BT_ANT 0x00100000 1822250003Sadrian#define AR_BT_DISABLE_BT_ANT_S 20 1823250003Sadrian#define AR_BT_QUIET_2_WIRE 0x00200000 1824250003Sadrian#define AR_BT_QUIET_2_WIRE_S 21 1825250003Sadrian#define AR_BT_WL_ACTIVE_MODE 0x00c00000 1826250003Sadrian#define AR_BT_WL_ACTIVE_MODE_S 22 1827250003Sadrian#define AR_BT_WL_TXRX_SEPARATE 0x01000000 1828250003Sadrian#define AR_BT_WL_TXRX_SEPARATE_S 24 1829250003Sadrian#define AR_BT_RS_DISCARD_EXTEND 0x02000000 1830250003Sadrian#define AR_BT_RS_DISCARD_EXTEND_S 25 1831250003Sadrian#define AR_BT_TSF_BT_ACTIVE_CTRL 0x0c000000 1832250003Sadrian#define AR_BT_TSF_BT_ACTIVE_CTRL_S 26 1833250003Sadrian#define AR_BT_TSF_BT_PRIORITY_CTRL 0x30000000 1834250003Sadrian#define AR_BT_TSF_BT_PRIORITY_CTRL_S 28 1835250003Sadrian#define AR_BT_INTERRUPT_ENABLE 0x40000000 1836250003Sadrian#define AR_BT_INTERRUPT_ENABLE_S 30 1837250003Sadrian#define AR_BT_PHY_ERR_BT_COLL_ENABLE 0x80000000 1838250003Sadrian#define AR_BT_PHY_ERR_BT_COLL_ENABLE_S 31 1839250003Sadrian 1840250003Sadrian/* Generic Timers 2 */ 1841250003Sadrian#define AR_GEN_TIMERS2_0 AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2) 1842250003Sadrian#define AR_GEN_TIMERS2_NEXT(_i) (AR_GEN_TIMERS2_0 + ((_i)<<2)) 1843250003Sadrian#define AR_GEN_TIMERS2_PERIOD(_i) (AR_GEN_TIMERS2_NEXT(8) + ((_i)<<2)) 1844250003Sadrian 1845250003Sadrian#define AR_GEN_TIMERS2_0_NEXT AR_GEN_TIMERS2_NEXT(0) 1846250003Sadrian#define AR_GEN_TIMERS2_1_NEXT AR_GEN_TIMERS2_NEXT(1) 1847250003Sadrian#define AR_GEN_TIMERS2_2_NEXT AR_GEN_TIMERS2_NEXT(2) 1848250003Sadrian#define AR_GEN_TIMERS2_3_NEXT AR_GEN_TIMERS2_NEXT(3) 1849250003Sadrian#define AR_GEN_TIMERS2_4_NEXT AR_GEN_TIMERS2_NEXT(4) 1850250003Sadrian#define AR_GEN_TIMERS2_5_NEXT AR_GEN_TIMERS2_NEXT(5) 1851250003Sadrian#define AR_GEN_TIMERS2_6_NEXT AR_GEN_TIMERS2_NEXT(6) 1852250003Sadrian#define AR_GEN_TIMERS2_7_NEXT AR_GEN_TIMERS2_NEXT(7) 1853250003Sadrian#define AR_GEN_TIMERS2_0_PERIOD AR_GEN_TIMERS2_PERIOD(0) 1854250003Sadrian#define AR_GEN_TIMERS2_1_PERIOD AR_GEN_TIMERS2_PERIOD(1) 1855250003Sadrian#define AR_GEN_TIMERS2_2_PERIOD AR_GEN_TIMERS2_PERIOD(2) 1856250003Sadrian#define AR_GEN_TIMERS2_3_PERIOD AR_GEN_TIMERS2_PERIOD(3) 1857250003Sadrian#define AR_GEN_TIMERS2_4_PERIOD AR_GEN_TIMERS2_PERIOD(4) 1858250003Sadrian#define AR_GEN_TIMERS2_5_PERIOD AR_GEN_TIMERS2_PERIOD(5) 1859250003Sadrian#define AR_GEN_TIMERS2_6_PERIOD AR_GEN_TIMERS2_PERIOD(6) 1860250003Sadrian#define AR_GEN_TIMERS2_7_PERIOD AR_GEN_TIMERS2_PERIOD(7) 1861250003Sadrian 1862250003Sadrian#define AR_GEN_TIMER_BANK_1_LEN 8 1863250003Sadrian#define AR_FIRST_NDP_TIMER 7 1864250003Sadrian#define AR_NUM_GEN_TIMERS 16 1865250003Sadrian#define AR_GEN_TIMER_RESERVED 8 1866250003Sadrian 1867250003Sadrian/* Generic Timers 2 Mode */ 1868250003Sadrian#define AR_GEN_TIMERS2_MODE AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2_MODE) 1869250003Sadrian 1870250003Sadrian/* BlueTooth coexistance WLAN weights 1 */ 1871250003Sadrian#define AR_BT_COEX_WL_WEIGHTS1 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS1) 1872250003Sadrian 1873250003Sadrian/* BlueTooth Coexistence TSF Snapshot for BT_ACTIVE */ 1874250003Sadrian#define AR_BT_TSF_ACTIVE AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE) 1875250003Sadrian 1876250003Sadrian/* BlueTooth Coexistence TSF Snapshot for BT_PRIORITY */ 1877250003Sadrian#define AR_BT_TSF_PRIORITY AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY) 1878250003Sadrian 1879250003Sadrian/* SIFS, TX latency and ACK shift */ 1880250003Sadrian#define AR_TXSIFS AR_MAC_PCU_OFFSET(MAC_PCU_TXSIFS) 1881250003Sadrian#define AR_TXSIFS_TIME 0x000000FF // uS in SIFS 1882250003Sadrian#define AR_TXSIFS_TX_LATENCY 0x00000F00 // uS for transmission thru bb 1883250003Sadrian#define AR_TXSIFS_TX_LATENCY_S 8 1884250003Sadrian#define AR_TXSIFS_ACK_SHIFT 0x00007000 // chan width for ack 1885250003Sadrian#define AR_TXSIFS_ACK_SHIFT_S 12 1886250003Sadrian 1887250003Sadrian/* BlueTooth mode 3 */ 1888250003Sadrian#define AR_BT_COEX_MODE3 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE3) 1889250003Sadrian 1890250003Sadrian 1891250003Sadrian/* TXOP for legacy non-qos */ 1892250003Sadrian#define AR_TXOP_X AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_X) 1893250003Sadrian#define AR_TXOP_X_VAL 0x000000FF 1894250003Sadrian 1895250003Sadrian/* TXOP for TID 0 to 3 */ 1896250003Sadrian#define AR_TXOP_0_3 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_0_3) 1897250003Sadrian/* TXOP for TID 4 to 7 */ 1898250003Sadrian#define AR_TXOP_4_7 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_4_7) 1899250003Sadrian/* TXOP for TID 8 to 11 */ 1900250003Sadrian#define AR_TXOP_8_11 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_8_11) 1901250003Sadrian/* TXOP for TID 12 to 15 */ 1902250003Sadrian#define AR_TXOP_12_15 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_12_15) 1903250003Sadrian 1904250003Sadrian/* Generic Timers */ 1905250003Sadrian#define AR_GEN_TIMERS_0 AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS) 1906250003Sadrian#define AR_GEN_TIMERS(_i) (AR_GEN_TIMERS_0 + ((_i)<<2)) 1907250003Sadrian 1908250003Sadrian/* generic timers based on tsf - all uS */ 1909250003Sadrian#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) 1910250003Sadrian#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1) 1911250003Sadrian#define AR_NEXT_SWBA AR_GEN_TIMERS(2) 1912250003Sadrian#define AR_NEXT_HCF AR_GEN_TIMERS(3) 1913250003Sadrian#define AR_NEXT_TIM AR_GEN_TIMERS(4) 1914250003Sadrian#define AR_NEXT_DTIM AR_GEN_TIMERS(5) 1915250003Sadrian#define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6) 1916250003Sadrian#define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7) 1917250003Sadrian#define AR_BEACON_PERIOD AR_GEN_TIMERS(8) 1918250003Sadrian#define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9) 1919250003Sadrian#define AR_SWBA_PERIOD AR_GEN_TIMERS(10) 1920250003Sadrian#define AR_HCF_PERIOD AR_GEN_TIMERS(11) 1921250003Sadrian#define AR_TIM_PERIOD AR_GEN_TIMERS(12) 1922250003Sadrian#define AR_DTIM_PERIOD AR_GEN_TIMERS(13) 1923250003Sadrian#define AR_QUIET_PERIOD AR_GEN_TIMERS(14) 1924250003Sadrian#define AR_NDP_PERIOD AR_GEN_TIMERS(15) 1925250003Sadrian 1926250003Sadrian/* Generic Timers Mode */ 1927250003Sadrian#define AR_TIMER_MODE AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_MODE) 1928250003Sadrian#define AR_TBTT_TIMER_EN 0x00000001 1929250003Sadrian#define AR_DBA_TIMER_EN 0x00000002 1930250003Sadrian#define AR_SWBA_TIMER_EN 0x00000004 1931250003Sadrian#define AR_HCF_TIMER_EN 0x00000008 1932250003Sadrian#define AR_TIM_TIMER_EN 0x00000010 1933250003Sadrian#define AR_DTIM_TIMER_EN 0x00000020 1934250003Sadrian#define AR_QUIET_TIMER_EN 0x00000040 1935250003Sadrian#define AR_NDP_TIMER_EN 0x00000080 1936250003Sadrian#define AR_TIMER_OVERFLOW_INDEX 0x00000700 1937250003Sadrian#define AR_TIMER_OVERFLOW_INDEX_S 8 1938250003Sadrian#define AR_TIMER_THRESH 0xFFFFF000 1939250003Sadrian#define AR_TIMER_THRESH_S 12 1940250003Sadrian 1941250003Sadrian#define AR_SLP32_MODE AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_MODE) 1942250003Sadrian#define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF // rising <-> falling edge 1943250003Sadrian#define AR_SLP32_ENA 0x00100000 1944250003Sadrian#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 // tsf update in progress 1945250003Sadrian 1946250003Sadrian#define AR_SLP32_WAKE AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_WAKE) 1947250003Sadrian#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF // time to wake crystal 1948250003Sadrian 1949250003Sadrian#define AR_SLP32_INC AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_INC) 1950250003Sadrian#define AR_SLP32_TST_INC 0x000FFFFF 1951250003Sadrian 1952250003Sadrian/* Sleep MIB cycle count 32kHz cycles for which mac is asleep */ 1953250003Sadrian#define AR_SLP_CNT AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB1) 1954250003Sadrian#define AR_SLP_CYCLE_CNT 0x8254 // absolute number of 32kHz cycles 1955250003Sadrian 1956250003Sadrian/* Sleep MIB cycle count 2 */ 1957250003Sadrian#define AR_SLP_MIB2 AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB2) 1958250003Sadrian 1959250003Sadrian/* Sleep MIB control status */ 1960250003Sadrian#define AR_SLP_MIB_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB3) 1961250003Sadrian#define AR_SLP_MIB_CLEAR 0x00000001 // clear pending 1962250003Sadrian#define AR_SLP_MIB_PENDING 0x00000002 // clear counters 1963250003Sadrian 1964250003Sadrian//#ifdef AR9300_EMULATION 1965250003Sadrian// MAC trace buffer registers (emulation only) 1966250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER) 1967250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_CTL 0x0000000F 1968250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_HOLD 0x00000001 1969250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_CLEAR 0x00000002 1970250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_STATE 0x00000004 1971250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_ENABLE 0x00000008 1972250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL 0x000000F0 1973250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL_S 4 1974250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR 0x0003FF00 1975250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR_S 8 1976250003Sadrian 1977250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE 0xFFFC0000 1978250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_S 18 1979250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20614 0x00040000 1980250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1981250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20803 0x40000000 1982250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996 0x9d500010 1983250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE 0x9d400010 1984250003Sadrian 1985250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_32L AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_32L) 1986250003Sadrian#define AR_MAC_PCU_LOGIC_ANALYZER_16U AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_16U) 1987250003Sadrian 1988250003Sadrian#define AR_MAC_PCU_TRACE_REG_START 0xE000 1989250003Sadrian#define AR_MAC_PCU_TRACE_REG_END 0xFFFC 1990250003Sadrian#define AR_MAC_PCU_TRACE_BUFFER_LENGTH (AR_MAC_PCU_TRACE_REG_END - AR_MAC_PCU_TRACE_REG_START + sizeof(uint32_t)) 1991250003Sadrian//#endif // AR9300_EMULATION 1992250003Sadrian 1993250003Sadrian/* MAC PCU global mode register */ 1994250003Sadrian#define AR_2040_MODE AR_MAC_PCU_OFFSET(MAC_PCU_20_40_MODE) 1995250003Sadrian#define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca 1996250003Sadrian 1997250003Sadrian/* MAC PCU H transfer timeout register */ 1998250003Sadrian#define AR_H_XFER_TIMEOUT AR_MAC_PCU_OFFSET(MAC_PCU_H_XFER_TIMEOUT) 1999250003Sadrian#define AR_EXBF_IMMDIATE_RESP 0x00000040 2000250003Sadrian#define AR_EXBF_NOACK_NO_RPT 0x00000100 2001250003Sadrian#define AR_H_XFER_TIMEOUT_COUNT 0xf 2002250003Sadrian#define AR_H_XFER_TIMEOUT_COUNT_S 0 2003250003Sadrian 2004250003Sadrian/* 2005250003Sadrian * Additional cycle counter. See also AR_CCCNT 2006250003Sadrian * extension channel rx clear count 2007250003Sadrian * counts number of cycles rx_clear (ext) is low (i.e. busy) 2008250003Sadrian * when the MAC is not actively transmitting/receiving 2009250003Sadrian */ 2010250003Sadrian#define AR_EXTRCCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_DIFF_CNT) 2011250003Sadrian 2012250003Sadrian/* antenna mask for self generated files */ 2013250003Sadrian#define AR_SELFGEN_MASK AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_ANTENNA_MASK) 2014250003Sadrian 2015250003Sadrian/* control registers for block BA control fields */ 2016250003Sadrian#define AR_BA_BAR_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_BA_BAR_CONTROL) 2017250003Sadrian 2018250003Sadrian/* legacy PLCP spoof */ 2019250003Sadrian#define AR_LEG_PLCP_SPOOF AR_MAC_PCU_OFFSET(MAC_PCU_LEGACY_PLCP_SPOOF) 2020250003Sadrian 2021250003Sadrian/* PHY error mask and EIFS mask continued */ 2022250003Sadrian#define AR_PHY_ERR_MASK_CONT AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT) 2023250003Sadrian 2024250003Sadrian/* MAC PCU transmit timer */ 2025250003Sadrian#define AR_TX_TIMER AR_MAC_PCU_OFFSET(MAC_PCU_TX_TIMER) 2026250003Sadrian 2027250003Sadrian/* MAC PCU transmit buffer control */ 2028250003Sadrian#define AR_PCU_TXBUF_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_CTRL) 2029250003Sadrian#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 2030250003Sadrian#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 2031250003Sadrian 2032250003Sadrian/* 2033250003Sadrian * MAC PCU miscellaneous mode 2 2034250003Sadrian * WAR flags for various bugs, see mac_pcu_reg documentation. 2035250003Sadrian */ 2036250003Sadrian#define AR_PCU_MISC_MODE2 AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE2) 2037250003Sadrian#define AR_PCU_MISC_MODE2_BUG_21532_ENABLE 0x00000001 2038250003Sadrian#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 /* Decrypt MGT frames using MFP method */ 2039250003Sadrian#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 /* Don't decrypt MGT frames at all */ 2040250003Sadrian 2041250003Sadrian#define AR_BUG_58603_FIX_ENABLE 0x00000008 /* Enable fix for bug 58603. This allows 2042250003Sadrian * the use of AR_AGG_WEP_ENABLE. 2043250003Sadrian */ 2044250003Sadrian 2045250003Sadrian#define AR_PCU_MISC_MODE2_PROM_VC_MODE 0xa148103b /* Enable promiscous in azimuth mode */ 2046250003Sadrian 2047250003Sadrian#define AR_PCU_MISC_MODE2_RESERVED 0x00000038 2048250003Sadrian 2049250003Sadrian#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search 2050250003Sadrian * based on both MAC Address and Key ID. 2051250003Sadrian * If bit is 0, then Multicast search is 2052250003Sadrian * based on MAC address only. 2053250003Sadrian * For Merlin and above only. 2054250003Sadrian */ 2055250003Sadrian 2056250003Sadrian#define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 2057250003Sadrian#define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00 2058250003Sadrian#define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 2059250003Sadrian#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000 2060250003Sadrian#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature, 2061250003Sadrian * when it is enable, AGG_WEP would takes 2062250003Sadrian * charge of the encryption interface of 2063250003Sadrian * pcu_txsm. 2064250003Sadrian */ 2065250003Sadrian#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 2066250003Sadrian#define AR_PCU_MISC_MODE2_PROXY_STA 0x01000000 /* see EV 75996 */ 2067250003Sadrian#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 2068250003Sadrian#define AR_DECOUPLE_DECRYPTION 0x08000000 2069250003Sadrian 2070250003Sadrian#define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 2071250003Sadrian 2072250003Sadrian/* MAC PCU Alternate AES QoS mute mask */ 2073250003Sadrian#define AR_ALT_AES_MUTE_MASK AR_MAC_PCU_OFFSET(MAC_PCU_ALT_AES_MUTE_MASK) 2074250003Sadrian 2075250003Sadrian/* Async Fifo registers - debug only */ 2076250003Sadrian#define AR_ASYNC_FIFO_1 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG1) 2077250003Sadrian#define AR_ASYNC_FIFO_2 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG2) 2078250003Sadrian#define AR_ASYNC_FIFO_3 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG3) 2079250003Sadrian 2080250003Sadrian/* Maps the 16 user priority TID values to Access categories */ 2081250003Sadrian#define AR_TID_TO_AC_MAP AR_MAC_PCU_OFFSET(MAC_PCU_TID_TO_AC) 2082250003Sadrian 2083250003Sadrian/* High Priority Queue Control */ 2084250003Sadrian#define AR_HP_Q_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE) 2085250003Sadrian 2086250003Sadrian/* Rx High Priority Queue Control */ 2087250003Sadrian#define AR_HPQ_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE) 2088250003Sadrian#define AR_HPQ_ENABLE 0x00000001 2089250003Sadrian#define AR_HPQ_MASK_BE 0x00000002 2090250003Sadrian#define AR_HPQ_MASK_BK 0x00000004 2091250003Sadrian#define AR_HPQ_MASK_VI 0x00000008 2092250003Sadrian#define AR_HPQ_MASK_VO 0x00000010 2093250003Sadrian#define AR_HPQ_UAPSD 0x00000020 2094250003Sadrian#define AR_HPQ_FRAME_FILTER_0 0x00000040 2095250003Sadrian#define AR_HPQ_FRAME_BSSID_MATCH_0 0x00000080 2096250003Sadrian#define AR_HPQ_UAPSD_TRIGGER_EN 0x00100000 2097250003Sadrian 2098250003Sadrian#define AR_BT_COEX_BT_WEIGHTS0 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS0) 2099250003Sadrian#define AR_BT_COEX_BT_WEIGHTS1 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS1) 2100250003Sadrian#define AR_BT_COEX_BT_WEIGHTS2 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS2) 2101250003Sadrian#define AR_BT_COEX_BT_WEIGHTS3 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS3) 2102250003Sadrian 2103250003Sadrian#define AR_AGC_SATURATION_CNT0 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT0) 2104250003Sadrian#define AR_AGC_SATURATION_CNT1 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT1) 2105250003Sadrian#define AR_AGC_SATURATION_CNT2 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT2) 2106250003Sadrian 2107250003Sadrian/* Hardware beacon processing */ 2108250003Sadrian#define AR_HWBCNPROC1 AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC1) 2109250003Sadrian#define AR_HWBCNPROC1_CRC_ENABLE 0x00000001 /* Enable hw beacon processing */ 2110250003Sadrian#define AR_HWBCNPROC1_RESET_CRC 0x00000002 /* Reset the last beacon CRC calculated */ 2111250003Sadrian#define AR_HWBCNPROC1_EXCLUDE_BCN_INTVL 0x00000004 /* Exclude Beacon interval in CRC calculation */ 2112250003Sadrian#define AR_HWBCNPROC1_EXCLUDE_CAP_INFO 0x00000008 /* Exclude Beacon capability information in CRC calculation */ 2113250003Sadrian#define AR_HWBCNPROC1_EXCLUDE_TIM_ELM 0x00000010 /* Exclude Beacon TIM element in CRC calculation */ 2114250003Sadrian#define AR_HWBCNPROC1_EXCLUDE_ELM0 0x00000020 /* Exclude element ID ELM0 in CRC calculation */ 2115250003Sadrian#define AR_HWBCNPROC1_EXCLUDE_ELM1 0x00000040 /* Exclude element ID ELM1 in CRC calculation */ 2116250003Sadrian#define AR_HWBCNPROC1_EXCLUDE_ELM2 0x00000080 /* Exclude element ID ELM2 in CRC calculation */ 2117250003Sadrian#define AR_HWBCNPROC1_ELM0_ID 0x0000FF00 /* Element ID 0 */ 2118250003Sadrian#define AR_HWBCNPROC1_ELM0_ID_S 8 2119250003Sadrian#define AR_HWBCNPROC1_ELM1_ID 0x00FF0000 /* Element ID 1 */ 2120250003Sadrian#define AR_HWBCNPROC1_ELM1_ID_S 16 2121250003Sadrian#define AR_HWBCNPROC1_ELM2_ID 0xFF000000 /* Element ID 2 */ 2122250003Sadrian#define AR_HWBCNPROC1_ELM2_ID_S 24 2123250003Sadrian 2124250003Sadrian#define AR_HWBCNPROC2 AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC2) 2125250003Sadrian#define AR_HWBCNPROC2_FILTER_INTERVAL_ENABLE 0x00000001 /* Enable filtering beacons based on filter interval */ 2126250003Sadrian#define AR_HWBCNPROC2_RESET_INTERVAL 0x00000002 /* Reset internal interval counter interval */ 2127250003Sadrian#define AR_HWBCNPROC2_EXCLUDE_ELM3 0x00000004 /* Exclude element ID ELM3 in CRC calculation */ 2128250003Sadrian#define AR_HWBCNPROC2_RSVD 0x000000F8 /* reserved */ 2129250003Sadrian#define AR_HWBCNPROC2_FILTER_INTERVAL 0x0000FF00 /* Filter interval for beacons */ 2130250003Sadrian#define AR_HWBCNPROC2_FILTER_INTERVAL_S 8 2131250003Sadrian#define AR_HWBCNPROC2_ELM3_ID 0x00FF0000 /* Element ID 3 */ 2132250003Sadrian#define AR_HWBCNPROC2_ELM3_ID_S 16 2133250003Sadrian#define AR_HWBCNPROC2_RSVD2 0xFF000000 /* reserved */ 2134250003Sadrian 2135250003Sadrian#define AR_MAC_PCU_MISC_MODE3 AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE3) 2136250003Sadrian#define AR_BUG_61936_FIX_ENABLE 0x00000040 /* EV61936 - rx descriptor corruption */ 2137250003Sadrian#define AR_TIME_BASED_DISCARD_EN 0x80000000 2138250003Sadrian#define AR_TIME_BASED_DISCARD_EN_S 31 2139250003Sadrian 2140250003Sadrian#define AR_MAC_PCU_GEN_TIMER_TSF_SEL AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_TSF_SEL) 2141250003Sadrian 2142250003Sadrian#define AR_MAC_PCU_TBD_FILTER AR_MAC_PCU_OFFSET(MAC_PCU_TBD_FILTER) 2143250003Sadrian#define AR_MAC_PCU_USE_WBTIMER_TX_TS 0x00000001 2144250003Sadrian#define AR_MAC_PCU_USE_WBTIMER_TX_TS_S 0 2145250003Sadrian#define AR_MAC_PCU_USE_WBTIMER_RX_TS 0x00000002 2146250003Sadrian#define AR_MAC_PCU_USE_WBTIMER_RX_TS_S 1 2147250003Sadrian 2148250003Sadrian#define AR_TXBUF_BA AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_BA) 2149250003Sadrian 2150250003Sadrian 2151250003Sadrian/* MAC Key Cache */ 2152250003Sadrian#define AR_KEYTABLE_0 AR_MAC_PCU_OFFSET(MAC_PCU_KEY_CACHE) 2153250003Sadrian#define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) 2154250003Sadrian#define AR_KEY_CACHE_SIZE 128 2155250003Sadrian#define AR_RSVD_KEYTABLE_ENTRIES 4 2156250003Sadrian#define AR_KEY_TYPE 0x00000007 // MAC Key Type Mask 2157250003Sadrian#define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */ 2158250003Sadrian#define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */ 2159250003Sadrian#define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */ 2160250003Sadrian#define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */ 2161250003Sadrian#define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */ 2162250003Sadrian#define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */ 2163250003Sadrian#define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */ 2164250003Sadrian#define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */ 2165250003Sadrian#define AR_KEYTABLE_UAPSD 0x000001E0 /* UAPSD AC mask */ 2166250003Sadrian#define AR_KEYTABLE_UAPSD_S 5 2167250003Sadrian#define AR_KEYTABLE_PWRMGT 0x00000200 /* hw managed PowerMgt bit */ 2168250003Sadrian 2169250003Sadrian#define AR_KEYTABLE_MMSS 0x00001c00 /* remote's MMSS*/ 2170250003Sadrian#define AR_KEYTABLE_MMSS_S 10 2171250003Sadrian#define AR_KEYTABLE_CEC 0x00006000 /* remote's CEC*/ 2172250003Sadrian#define AR_KEYTABLE_CEC_S 13 2173250003Sadrian#define AR_KEYTABLE_STAGGED 0x00010000 /* remote's stagged sounding*/ 2174250003Sadrian#define AR_KEYTABLE_STAGGED_S 16 2175250003Sadrian 2176250003Sadrian#define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ 2177250003Sadrian#define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */ 2178250003Sadrian#define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */ 2179250003Sadrian#define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */ 2180250003Sadrian#define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */ 2181250003Sadrian#define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */ 2182250003Sadrian#define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) /* key type */ 2183250003Sadrian#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */ 2184250003Sadrian#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */ 2185250003Sadrian#define AR_KEYTABLE_DIR_ACK_BIT 0x00000010 /* Directed ACK bit */ 2186250003Sadrian 2187250003Sadrian 2188250003Sadrian 2189250003Sadrian/* 2190250003Sadrian * MAC WoW Registers. 2191250003Sadrian */ 2192250003Sadrian#define AR_WOW_PATTERN_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW1) 2193250003Sadrian#define AR_WOW_PAT_BACKOFF 0x00000004 2194250003Sadrian#define AR_WOW_BACK_OFF_SHIFT(x) ((x & 0xf) << 27) /* in usecs */ 2195250003Sadrian#define AR_WOW_MAC_INTR_EN 0x00040000 2196250003Sadrian#define AR_WOW_MAGIC_EN 0x00010000 2197250003Sadrian#define AR_WOW_PATTERN_EN(x) ((x & 0xff) << 0) 2198250003Sadrian#define AR_WOW_PATTERN_FOUND_SHIFT 8 2199250003Sadrian#define AR_WOW_PATTERN_FOUND(x) (x & (0xff << AR_WOW_PATTERN_FOUND_SHIFT)) 2200250003Sadrian#define AR_WOW_PATTERN_FOUND_MASK ((0xff) << AR_WOW_PATTERN_FOUND_SHIFT) 2201250003Sadrian#define AR_WOW_MAGIC_PAT_FOUND 0x00020000 2202250003Sadrian#define AR_WOW_MAC_INTR 0x00080000 2203250003Sadrian#define AR_WOW_KEEP_ALIVE_FAIL 0x00100000 2204250003Sadrian#define AR_WOW_BEACON_FAIL 0x00200000 2205250003Sadrian 2206250003Sadrian 2207250003Sadrian#define AR_WOW_COUNT_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW2) 2208250003Sadrian#define AR_WOW_AIFS_CNT(x) ((x & 0xff) << 0) 2209250003Sadrian#define AR_WOW_SLOT_CNT(x) ((x & 0xff) << 8) 2210250003Sadrian#define AR_WOW_KEEP_ALIVE_CNT(x) ((x & 0xff) << 16) 2211250003Sadrian/* 2212250003Sadrian * Default values for Wow Configuration for backoff, aifs, slot, keep-alive, etc. 2213250003Sadrian * to be programmed into various registers. 2214250003Sadrian */ 2215250003Sadrian#define AR_WOW_CNT_AIFS_CNT 0x00000022 // AR_WOW_COUNT_REG 2216250003Sadrian#define AR_WOW_CNT_SLOT_CNT 0x00000009 // AR_WOW_COUNT_REG 2217250003Sadrian/* 2218250003Sadrian * Keepalive count applicable for Merlin 2.0 and above. 2219250003Sadrian */ 2220250003Sadrian#define AR_WOW_CNT_KA_CNT 0x00000008 // AR_WOW_COUNT_REG 2221250003Sadrian 2222250003Sadrian 2223250003Sadrian#define AR_WOW_BCN_EN_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON_FAIL) 2224250003Sadrian#define AR_WOW_BEACON_FAIL_EN 0x00000001 2225250003Sadrian 2226250003Sadrian#define AR_WOW_BCN_TIMO_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON) 2227250003Sadrian#define AR_WOW_BEACON_TIMO 0x40000000 /* Valid if BCN_EN is set */ 2228250003Sadrian#define AR_WOW_BEACON_TIMO_MAX 0xFFFFFFFF /* Max. value for Beacon Timeout */ 2229250003Sadrian 2230250003Sadrian#define AR_WOW_KEEP_ALIVE_TIMO_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_KEEP_ALIVE) 2231250003Sadrian#define AR_WOW_KEEP_ALIVE_TIMO 0x00007A12 2232250003Sadrian#define AR_WOW_KEEP_ALIVE_NEVER 0xFFFFFFFF 2233250003Sadrian 2234250003Sadrian#define AR_WOW_KEEP_ALIVE_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_KA) 2235250003Sadrian#define AR_WOW_KEEP_ALIVE_AUTO_DIS 0x00000001 2236250003Sadrian#define AR_WOW_KEEP_ALIVE_FAIL_DIS 0x00000002 2237250003Sadrian 2238250003Sadrian#define AR_WOW_US_SCALAR_REG AR_MAC_PCU_OFFSET(PCU_1US) 2239250003Sadrian 2240250003Sadrian#define AR_WOW_KEEP_ALIVE_DELAY_REG AR_MAC_PCU_OFFSET(PCU_KA) 2241250003Sadrian#define AR_WOW_KEEP_ALIVE_DELAY 0x000003E8 // 1 msec 2242250003Sadrian 2243250003Sadrian#define AR_WOW_PATTERN_MATCH_REG AR_MAC_PCU_OFFSET(WOW_EXACT) 2244250003Sadrian#define AR_WOW_PAT_END_OF_PKT(x) ((x & 0xf) << 0) 2245250003Sadrian#define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8) 2246250003Sadrian 2247250003Sadrian#define AR_WOW_PATTERN_MATCH_REG_2 AR_MAC_PCU_OFFSET(WOW2_EXACT) 2248250003Sadrian#define AR_WOW_PATTERN_OFF1_REG AR_MAC_PCU_OFFSET(PCU_WOW4) /* Pattern bytes 0 -> 3 */ 2249250003Sadrian#define AR_WOW_PATTERN_OFF2_REG AR_MAC_PCU_OFFSET(PCU_WOW5) /* Pattern bytes 4 -> 7 */ 2250250003Sadrian#define AR_WOW_PATTERN_OFF3_REG AR_MAC_PCU_OFFSET(PCU_WOW6) /* Pattern bytes 8 -> 11 */ 2251250003Sadrian#define AR_WOW_PATTERN_OFF4_REG AR_MAC_PCU_OFFSET(PCU_WOW7) /* Pattern bytes 12 -> 15 */ 2252250003Sadrian 2253250003Sadrian/* start address of the frame in RxBUF */ 2254250003Sadrian#define AR_WOW_RXBUF_START_ADDR AR_MAC_PCU_OFFSET(MAC_PCU_WOW6) 2255250003Sadrian 2256250003Sadrian/* Pattern detect and enable bits */ 2257250003Sadrian#define AR_WOW_PATTERN_DETECT_ENABLE AR_MAC_PCU_OFFSET(MAC_PCU_WOW4) 2258250003Sadrian 2259250003Sadrian/* Rx Abort Enable */ 2260250003Sadrian#define AR_WOW_RX_ABORT_ENABLE AR_MAC_PCU_OFFSET(MAC_PCU_WOW5) 2261250003Sadrian 2262250003Sadrian/* PHY error counter 1, 2, and 3 mask continued */ 2263250003Sadrian#define AR_PHY_ERR_CNT_MASK_CONT AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_MASK_CONT) 2264250003Sadrian 2265250003Sadrian/* AZIMUTH mode reg can be used for proxySTA */ 2266250003Sadrian#define AR_AZIMUTH_MODE AR_MAC_PCU_OFFSET(MAC_PCU_AZIMUTH_MODE) 2267250003Sadrian#define AR_AZIMUTH_KEY_SEARCH_AD1 0x00000002 2268250003Sadrian#define AR_AZIMUTH_CTS_MATCH_TX_AD2 0x00000040 2269250003Sadrian#define AR_AZIMUTH_BA_USES_AD1 0x00000080 2270250003Sadrian#define AR_AZIMUTH_FILTER_PASS_HOLD 0x00000200 2271250003Sadrian 2272250003Sadrian/* Length of Pattern Match for Pattern */ 2273250003Sadrian#define AR_WOW_LENGTH1_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH1) 2274250003Sadrian#define AR_WOW_LENGTH2_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH2) 2275250003Sadrian#define AR_WOW_LENGTH3_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH3) 2276250003Sadrian#define AR_WOW_LENGTH4_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH4) 2277250003Sadrian 2278250003Sadrian#define AR_LOC_CTL_REG AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_CONTROL) 2279250003Sadrian#define AR_LOC_TIMER_REG AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_TIMER) 2280250003Sadrian#define AR_LOC_CTL_REG_FS 0x1 2281250003Sadrian 2282250003Sadrian/* Register to enable pattern match for less than 256 bytes packets */ 2283250003Sadrian#define AR_WOW_PATTERN_MATCH_LT_256B_REG AR_MAC_PCU_OFFSET(WOW_PATTERN_MATCH_LESS_THAN_256_BYTES) 2284250003Sadrian 2285250003Sadrian 2286250003Sadrian#define AR_WOW_STATUS(x) (x & (AR_WOW_PATTERN_FOUND_MASK | AR_WOW_MAGIC_PAT_FOUND | \ 2287250003Sadrian AR_WOW_KEEP_ALIVE_FAIL | AR_WOW_BEACON_FAIL)) 2288250003Sadrian#define AR_WOW_CLEAR_EVENTS(x) (x & ~(AR_WOW_PATTERN_EN(0xff) | \ 2289250003Sadrian AR_WOW_MAGIC_EN | AR_WOW_MAC_INTR_EN | AR_WOW_BEACON_FAIL | \ 2290250003Sadrian AR_WOW_KEEP_ALIVE_FAIL)) 2291250003Sadrian 2292250003Sadrian 2293250003Sadrian/* 2294250003Sadrian * Keep it long for Beacon workaround - ensures no AH_FALSE alarm 2295250003Sadrian */ 2296250003Sadrian#define AR_WOW_BMISSTHRESHOLD 0x20 2297250003Sadrian 2298250003Sadrian 2299250003Sadrian/* WoW - Transmit buffer for keep alive frames */ 2300250003Sadrian#define AR_WOW_TRANSMIT_BUFFER AR_MAC_PCU_OFFSET(MAC_PCU_BUF) 2301250003Sadrian#define AR_WOW_TXBUF(_i) (AR_WOW_TRANSMIT_BUFFER + ((_i)<<2)) 2302250003Sadrian 2303250003Sadrian#define AR_WOW_KA_DESC_WORD2 AR_WOW_TXBUF(0) 2304250003Sadrian#define AR_WOW_KA_DESC_WORD3 AR_WOW_TXBUF(1) 2305250003Sadrian#define AR_WOW_KA_DESC_WORD4 AR_WOW_TXBUF(2) 2306250003Sadrian#define AR_WOW_KA_DESC_WORD5 AR_WOW_TXBUF(3) 2307250003Sadrian#define AR_WOW_KA_DESC_WORD6 AR_WOW_TXBUF(4) 2308250003Sadrian#define AR_WOW_KA_DESC_WORD7 AR_WOW_TXBUF(5) 2309250003Sadrian#define AR_WOW_KA_DESC_WORD8 AR_WOW_TXBUF(6) 2310250003Sadrian#define AR_WOW_KA_DESC_WORD9 AR_WOW_TXBUF(7) 2311250003Sadrian#define AR_WOW_KA_DESC_WORD10 AR_WOW_TXBUF(8) 2312250003Sadrian#define AR_WOW_KA_DESC_WORD11 AR_WOW_TXBUF(9) 2313250003Sadrian#define AR_WOW_KA_DESC_WORD12 AR_WOW_TXBUF(10) 2314250003Sadrian#define AR_WOW_KA_DESC_WORD13 AR_WOW_TXBUF(11) 2315250003Sadrian 2316250003Sadrian/* KA_DATA_WORD = 6 words. Depending on the number of 2317250003Sadrian * descriptor words, it can start at AR_WOW_TXBUF(12) 2318250003Sadrian * or AR_WOW_TXBUF(13) */ 2319250003Sadrian 2320250003Sadrian#define AR_WOW_OFFLOAD_GTK_DATA_START AR_WOW_TXBUF(19) 2321250003Sadrian 2322250003Sadrian#define AR_WOW_KA_DATA_WORD_END_JUPITER AR_WOW_TXBUF(60) 2323250003Sadrian 2324250003Sadrian#define AR_WOW_SW_NULL_PARAMETER AR_WOW_TXBUF(61) 2325250003Sadrian#define AR_WOW_SW_NULL_LONG_PERIOD_MASK 0x0000FFFF 2326250003Sadrian#define AR_WOW_SW_NULL_LONG_PERIOD_MASK_S 0 2327250003Sadrian#define AR_WOW_SW_NULL_SHORT_PERIOD_MASK 0xFFFF0000 2328250003Sadrian#define AR_WOW_SW_NULL_SHORT_PERIOD_MASK_S 16 2329250003Sadrian 2330250003Sadrian#define AR_WOW_OFFLOAD_COMMAND_JUPITER AR_WOW_TXBUF(62) 2331250003Sadrian#define AR_WOW_OFFLOAD_ENA_GTK 0x80000000 2332250003Sadrian#define AR_WOW_OFFLOAD_ENA_ACER_MAGIC 0x40000000 2333250003Sadrian#define AR_WOW_OFFLOAD_ENA_STD_MAGIC 0x20000000 2334250003Sadrian#define AR_WOW_OFFLOAD_ENA_SWKA 0x10000000 2335250003Sadrian#define AR_WOW_OFFLOAD_ENA_ARP_OFFLOAD 0x08000000 2336250003Sadrian#define AR_WOW_OFFLOAD_ENA_NS_OFFLOAD 0x04000000 2337250003Sadrian#define AR_WOW_OFFLOAD_ENA_4WAY_WAKE 0x02000000 2338250003Sadrian#define AR_WOW_OFFLOAD_ENA_GTK_ERROR_WAKE 0x01000000 2339250003Sadrian#define AR_WOW_OFFLOAD_ENA_AP_LOSS_WAKE 0x00800000 2340250003Sadrian#define AR_WOW_OFFLOAD_ENA_BT_SLEEP 0x00080000 2341250003Sadrian#define AR_WOW_OFFLOAD_ENA_SW_NULL 0x00040000 2342250003Sadrian#define AR_WOW_OFFLOAD_ENA_HWKA_FAIL 0x00020000 2343250003Sadrian#define AR_WOW_OFFLOAD_ENA_DEVID_SWAR 0x00010000 2344250003Sadrian 2345250003Sadrian#define AR_WOW_OFFLOAD_STATUS_JUPITER AR_WOW_TXBUF(63) 2346250003Sadrian 2347250003Sadrian/* WoW Transmit Buffer for patterns */ 2348250003Sadrian#define AR_WOW_TB_PATTERN0 AR_WOW_TXBUF(64) 2349250003Sadrian#define AR_WOW_TB_PATTERN1 AR_WOW_TXBUF(128) 2350250003Sadrian#define AR_WOW_TB_PATTERN2 AR_WOW_TXBUF(192) 2351250003Sadrian#define AR_WOW_TB_PATTERN3 AR_WOW_TXBUF(256) 2352250003Sadrian#define AR_WOW_TB_PATTERN4 AR_WOW_TXBUF(320) 2353250003Sadrian#define AR_WOW_TB_PATTERN5 AR_WOW_TXBUF(384) 2354250003Sadrian#define AR_WOW_TB_PATTERN6 AR_WOW_TXBUF(448) 2355250003Sadrian#define AR_WOW_TB_PATTERN7 AR_WOW_TXBUF(512) 2356250003Sadrian#define AR_WOW_TB_MASK0 AR_WOW_TXBUF(768) 2357250003Sadrian#define AR_WOW_TB_MASK1 AR_WOW_TXBUF(776) 2358250003Sadrian#define AR_WOW_TB_MASK2 AR_WOW_TXBUF(784) 2359250003Sadrian#define AR_WOW_TB_MASK3 AR_WOW_TXBUF(792) 2360250003Sadrian#define AR_WOW_TB_MASK4 AR_WOW_TXBUF(800) 2361250003Sadrian#define AR_WOW_TB_MASK5 AR_WOW_TXBUF(808) 2362250003Sadrian#define AR_WOW_TB_MASK6 AR_WOW_TXBUF(816) 2363250003Sadrian#define AR_WOW_TB_MASK7 AR_WOW_TXBUF(824) 2364250003Sadrian 2365250003Sadrian 2366250003Sadrian#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START AR_WOW_TXBUF(825) 2367250003Sadrian#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START_JUPITER AR_WOW_TXBUF(832) 2368250003Sadrian#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_WORDS 4 2369250003Sadrian 2370250003Sadrian#define AR_WOW_OFFLOAD_GTK_DATA_START_JUPITER AR_WOW_TXBUF(836) 2371250003Sadrian#define AR_WOW_OFFLOAD_GTK_DATA_WORDS_JUPITER 20 2372250003Sadrian 2373250003Sadrian#define AR_WOW_OFFLOAD_ACER_MAGIC_START AR_WOW_TXBUF(856) 2374250003Sadrian#define AR_WOW_OFFLOAD_ACER_MAGIC_WORDS 2 2375250003Sadrian 2376250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA0_START AR_WOW_TXBUF(858) 2377250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA0_PERIOD_MS AR_WOW_TXBUF(858) 2378250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA0_SIZE AR_WOW_TXBUF(859) 2379250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA0_DATA AR_WOW_TXBUF(860) 2380250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA0_DATA_WORDS 20 2381250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA0_WORDS 22 2382250003Sadrian 2383250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA1_START AR_WOW_TXBUF(880) 2384250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA1_PERIOD_MS AR_WOW_TXBUF(880) 2385250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA1_SIZE AR_WOW_TXBUF(881) 2386250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA1_DATA AR_WOW_TXBUF(882) 2387250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA1_DATA_WORDS 20 2388250003Sadrian#define AR_WOW_OFFLOAD_ACER_KA1_WORDS 22 2389250003Sadrian 2390250003Sadrian#define AR_WOW_OFFLOAD_ARP0_START AR_WOW_TXBUF(902) 2391250003Sadrian#define AR_WOW_OFFLOAD_ARP0_VALID AR_WOW_TXBUF(902) 2392250003Sadrian#define AR_WOW_OFFLOAD_ARP0_RMT_IP AR_WOW_TXBUF(903) 2393250003Sadrian#define AR_WOW_OFFLOAD_ARP0_HOST_IP AR_WOW_TXBUF(904) 2394250003Sadrian#define AR_WOW_OFFLOAD_ARP0_MAC_L AR_WOW_TXBUF(905) 2395250003Sadrian#define AR_WOW_OFFLOAD_ARP0_MAC_H AR_WOW_TXBUF(906) 2396250003Sadrian#define AR_WOW_OFFLOAD_ARP0_WORDS 5 2397250003Sadrian 2398250003Sadrian#define AR_WOW_OFFLOAD_ARP1_START AR_WOW_TXBUF(907) 2399250003Sadrian#define AR_WOW_OFFLOAD_ARP1_VALID AR_WOW_TXBUF(907) 2400250003Sadrian#define AR_WOW_OFFLOAD_ARP1_RMT_IP AR_WOW_TXBUF(908) 2401250003Sadrian#define AR_WOW_OFFLOAD_ARP1_HOST_IP AR_WOW_TXBUF(909) 2402250003Sadrian#define AR_WOW_OFFLOAD_ARP1_MAC_L AR_WOW_TXBUF(910) 2403250003Sadrian#define AR_WOW_OFFLOAD_ARP1_MAC_H AR_WOW_TXBUF(911) 2404250003Sadrian#define AR_WOW_OFFLOAD_ARP1_WORDS 5 2405250003Sadrian 2406250003Sadrian#define AR_WOW_OFFLOAD_NS0_START AR_WOW_TXBUF(912) 2407250003Sadrian#define AR_WOW_OFFLOAD_NS0_VALID AR_WOW_TXBUF(912) 2408250003Sadrian#define AR_WOW_OFFLOAD_NS0_RMT_IPV6 AR_WOW_TXBUF(913) 2409250003Sadrian#define AR_WOW_OFFLOAD_NS0_SOLICIT_IPV6 AR_WOW_TXBUF(917) 2410250003Sadrian#define AR_WOW_OFFLOAD_NS0_MAC_L AR_WOW_TXBUF(921) 2411250003Sadrian#define AR_WOW_OFFLOAD_NS0_MAC_H AR_WOW_TXBUF(922) 2412250003Sadrian#define AR_WOW_OFFLOAD_NS0_TGT0_IPV6 AR_WOW_TXBUF(923) 2413250003Sadrian#define AR_WOW_OFFLOAD_NS0_TGT1_IPV6 AR_WOW_TXBUF(927) 2414250003Sadrian#define AR_WOW_OFFLOAD_NS0_WORDS 19 2415250003Sadrian 2416250003Sadrian#define AR_WOW_OFFLOAD_NS1_START AR_WOW_TXBUF(931) 2417250003Sadrian#define AR_WOW_OFFLOAD_NS1_VALID AR_WOW_TXBUF(931) 2418250003Sadrian#define AR_WOW_OFFLOAD_NS1_RMT_IPV6 AR_WOW_TXBUF(932) 2419250003Sadrian#define AR_WOW_OFFLOAD_NS1_SOLICIT_IPV6 AR_WOW_TXBUF(936) 2420250003Sadrian#define AR_WOW_OFFLOAD_NS1_MAC_L AR_WOW_TXBUF(940) 2421250003Sadrian#define AR_WOW_OFFLOAD_NS1_MAC_H AR_WOW_TXBUF(941) 2422250003Sadrian#define AR_WOW_OFFLOAD_NS1_TGT0_IPV6 AR_WOW_TXBUF(942) 2423250003Sadrian#define AR_WOW_OFFLOAD_NS1_TGT1_IPV6 AR_WOW_TXBUF(946) 2424250003Sadrian#define AR_WOW_OFFLOAD_NS1_WORDS 19 2425250003Sadrian 2426250003Sadrian#define AR_WOW_OFFLOAD_WLAN_REGSET_START AR_WOW_TXBUF(950) 2427250003Sadrian#define AR_WOW_OFFLOAD_WLAN_REGSET_NUM AR_WOW_TXBUF(950) 2428250003Sadrian#define AR_WOW_OFFLOAD_WLAN_REGSET_REGVAL AR_WOW_TXBUF(951) 2429250003Sadrian#define AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR 32 2430250003Sadrian#define AR_WOW_OFFLOAD_WLAN_REGSET_WORDS 65 //(1 + AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR * 2) 2431250003Sadrian 2432250003Sadrian/* Currently Pattern 0-7 are supported - so bit 0-7 are set */ 2433250003Sadrian#define AR_WOW_PATTERN_SUPPORTED 0xFF 2434250003Sadrian#define AR_WOW_LENGTH_MAX 0xFF 2435250003Sadrian#define AR_WOW_LENGTH1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3) 2436250003Sadrian#define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH1_SHIFT(_i)) 2437250003Sadrian#define AR_WOW_LENGTH2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3) 2438250003Sadrian#define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH2_SHIFT(_i)) 2439250003Sadrian 2440250003Sadrian/* 2441250003Sadrian * MAC Direct Connect registers 2442250003Sadrian * 2443250003Sadrian * Added to support dual BSSID/TSF which are needed in the application 2444250003Sadrian * of Mesh networking or Direct Connect. 2445250003Sadrian */ 2446250003Sadrian 2447250003Sadrian/* 2448250003Sadrian * Note that the only function added with this BSSID2 is to receive 2449250003Sadrian * multi/broadcast from BSSID2 as well 2450250003Sadrian */ 2451250003Sadrian/* MAC BSSID low 32 bits */ 2452250003Sadrian#define AR_BSS2_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32) 2453250003Sadrian/* MAC BSSID upper 16 bits / AID */ 2454250003Sadrian#define AR_BSS2_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16) 2455250003Sadrian 2456250003Sadrian/* 2457250003Sadrian * Secondary TSF support added for dual BSSID/TSF 2458250003Sadrian */ 2459250003Sadrian/* MAC local clock lower 32 bits */ 2460250003Sadrian#define AR_TSF2_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32) 2461250003Sadrian/* MAC local clock upper 32 bits */ 2462250003Sadrian#define AR_TSF2_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32) 2463250003Sadrian 2464250003Sadrian/* MAC Direct Connect Control */ 2465250003Sadrian#define AR_DIRECT_CONNECT AR_MAC_PCU_OFFSET(MAC_PCU_DIRECT_CONNECT) 2466250003Sadrian#define AR_DC_AP_STA_EN 0x00000001 2467250003Sadrian#define AR_DC_AP_STA_EN_S 0 2468250003Sadrian 2469250003Sadrian/* 2470250003Sadrian * tx_bf Register 2471250003Sadrian */ 2472250003Sadrian#define AR_SVD_OFFSET(_x) offsetof(struct svd_reg, _x) 2473250003Sadrian 2474250003Sadrian#define AR_TXBF_DBG AR_SVD_OFFSET(TXBF_DBG) 2475250003Sadrian 2476250003Sadrian#define AR_TXBF AR_SVD_OFFSET(TXBF) 2477250003Sadrian#define AR_TXBF_CB_TX 0x00000003 2478250003Sadrian#define AR_TXBF_CB_TX_S 0 2479250003Sadrian#define AR_TXBF_PSI_1_PHI_3 0 2480250003Sadrian#define AR_TXBF_PSI_2_PHI_4 1 2481250003Sadrian#define AR_TXBF_PSI_3_PHI_5 2 2482250003Sadrian#define AR_TXBF_PSI_4_PHI_6 3 2483250003Sadrian 2484250003Sadrian#define AR_TXBF_NB_TX 0x0000000C 2485250003Sadrian#define AR_TXBF_NB_TX_S 2 2486250003Sadrian#define AR_TXBF_NUMBEROFBIT_4 0 2487250003Sadrian#define AR_TXBF_NUMBEROFBIT_2 1 2488250003Sadrian#define AR_TXBF_NUMBEROFBIT_6 2 2489250003Sadrian#define AR_TXBF_NUMBEROFBIT_8 3 2490250003Sadrian 2491250003Sadrian#define AR_TXBF_NG_RPT_TX 0x00000030 2492250003Sadrian#define AR_TXBF_NG_RPT_TX_S 4 2493250003Sadrian#define AR_TXBF_No_GROUP 0 2494250003Sadrian#define AR_TXBF_TWO_GROUP 1 2495250003Sadrian#define AR_TXBF_FOUR_GROUP 2 2496250003Sadrian 2497250003Sadrian#define AR_TXBF_NG_CVCACHE 0x000000C0 2498250003Sadrian#define AR_TXBF_NG_CVCACHE_S 6 2499250003Sadrian#define AR_TXBF_FOUR_CLIENTS 0 2500250003Sadrian#define AR_TXBF_EIGHT_CLIENTS 1 2501250003Sadrian#define AR_TXBF_SIXTEEN_CLIENTS 2 2502250003Sadrian 2503250003Sadrian#define AR_TXBF_TXCV_BFWEIGHT_METHOD 0x00000600 2504250003Sadrian#define AR_TXBF_TXCV_BFWEIGHT_METHOD_S 9 2505250003Sadrian#define AR_TXBF_NO_WEIGHTING 0 2506250003Sadrian#define AR_TXBF_MAX_POWER 1 2507250003Sadrian#define AR_TXBF_KEEP_RATIO 2 2508250003Sadrian 2509250003Sadrian#define AR_TXBF_RLR_EN 0x00000800 2510250003Sadrian#define AR_TXBF_RC_20_U_DONE 0x00001000 2511250003Sadrian#define AR_TXBF_RC_20_L_DONE 0x00002000 2512250003Sadrian#define AR_TXBF_RC_40_DONE 0x00004000 2513250003Sadrian#define AR_TXBF_FORCE_UPDATE_V2BB 0x00008000 2514250003Sadrian 2515250003Sadrian#define AR_TXBF_TIMER AR_SVD_OFFSET(TXBF_TIMER) 2516250003Sadrian#define AR_TXBF_TIMER_TIMEOUT 0x000000FF 2517250003Sadrian#define AR_TXBF_TIMER_TIMEOUT_S 0 2518250003Sadrian#define AR_TXBF_TIMER_ATIMEOU 0x0000FF00 2519250003Sadrian#define AR_TXBF_TIMER_ATIMEOUT_S 8 2520250003Sadrian 2521250003Sadrian/* for SVD cache update */ 2522250003Sadrian#define AR_TXBF_SW AR_SVD_OFFSET(TXBF_SW) 2523250003Sadrian#define AR_LRU_ACK 0x00000001 2524250003Sadrian#define AR_LRU_ADDR 0x000003FE 2525250003Sadrian#define AR_LRU_ADDR_S 1 2526250003Sadrian#define AR_LRU_EN 0x00000800 2527250003Sadrian#define AR_LRU_EN_S 11 2528250003Sadrian#define AR_DEST_IDX 0x0007f000 2529250003Sadrian#define AR_DEST_IDX_S 12 2530250003Sadrian#define AR_LRU_WR_ACK 0x00080000 2531250003Sadrian#define AR_LRU_WR_ACK_S 19 2532250003Sadrian#define AR_LRU_RD_ACK 0x00100000 2533250003Sadrian#define AR_LRU_RD_ACK_S 20 2534250003Sadrian 2535250003Sadrian#define AR_RC0_0 AR_SVD_OFFSET(RC0) 2536250003Sadrian#define AR_RC0(_idx) (AR_RC0_0+(_idx)) 2537250003Sadrian#define AR_RC1_0 AR_SVD_OFFSET(RC1) 2538250003Sadrian#define AR_RC1(_idx) (AR_RC1_0+(_idx)) 2539250003Sadrian 2540250003Sadrian#define AR_CVCACHE_0 AR_SVD_OFFSET(CVCACHE) 2541250003Sadrian#define AR_CVCACHE(_idx) (AR_CVCACHE_0+(_idx)) 2542250003Sadrian/* for CV CACHE Header */ 2543250003Sadrian#define AR_CVCACHE_Ng_IDX 0x0000C000 2544250003Sadrian#define AR_CVCACHE_Ng_IDX_S 14 2545250003Sadrian#define AR_CVCACHE_BW40 0x00010000 2546250003Sadrian#define AR_CVCACHE_BW40_S 16 2547250003Sadrian#define AR_CVCACHE_IMPLICIT 0x00020000 2548250003Sadrian#define AR_CVCACHE_IMPLICIT_S 17 2549250003Sadrian#define AR_CVCACHE_DEST_IDX 0x01FC0000 2550250003Sadrian#define AR_CVCACHE_DEST_IDX_S 18 2551250003Sadrian#define AR_CVCACHE_Nc_IDX 0x06000000 2552250003Sadrian#define AR_CVCACHE_Nc_IDX_S 25 2553250003Sadrian#define AR_CVCACHE_Nr_IDX 0x18000000 2554250003Sadrian#define AR_CVCACHE_Nr_IDX_S 27 2555250003Sadrian#define AR_CVCACHE_EXPIRED 0x20000000 2556250003Sadrian#define AR_CVCACHE_EXPIRED_S 29 2557250003Sadrian#define AR_CVCACHE_WRITE 0x80000000 2558250003Sadrian/* for CV cache data*/ 2559250003Sadrian#define AR_CVCACHE_RD_EN 0x40000000 2560250003Sadrian#define AR_CVCACHE_DATA 0x3fffffff 2561250003Sadrian/* 2562250003Sadrian * ANT DIV setting 2563250003Sadrian */ 2564250003Sadrian#define ANT_DIV_CONTROL_ALL (0x7e000000) 2565250003Sadrian#define ANT_DIV_CONTROL_ALL_S (25) 2566250003Sadrian#define ANT_DIV_ENABLE (0x1000000) 2567250003Sadrian#define ANT_DIV_ENABLE_S (24) 2568250003Sadrian#define FAST_DIV_ENABLE (0x2000) 2569250003Sadrian#define FAST_DIV_ENABLE_S (13) 2570250003Sadrian 2571250003Sadrian/* Global register */ 2572250003Sadrian#define AR_GLB_REG_OFFSET(_x) offsetof(struct wlan_bt_glb_reg_pcie, _x) 2573250003Sadrian 2574250003Sadrian#define AR_MBOX_CTRL_STATUS AR_GLB_REG_OFFSET(GLB_MBOX_CONTROL_STATUS) 2575250003Sadrian#define AR_MBOX_INT_EMB_CPU 0x0001 2576250003Sadrian#define AR_MBOX_INT_WLAN 0x0002 2577250003Sadrian#define AR_MBOX_RESET 0x0004 2578250003Sadrian#define AR_MBOX_RAM_REQ_MASK 0x0018 2579250003Sadrian#define AR_MBOX_RAM_REQ_NO_RAM 0x0000 2580250003Sadrian#define AR_MBOX_RAM_REQ_USB 0x0008 2581250003Sadrian#define AR_MBOX_RAM_REQ_WLAN_BUF 0x0010 2582250003Sadrian#define AR_MBOX_RAM_REQ_PATCH_REAPPY 0x0018 2583250003Sadrian#define AR_MBOX_RAM_CONF 0x0020 2584250003Sadrian#define AR_MBOX_WLAN_BUF 0x0040 2585250003Sadrian#define AR_MBOX_WOW_REQ 0x0080 2586250003Sadrian#define AR_MBOX_WOW_CONF 0x0100 2587250003Sadrian#define AR_MBOX_WOW_ERROR_MASK 0x1e00 2588250003Sadrian#define AR_MBOX_WOW_ERROR_NONE 0x0000 2589250003Sadrian#define AR_MBOX_WOW_ERROR_INVALID_MSG 0x0200 2590250003Sadrian#define AR_MBOX_WOW_ERROR_MALFORMED_MSG 0x0400 2591250003Sadrian#define AR_MBOX_WOW_ERROR_INVALID_RAM_IMAGE 0x0600 2592250003Sadrian 2593250003Sadrian#define AR_WLAN_WOW_STATUS AR_GLB_REG_OFFSET(GLB_WLAN_WOW_STATUS) 2594250003Sadrian 2595250003Sadrian#define AR_WLAN_WOW_ENABLE AR_GLB_REG_OFFSET(GLB_WLAN_WOW_ENABLE) 2596250003Sadrian 2597250003Sadrian#define AR_EMB_CPU_WOW_STATUS AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_STATUS) 2598250003Sadrian#define AR_EMB_CPU_WOW_STATUS_KEEP_ALIVE_FAIL 0x1 2599250003Sadrian#define AR_EMB_CPU_WOW_STATUS_BEACON_MISS 0x2 2600250003Sadrian#define AR_EMB_CPU_WOW_STATUS_PATTERN_MATCH 0x4 2601250003Sadrian#define AR_EMB_CPU_WOW_STATUS_MAGIC_PATTERN 0x8 2602250003Sadrian 2603250003Sadrian#define AR_EMB_CPU_WOW_ENABLE AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_ENABLE) 2604250003Sadrian#define AR_EMB_CPU_WOW_ENABLE_KEEP_ALIVE_FAIL 0x1 2605250003Sadrian#define AR_EMB_CPU_WOW_ENABLE_BEACON_MISS 0x2 2606250003Sadrian#define AR_EMB_CPU_WOW_ENABLE_PATTERN_MATCH 0x4 2607250003Sadrian#define AR_EMB_CPU_WOW_ENABLE_MAGIC_PATTERN 0x8 2608250003Sadrian 2609250003Sadrian#define AR_SW_WOW_CONTROL AR_GLB_REG_OFFSET(GLB_SW_WOW_CONTROL) 2610250003Sadrian#define AR_SW_WOW_ENABLE 0x1 2611250003Sadrian#define AR_SWITCH_TO_REFCLK 0x2 2612250003Sadrian#define AR_RESET_CONTROL 0x4 2613250003Sadrian#define AR_RESET_VALUE_MASK 0x8 2614250003Sadrian#define AR_HW_WOW_DISABLE 0x10 2615250003Sadrian#define AR_CLR_MAC_INTERRUPT 0x20 2616250003Sadrian#define AR_CLR_KA_INTERRUPT 0x40 2617250003Sadrian 2618250003Sadrian/* 2619250003Sadrian * WLAN coex registers 2620250003Sadrian */ 2621250003Sadrian#define AR_WLAN_COEX_OFFSET(_x) offsetof(struct wlan_coex_reg, _x) 2622250003Sadrian 2623250003Sadrian#define AR_MCI_COMMAND0 AR_WLAN_COEX_OFFSET(MCI_COMMAND0) 2624250003Sadrian#define AR_MCI_COMMAND0_HEADER 0xFF 2625250003Sadrian#define AR_MCI_COMMAND0_HEADER_S 0 2626250003Sadrian#define AR_MCI_COMMAND0_LEN 0x1f00 2627250003Sadrian#define AR_MCI_COMMAND0_LEN_S 8 2628250003Sadrian#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000 2629250003Sadrian#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13 2630250003Sadrian 2631250003Sadrian#define AR_MCI_COMMAND1 AR_WLAN_COEX_OFFSET(MCI_COMMAND1) 2632250003Sadrian 2633250003Sadrian#define AR_MCI_COMMAND2 AR_WLAN_COEX_OFFSET(MCI_COMMAND2) 2634250003Sadrian#define AR_MCI_COMMAND2_RESET_TX 0x01 2635250003Sadrian#define AR_MCI_COMMAND2_RESET_TX_S 0 2636250003Sadrian#define AR_MCI_COMMAND2_RESET_RX 0x02 2637250003Sadrian#define AR_MCI_COMMAND2_RESET_RX_S 1 2638250003Sadrian#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC 2639250003Sadrian#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2 2640250003Sadrian#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400 2641250003Sadrian#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10 2642250003Sadrian 2643250003Sadrian#define AR_MCI_RX_CTRL AR_WLAN_COEX_OFFSET(MCI_RX_CTRL) 2644250003Sadrian 2645250003Sadrian#define AR_MCI_TX_CTRL AR_WLAN_COEX_OFFSET(MCI_TX_CTRL) 2646250003Sadrian/* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */ 2647250003Sadrian#define AR_MCI_TX_CTRL_CLK_DIV 0x03 2648250003Sadrian#define AR_MCI_TX_CTRL_CLK_DIV_S 0 2649250003Sadrian#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04 2650250003Sadrian#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2 2651250003Sadrian#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8 2652250003Sadrian#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3 2653250003Sadrian#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000 2654250003Sadrian#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24 2655250003Sadrian 2656250003Sadrian#define AR_MCI_MSG_ATTRIBUTES_TABLE AR_WLAN_COEX_OFFSET(MCI_MSG_ATTRIBUTES_TABLE) 2657250003Sadrian#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF 2658250003Sadrian#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0 2659250003Sadrian#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000 2660250003Sadrian#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16 2661250003Sadrian 2662250003Sadrian#define AR_MCI_SCHD_TABLE_0 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_0) 2663250003Sadrian#define AR_MCI_SCHD_TABLE_1 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_1) 2664250003Sadrian#define AR_MCI_GPM_0 AR_WLAN_COEX_OFFSET(MCI_GPM_0) 2665250003Sadrian#define AR_MCI_GPM_1 AR_WLAN_COEX_OFFSET(MCI_GPM_1) 2666250003Sadrian#define AR_MCI_GPM_WRITE_PTR 0xFFFF0000 2667250003Sadrian#define AR_MCI_GPM_WRITE_PTR_S 16 2668250003Sadrian#define AR_MCI_GPM_BUF_LEN 0x0000FFFF 2669250003Sadrian#define AR_MCI_GPM_BUF_LEN_S 0 2670250003Sadrian 2671250003Sadrian#define AR_MCI_INTERRUPT_RAW AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RAW) 2672250003Sadrian#define AR_MCI_INTERRUPT_EN AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_EN) 2673250003Sadrian#define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 2674250003Sadrian#define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0 2675250003Sadrian#define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 2676250003Sadrian#define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1 2677250003Sadrian#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004 2678250003Sadrian#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2 2679250003Sadrian#define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 2680250003Sadrian#define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3 2681250003Sadrian#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 2682250003Sadrian#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4 2683250003Sadrian#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 2684250003Sadrian#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5 2685250003Sadrian#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 2686250003Sadrian#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7 2687250003Sadrian#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 2688250003Sadrian#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8 2689250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG 0x00000200 2690250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_S 9 2691250003Sadrian#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 2692250003Sadrian#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10 2693250003Sadrian#define AR_MCI_INTERRUPT_BT_PRI 0x07fff800 2694250003Sadrian#define AR_MCI_INTERRUPT_BT_PRI_S 11 2695250003Sadrian#define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000 2696250003Sadrian#define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27 2697250003Sadrian#define AR_MCI_INTERRUPT_BT_FREQ 0x10000000 2698250003Sadrian#define AR_MCI_INTERRUPT_BT_FREQ_S 28 2699250003Sadrian#define AR_MCI_INTERRUPT_BT_STOMP 0x20000000 2700250003Sadrian#define AR_MCI_INTERRUPT_BT_STOMP_S 29 2701250003Sadrian#define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000 2702250003Sadrian#define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30 2703250003Sadrian#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 2704250003Sadrian#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31 2705250003Sadrian 2706250003Sadrian#define AR_MCI_INTERRUPT_MSG_FAIL_MASK ( AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 2707250003Sadrian AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 2708250003Sadrian AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 2709250003Sadrian AR_MCI_INTERRUPT_TX_SW_MSG_FAIL ) 2710250003Sadrian 2711250003Sadrian#define AR_MCI_INTERRUPT_DEFAULT ( AR_MCI_INTERRUPT_SW_MSG_DONE | \ 2712250003Sadrian AR_MCI_INTERRUPT_RX_INVALID_HDR | \ 2713250003Sadrian AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 2714250003Sadrian AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 2715250003Sadrian AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 2716250003Sadrian AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \ 2717250003Sadrian AR_MCI_INTERRUPT_RX_MSG | \ 2718250003Sadrian AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \ 2719250003Sadrian AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT ) 2720250003Sadrian 2721250003Sadrian#define AR_MCI_REMOTE_CPU_INT AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT) 2722250003Sadrian#define AR_MCI_REMOTE_CPU_INT_EN AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT_EN) 2723250003Sadrian 2724250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_RAW AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_RAW) 2725250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_EN AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_EN) 2726250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 2727250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 2728250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 2729250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 2730250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 2731250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 2732250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 2733250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 2734250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 2735250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 2736250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 2737250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 2738250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 2739250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 2740250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 2741250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 2742250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 2743250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 2744250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 2745250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 2746250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 2747250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 2748250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 2749250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 2750250003Sadrian#ifdef AH_DEBUG 2751250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_DEFAULT ( AR_MCI_INTERRUPT_RX_MSG_GPM | \ 2752250003Sadrian AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ 2753250003Sadrian AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ 2754250003Sadrian AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ 2755250003Sadrian AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ 2756250003Sadrian AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ 2757250003Sadrian AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 2758250003Sadrian AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 2759250003Sadrian AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 2760250003Sadrian AR_MCI_INTERRUPT_RX_MSG_CONT_RST | \ 2761250003Sadrian AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE ) 2762250003Sadrian#else 2763250003Sadrian#define AR_MCI_INTERRUPT_RX_MSG_DEFAULT ( AR_MCI_INTERRUPT_RX_MSG_GPM | \ 2764250003Sadrian AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ 2765250003Sadrian AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ 2766250003Sadrian AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ 2767250003Sadrian AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE ) 2768250003Sadrian#endif 2769250003Sadrian#define AR_MCI_INTERRUPT_RX_HW_MSG_MASK ( AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ 2770250003Sadrian AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ 2771250003Sadrian AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 2772250003Sadrian AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 2773250003Sadrian AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 2774250003Sadrian AR_MCI_INTERRUPT_RX_MSG_CONT_RST ) 2775250003Sadrian 2776250003Sadrian#define AR_MCI_CPU_INT AR_WLAN_COEX_OFFSET(MCI_CPU_INT) 2777250003Sadrian 2778250003Sadrian#define AR_MCI_RX_STATUS AR_WLAN_COEX_OFFSET(MCI_RX_STATUS) 2779250003Sadrian#define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00 2780250003Sadrian#define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8 2781250003Sadrian#define AR_MCI_RX_REMOTE_SLEEP 0x00001000 2782250003Sadrian#define AR_MCI_RX_REMOTE_SLEEP_S 12 2783250003Sadrian#define AR_MCI_RX_MCI_CLK_REQ 0x00002000 2784250003Sadrian#define AR_MCI_RX_MCI_CLK_REQ_S 13 2785250003Sadrian 2786250003Sadrian#define AR_MCI_CONT_STATUS AR_WLAN_COEX_OFFSET(MCI_CONT_STATUS) 2787250003Sadrian#define AR_MCI_CONT_RSSI_POWER 0x000000FF 2788250003Sadrian#define AR_MCI_CONT_RSSI_POWER_S 0 2789250003Sadrian#define AR_MCI_CONT_RRIORITY 0x0000FF00 2790250003Sadrian#define AR_MCI_CONT_RRIORITY_S 8 2791250003Sadrian#define AR_MCI_CONT_TXRX 0x00010000 2792250003Sadrian#define AR_MCI_CONT_TXRX_S 16 2793250003Sadrian 2794250003Sadrian#define AR_MCI_BT_PRI0 AR_WLAN_COEX_OFFSET(MCI_BT_PRI0) 2795250003Sadrian#define AR_MCI_BT_PRI1 AR_WLAN_COEX_OFFSET(MCI_BT_PRI1) 2796250003Sadrian#define AR_MCI_BT_PRI2 AR_WLAN_COEX_OFFSET(MCI_BT_PRI2) 2797250003Sadrian#define AR_MCI_BT_PRI3 AR_WLAN_COEX_OFFSET(MCI_BT_PRI3) 2798250003Sadrian#define AR_MCI_BT_PRI AR_WLAN_COEX_OFFSET(MCI_BT_PRI) 2799250003Sadrian#define AR_MCI_WL_FREQ0 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ0) 2800250003Sadrian#define AR_MCI_WL_FREQ1 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ1) 2801250003Sadrian#define AR_MCI_WL_FREQ2 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ2) 2802250003Sadrian#define AR_MCI_GAIN AR_WLAN_COEX_OFFSET(MCI_GAIN) 2803250003Sadrian#define AR_MCI_WBTIMER1 AR_WLAN_COEX_OFFSET(MCI_WBTIMER1) 2804250003Sadrian#define AR_MCI_WBTIMER2 AR_WLAN_COEX_OFFSET(MCI_WBTIMER2) 2805250003Sadrian#define AR_MCI_WBTIMER3 AR_WLAN_COEX_OFFSET(MCI_WBTIMER3) 2806250003Sadrian#define AR_MCI_WBTIMER4 AR_WLAN_COEX_OFFSET(MCI_WBTIMER4) 2807250003Sadrian#define AR_MCI_MAXGAIN AR_WLAN_COEX_OFFSET(MCI_MAXGAIN) 2808250003Sadrian#define AR_MCI_HW_SCHD_TBL_CTL AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_CTL) 2809250003Sadrian#define AR_MCI_HW_SCHD_TBL_D0 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D0) 2810250003Sadrian#define AR_MCI_HW_SCHD_TBL_D1 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D1) 2811250003Sadrian#define AR_MCI_HW_SCHD_TBL_D2 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D2) 2812250003Sadrian#define AR_MCI_HW_SCHD_TBL_D3 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D3) 2813250003Sadrian#define AR_MCI_TX_PAYLOAD0 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD0) 2814250003Sadrian#define AR_MCI_TX_PAYLOAD1 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD1) 2815250003Sadrian#define AR_MCI_TX_PAYLOAD2 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD2) 2816250003Sadrian#define AR_MCI_TX_PAYLOAD3 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD3) 2817250003Sadrian#define AR_BTCOEX_WBTIMER AR_WLAN_COEX_OFFSET(BTCOEX_WBTIMER) 2818250003Sadrian 2819250003Sadrian#define AR_BTCOEX_CTRL AR_WLAN_COEX_OFFSET(BTCOEX_CTRL) 2820250003Sadrian#define AR_BTCOEX_CTRL_JUPITER_MODE 0x00000001 2821250003Sadrian#define AR_BTCOEX_CTRL_JUPITER_MODE_S 0 2822250003Sadrian#define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002 2823250003Sadrian#define AR_BTCOEX_CTRL_WBTIMER_EN_S 1 2824250003Sadrian#define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004 2825250003Sadrian#define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2 2826250003Sadrian#define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008 2827250003Sadrian#define AR_BTCOEX_CTRL_LNA_SHARED_S 3 2828250003Sadrian#define AR_BTCOEX_CTRL_PA_SHARED 0x00000010 2829250003Sadrian#define AR_BTCOEX_CTRL_PA_SHARED_S 4 2830250003Sadrian#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020 2831250003Sadrian#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5 2832250003Sadrian#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040 2833250003Sadrian#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6 2834250003Sadrian#define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180 2835250003Sadrian#define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7 2836250003Sadrian#define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00 2837250003Sadrian#define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9 2838250003Sadrian#define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000 2839250003Sadrian#define AR_BTCOEX_CTRL_AGGR_THRESH_S 12 2840250003Sadrian#define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000 2841250003Sadrian#define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19 2842250003Sadrian#define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000 2843250003Sadrian#define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20 2844250003Sadrian#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000 2845250003Sadrian#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28 2846250003Sadrian#define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000 2847250003Sadrian#define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29 2848250003Sadrian#define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000 2849250003Sadrian#define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30 2850250003Sadrian#define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 2851250003Sadrian#define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 2852250003Sadrian 2853250003Sadrian#define AR_BTCOEX_WL_WEIGHTS0 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS0) 2854250003Sadrian#define AR_BTCOEX_WL_WEIGHTS1 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS1) 2855250003Sadrian#define AR_BTCOEX_WL_WEIGHTS2 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS2) 2856250003Sadrian#define AR_BTCOEX_WL_WEIGHTS3 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS3) 2857250003Sadrian#define AR_BTCOEX_MAX_TXPWR(_x) (AR_WLAN_COEX_OFFSET(BTCOEX_MAX_TXPWR) + ((_x) << 2)) 2858250003Sadrian#define AR_BTCOEX_WL_LNA AR_WLAN_COEX_OFFSET(BTCOEX_WL_LNA) 2859301016Sadrian#define AR_BTCOEX_WL_LNA_TIMEOUT 0x003FFFFF 2860301016Sadrian#define AR_BTCOEX_WL_LNA_TIMEOUT_S 0 2861301016Sadrian 2862250003Sadrian#define AR_BTCOEX_RFGAIN_CTRL AR_WLAN_COEX_OFFSET(BTCOEX_RFGAIN_CTRL) 2863250003Sadrian 2864250003Sadrian#define AR_BTCOEX_CTRL2 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL2) 2865250003Sadrian#define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800 2866250003Sadrian#define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11 2867250003Sadrian#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000 2868250003Sadrian#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19 2869250003Sadrian#define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000 2870250003Sadrian#define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22 2871250003Sadrian#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000 2872250003Sadrian#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23 2873250003Sadrian#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000 2874250003Sadrian#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24 2875250003Sadrian#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000 2876250003Sadrian#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25 2877250003Sadrian 2878250003Sadrian#define AR_BTCOEX_RC AR_WLAN_COEX_OFFSET(BTCOEX_RC) 2879250003Sadrian#define AR_BTCOEX_MAX_RFGAIN(_x) AR_WLAN_COEX_OFFSET(BTCOEX_MAX_RFGAIN[_x]) 2880250003Sadrian#define AR_BTCOEX_DBG AR_WLAN_COEX_OFFSET(BTCOEX_DBG) 2881250003Sadrian#define AR_MCI_LAST_HW_MSG_HDR AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_HDR) 2882250003Sadrian#define AR_MCI_LAST_HW_MSG_BDY AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_BDY) 2883250003Sadrian 2884250003Sadrian#define AR_MCI_SCHD_TABLE_2 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_2) 2885250003Sadrian#define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001 2886250003Sadrian#define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0 2887250003Sadrian#define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002 2888250003Sadrian#define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1 2889250003Sadrian 2890250003Sadrian#define AR_BTCOEX_CTRL3 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL3) 2891250003Sadrian#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000FFF 2892250003Sadrian#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 2893250003Sadrian 2894301016Sadrian/* QCA9565 */ 2895301016Sadrian 2896301016Sadrian#define AR_BTCOEX_WL_LNADIV 0x1a64 2897301016Sadrian#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD 0x00003FFF 2898301016Sadrian#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S 0 2899301016Sadrian#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY 0x00004000 2900301016Sadrian#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY_S 14 2901301016Sadrian#define AR_BTCOEX_WL_LNADIV_FORCE_ON 0x00008000 2902301016Sadrian#define AR_BTCOEX_WL_LNADIV_FORCE_ON_S 15 2903301016Sadrian#define AR_BTCOEX_WL_LNADIV_MODE_OPTION 0x00030000 2904301016Sadrian#define AR_BTCOEX_WL_LNADIV_MODE_OPTION_S 16 2905301016Sadrian#define AR_BTCOEX_WL_LNADIV_MODE 0x007c0000 2906301016Sadrian#define AR_BTCOEX_WL_LNADIV_MODE_S 18 2907301016Sadrian#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ 0x00800000 2908301016Sadrian#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ_S 23 2909301016Sadrian#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE 0x01000000 2910301016Sadrian#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE_S 24 2911301016Sadrian#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT 0x02000000 2912301016Sadrian#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT_S 25 2913301016Sadrian#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD 0xFC000000 2914301016Sadrian#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD_S 26 2915301016Sadrian 2916301016Sadrian#define AR_MCI_MISC 0x1a74 2917301016Sadrian#define AR_MCI_MISC_HW_FIX_EN 0x00000001 2918301016Sadrian#define AR_MCI_MISC_HW_FIX_EN_S 0 2919301016Sadrian 2920250003Sadrian/****************************************************************************** 2921250003Sadrian * WLAN BT Global Register Map 2922250003Sadrian******************************************************************************/ 2923250003Sadrian#define AR_WLAN_BT_GLB_OFFSET(_x) offsetof(struct wlan_bt_glb_reg_pcie, _x) 2924250003Sadrian 2925250003Sadrian/* 2926250003Sadrian * WLAN BT Global Registers 2927250003Sadrian */ 2928250003Sadrian 2929250003Sadrian#define AR_GLB_GPIO_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_GPIO_CONTROL) 2930250003Sadrian#define AR_GLB_WLAN_WOW_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_STATUS) 2931250003Sadrian#define AR_GLB_WLAN_WOW_ENABLE AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_ENABLE) 2932250003Sadrian#define AR_GLB_EMB_CPU_WOW_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_STATUS) 2933250003Sadrian#define AR_GLB_EMB_CPU_WOW_ENABLE AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_ENABLE) 2934250003Sadrian#define AR_GLB_MBOX_CONTROL_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_MBOX_CONTROL_STATUS) 2935250003Sadrian#define AR_GLB_SW_WOW_CLK_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_SW_WOW_CLK_CONTROL) 2936250003Sadrian#define AR_GLB_APB_TIMEOUT AR_WLAN_BT_GLB_OFFSET(GLB_APB_TIMEOUT) 2937250003Sadrian#define AR_GLB_OTP_LDO_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_CONTROL) 2938250003Sadrian#define AR_GLB_OTP_LDO_POWER_GOOD AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_POWER_GOOD) 2939250003Sadrian#define AR_GLB_OTP_LDO_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_STATUS) 2940250003Sadrian#define AR_GLB_SWREG_DISCONT_MODE AR_WLAN_BT_GLB_OFFSET(GLB_SWREG_DISCONT_MODE) 2941250003Sadrian#define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL0 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL0) 2942250003Sadrian#define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL1 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL1) 2943250003Sadrian#define AR_GLB_BT_GPIO_REMAP_IN_CONTROL0 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL0) 2944250003Sadrian#define AR_GLB_BT_GPIO_REMAP_IN_CONTROL1 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL1) 2945250003Sadrian#define AR_GLB_BT_GPIO_REMAP_IN_CONTROL2 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL2) 2946250003Sadrian#define AR_GLB_SCRATCH(_ah) \ 2947250003Sadrian (AR_SREV_APHRODITE(_ah)? \ 2948250003Sadrian AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Aphrodite_10.GLB_SCRATCH) : \ 2949250003Sadrian (AR_SREV_JUPITER_20(_ah) ? \ 2950250003Sadrian AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_SCRATCH) : \ 2951250003Sadrian AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_10.GLB_SCRATCH))) 2952250003Sadrian 2953250003Sadrian#define AR_GLB_CONTROL AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_CONTROL) 2954250003Sadrian#define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001 2955250003Sadrian#define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0 2956250003Sadrian#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002 2957250003Sadrian#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1 2958250003Sadrian#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004 2959250003Sadrian#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2 2960250003Sadrian#define AR_GLB_WLAN_UART_INTF_EN 0x00020000 2961250003Sadrian#define AR_GLB_WLAN_UART_INTF_EN_S 17 2962250003Sadrian#define AR_GLB_DS_JTAG_DISABLE 0x00040000 2963250003Sadrian#define AR_GLB_DS_JTAG_DISABLE_S 18 2964250003Sadrian 2965250003Sadrian#define AR_GLB_STATUS AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_STATUS) 2966250003Sadrian 2967250003Sadrian/* 2968250003Sadrian * MAC Version and Revision 2969250003Sadrian */ 2970250003Sadrian 2971250003Sadrian#define AR_SREV_VERSION_OSPREY 0x1C0 2972250003Sadrian#define AR_SREV_VERSION_AR9580 0x1C0 2973250003Sadrian#define AR_SREV_VERSION_JUPITER 0x280 2974250003Sadrian#define AR_SREV_VERSION_HORNET 0x200 2975250003Sadrian#define AR_SREV_VERSION_WASP 0x300 /* XXX: Check Wasp version number */ 2976250003Sadrian#define AR_SREV_VERSION_SCORPION 0x400 2977250003Sadrian#define AR_SREV_VERSION_POSEIDON 0x240 2978291437Sadrian#define AR_SREV_VERSION_HONEYBEE 0x500 2979250003Sadrian#define AR_SREV_VERSION_APHRODITE 0x2C0 2980250003Sadrian 2981250003Sadrian#define AR_SREV_REVISION_OSPREY_10 0 /* Osprey 1.0 */ 2982250003Sadrian#define AR_SREV_REVISION_OSPREY_20 2 /* Osprey 2.0/2.1 */ 2983250003Sadrian#define AR_SREV_REVISION_OSPREY_22 3 /* Osprey 2.2 */ 2984250003Sadrian#define AR_SREV_REVISION_AR9580_10 4 /* AR9580/Peacock 1.0 */ 2985250003Sadrian 2986250003Sadrian#define AR_SREV_REVISION_HORNET_10 0 /* Hornet 1.0 */ 2987250003Sadrian#define AR_SREV_REVISION_HORNET_11 1 /* Hornet 1.1 */ 2988250003Sadrian#define AR_SREV_REVISION_HORNET_12 2 /* Hornet 1.2 */ 2989250003Sadrian#define AR_SREV_REVISION_HORNET_11_MASK 0xf /* Hornet 1.1 revision mask */ 2990250003Sadrian 2991250003Sadrian#define AR_SREV_REVISION_POSEIDON_10 0 /* Poseidon 1.0 */ 2992250003Sadrian#define AR_SREV_REVISION_POSEIDON_11 1 /* Poseidon 1.1 */ 2993250003Sadrian 2994250003Sadrian#define AR_SREV_REVISION_WASP_10 0 /* Wasp 1.0 */ 2995250003Sadrian#define AR_SREV_REVISION_WASP_11 1 /* Wasp 1.1 */ 2996250003Sadrian#define AR_SREV_REVISION_WASP_12 2 /* Wasp 1.2 */ 2997250003Sadrian#define AR_SREV_REVISION_WASP_13 3 /* Wasp 1.3 */ 2998250003Sadrian#define AR_SREV_REVISION_WASP_MASK 0xf /* Wasp revision mask */ 2999250003Sadrian#define AR_SREV_REVISION_WASP_MINOR_MINOR_MASK 0x10000 /* Wasp minor minor revision mask */ 3000250003Sadrian#define AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT 16 /* Wasp minor minor revision shift */ 3001250003Sadrian 3002250003Sadrian#define AR_SREV_REVISION_JUPITER_10 0 /* Jupiter 1.0 */ 3003250003Sadrian#define AR_SREV_REVISION_JUPITER_20 2 /* Jupiter 2.0 */ 3004291433Sadrian#define AR_SREV_REVISION_JUPITER_21 3 /* Jupiter 2.1 */ 3005250003Sadrian 3006291437Sadrian#define AR_SREV_REVISION_HONEYBEE_10 0 /* Honeybee 1.0 */ 3007291437Sadrian#define AR_SREV_REVISION_HONEYBEE_11 1 /* Honeybee 1.1 */ 3008291437Sadrian#define AR_SREV_REVISION_HONEYBEE_MASK 0xf /* Honeybee revision mask */ 3009291437Sadrian 3010250003Sadrian#define AR_SREV_REVISION_APHRODITE_10 0 /* Aphrodite 1.0 */ 3011250003Sadrian 3012250003Sadrian#if defined(AH_SUPPORT_OSPREY) 3013250003Sadrian#define AR_SREV_OSPREY(_ah) \ 3014250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY)) 3015250003Sadrian 3016250003Sadrian#define AR_SREV_OSPREY_22(_ah) \ 3017250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && \ 3018250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OSPREY_22)) 3019250003Sadrian#else 3020250003Sadrian#define AR_SREV_OSPREY(_ah) 0 3021250003Sadrian#define AR_SREV_OSPREY_10(_ah) 0 3022250003Sadrian#define AR_SREV_OSPREY_20(_ah) 0 3023250003Sadrian#define AR_SREV_OSPREY_22(_ah) 0 3024250003Sadrian#define AR_SREV_OSPREY_20_OR_LATER(_ah) 0 3025250003Sadrian#define AR_SREV_OSPREY_22_OR_LATER(_ah) 0 3026250003Sadrian#endif /* #if defined(AH_SUPPORT_OSPREY) */ 3027250003Sadrian 3028250003Sadrian#define AR_SREV_AR9580(_ah) \ 3029250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \ 3030250003Sadrian (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_AR9580_10)) 3031250003Sadrian 3032250003Sadrian#define AR_SREV_AR9580_10(_ah) \ 3033250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \ 3034250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_AR9580_10)) 3035250003Sadrian 3036250003Sadrian/* NOTE: When adding chips newer than Peacock, add chip check here. */ 3037250003Sadrian#define AR_SREV_AR9580_10_OR_LATER(_ah) \ 3038291437Sadrian (AR_SREV_AR9580(_ah) || AR_SREV_SCORPION(_ah) || AR_SREV_HONEYBEE(_ah)) 3039250003Sadrian 3040250003Sadrian#define AR_SREV_JUPITER(_ah) \ 3041250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER)) 3042250003Sadrian 3043250003Sadrian#define AR_SREV_JUPITER_10(_ah) \ 3044250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3045250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_10)) 3046250003Sadrian 3047250003Sadrian#define AR_SREV_JUPITER_20(_ah) \ 3048250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3049250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_20)) 3050250003Sadrian 3051291433Sadrian#define AR_SREV_JUPITER_21(_ah) \ 3052291433Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3053291433Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_21)) 3054291433Sadrian 3055250003Sadrian#define AR_SREV_JUPITER_20_OR_LATER(_ah) \ 3056250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3057250003Sadrian (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_JUPITER_20)) 3058250003Sadrian 3059291433Sadrian#define AR_SREV_JUPITER_21_OR_LATER(_ah) \ 3060291433Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3061291433Sadrian (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_JUPITER_21)) 3062291433Sadrian 3063250003Sadrian#define AR_SREV_APHRODITE(_ah) \ 3064250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE)) 3065250003Sadrian 3066250003Sadrian#define AR_SREV_APHRODITE_10(_ah) \ 3067250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE) && \ 3068250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_APHRODITE_10)) 3069250003Sadrian 3070250003Sadrian#if defined(AH_SUPPORT_HORNET) 3071250003Sadrian#define AR_SREV_HORNET_10(_ah) \ 3072250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ 3073250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_10)) 3074250003Sadrian 3075250003Sadrian#define AR_SREV_HORNET_11(_ah) \ 3076250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ 3077250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_11)) 3078250003Sadrian 3079250003Sadrian#define AR_SREV_HORNET_12(_ah) \ 3080250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ 3081250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_12)) 3082250003Sadrian 3083250003Sadrian#define AR_SREV_HORNET(_ah) \ 3084250003Sadrian ( AR_SREV_HORNET_10(_ah) || AR_SREV_HORNET_11(_ah) || AR_SREV_HORNET_12(_ah) ) 3085250003Sadrian#else 3086250003Sadrian#define AR_SREV_HORNET_10(_ah) 0 3087250003Sadrian#define AR_SREV_HORNET_11(_ah) 0 3088250003Sadrian#define AR_SREV_HORNET_12(_ah) 0 3089250003Sadrian#define AR_SREV_HORNET(_ah) 0 3090250003Sadrian#endif /* #if defined(AH_SUPPORT_HORNET) */ 3091250003Sadrian 3092250003Sadrian#if defined(AH_SUPPORT_WASP) 3093250003Sadrian#define AR_SREV_WASP(_ah) \ 3094250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP)) 3095250003Sadrian#else 3096250003Sadrian#define AR_SREV_WASP(_ah) 0 3097250003Sadrian#endif /* #if defined(AH_SUPPORT_WASP) */ 3098250003Sadrian 3099291437Sadrian#if defined(AH_SUPPORT_HONEYBEE) 3100291437Sadrian#define AR_SREV_HONEYBEE(_ah) \ 3101291437Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE)) 3102291437Sadrian#define AR_SREV_HONEYBEE_10(_ah) \ 3103291437Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE) && \ 3104291437Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HONEYBEE_10)) 3105291437Sadrian#define AR_SREV_HONEYBEE_11(_ah) \ 3106291437Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE) && \ 3107291437Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HONEYBEE_11)) 3108291437Sadrian#else 3109291437Sadrian#define AR_SREV_HONEYBEE(_ah) 0 3110291437Sadrian#define AR_SREV_HONEYBEE_10(_ah) 0 3111291437Sadrian#define AR_SREV_HONEYBEE_11(_ah) 0 3112291437Sadrian#endif /* #if defined(AH_SUPPORT_HONEYBEE) */ 3113291437Sadrian 3114250003Sadrian#define AR_SREV_WASP_10(_ah) \ 3115250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ 3116250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_10)) 3117250003Sadrian 3118250003Sadrian#define AR_SREV_WASP_11(_ah) \ 3119250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ 3120250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_11)) 3121250003Sadrian 3122250003Sadrian#define AR_SREV_WASP_12(_ah) \ 3123250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ 3124250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_12)) 3125250003Sadrian 3126250003Sadrian#if defined(AH_SUPPORT_SCORPION) 3127250003Sadrian#define AR_SREV_SCORPION(_ah) \ 3128250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SCORPION)) 3129250003Sadrian#else 3130250003Sadrian#define AR_SREV_SCORPION(_ah) 0 3131250003Sadrian#endif /* #if defined(AH_SUPPORT_SCORPION) */ 3132250003Sadrian 3133250003Sadrian#if defined(AH_SUPPORT_POSEIDON) 3134250003Sadrian#define AR_SREV_POSEIDON(_ah) \ 3135250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON)) 3136250003Sadrian 3137250003Sadrian#define AR_SREV_POSEIDON_10(_ah) \ 3138250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ 3139250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_10)) 3140250003Sadrian 3141250003Sadrian#define AR_SREV_POSEIDON_11(_ah) \ 3142250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ 3143250003Sadrian (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_11)) 3144250003Sadrian#else 3145250003Sadrian#define AR_SREV_POSEIDON(_ah) 0 3146250003Sadrian#define AR_SREV_POSEIDON_10(_ah) 0 3147250003Sadrian#define AR_SREV_POSEIDON_11(_ah) 0 3148250003Sadrian#endif /* #if defined(AH_SUPPORT_POSEIDON) */ 3149250003Sadrian 3150250003Sadrian#define AR_SREV_POSEIDON_11_OR_LATER(_ah) \ 3151250003Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ 3152250003Sadrian (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_POSEIDON_11)) 3153250003Sadrian 3154250003Sadrian#define AR_SREV_POSEIDON_OR_LATER(_ah) \ 3155250003Sadrian (AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_POSEIDON) 3156291437Sadrian#define AR_SREV_SOC(_ah) (AR_SREV_HORNET(_ah) || AR_SREV_POSEIDON(_ah) || AR_SREV_WASP(_ah) || AR_SREV_HONEYBEE(_ah)) 3157250003Sadrian/* 3158250003Sadrian* Mask used to construct AAD for CCMP-AES 3159250003Sadrian* Cisco spec defined bits 0-3 as mask 3160250003Sadrian* IEEE802.11w defined as bit 4. 3161250003Sadrian*/ 3162250003Sadrian#define AR_MFP_QOS_MASK_IEEE 0x10 3163250003Sadrian#define AR_MFP_QOS_MASK_CISCO 0xf 3164250003Sadrian 3165250003Sadrian/* 3166250003Sadrian* frame control field mask: 3167250003Sadrian* 0 0 0 0 0 0 0 0 3168250003Sadrian* | | | | | | | | _ Order bit 3169250003Sadrian* | | | | | | | _ _ Protected Frame bit 3170250003Sadrian* | | | | | | _ _ _ More data bit 3171250003Sadrian* | | | | | _ _ _ _ Power management bit 3172250003Sadrian* | | | | _ _ _ _ _ Retry bit 3173250003Sadrian* | | | _ _ _ _ _ _ More fragments bit 3174250003Sadrian* | | _ _ _ _ _ _ _ FromDS bit 3175250003Sadrian* | _ _ _ _ _ _ _ _ ToDS bit 3176250003Sadrian*/ 3177250003Sadrian#define AR_AES_MUTE_MASK1_FC_MGMT_MFP 0xC7FF 3178250003Sadrian#endif 3179