| /freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_trampoline_AArch64.S | 26 STP Q2, Q3, [SP, #-32]!
45 LDP Q2, Q3, [SP], #32
114 STP Q2, Q3, [SP, #-32]!
135 LDP Q2, Q3, [SP], #32
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| /freebsd-11-stable/lib/msun/src/ |
| H A D | s_expm1f.c | 37 Q2 = 1.5807170421e-3; /* 0xcf3010.0p-33 */ variable
92 r1 = one+hxs*(Q1+hxs*Q2);
|
| H A D | s_expm1.c | 42 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5
44 * Q2 = 3.9682539681370365873E-4,
125 Q2 = 1.58730158725481460165e-03, /* 3F5A01A0 19FE5585 */ variable
186 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5))));
|
| /freebsd-11-stable/lib/msun/bsdsrc/ |
| H A D | b_tgamma.c | 104 #define Q2 -2.07474561943859936441469926649e-01 macro
254 q = Q0 +z*(Q1+z*(Q2+z*(Q3+z*(Q4+z*(Q5+z*(Q6+z*(Q7+z*Q8)))))));
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
|
| H A D | AArch64PBQPRegAlloc.cpp | 129 case AArch64::Q2:
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| H A D | AArch64FastISel.cpp | 3017 { AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
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| H A D | AArch64ISelLowering.cpp | 3638 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.cpp | 164 static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 77 Q0, Q1, Q2, Q3, 0
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 197 {codeview::RegisterId::ARM64_Q2, AArch64::Q2},
|
| H A D | AArch64InstPrinter.cpp | 1166 case AArch64::Q1: Reg = AArch64::Q2; break;
1167 case AArch64::Q2: Reg = AArch64::Q3; break;
|
| /freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaExprCXX.cpp | 6360 Qualifiers Q1, Q2;
6362 Composite2 = Context.getUnqualifiedArrayType(Composite2, Q2);
6369 Q2.getCVRUQualifiers());
6373 if (Q1.getAddressSpace() == Q2.getAddressSpace()) {
6376 bool MaybeQ1 = Q1.isAddressSpaceSupersetOf(Q2);
6377 bool MaybeQ2 = Q2.isAddressSpaceSupersetOf(Q1);
6381 : Q2.getAddressSpace());
6387 if (Q1.getObjCGCAttr() == Q2.getObjCGCAttr())
6393 if (Q1.getObjCLifetime() == Q2.getObjCLifetime())
6399 if (Q1 != Quals || Q2 !
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 639 Hexagon::Q2, Hexagon::Q3};
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 93 SP::Q2, SP::Q10, ~0U, ~0U,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 305 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
629 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 159 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 579 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
|
| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Demangle/ |
| H A D | ItaniumDemangle.h | 309 inline Qualifiers operator|=(Qualifiers &Q1, Qualifiers Q2) { argument
310 return Q1 = static_cast<Qualifiers>(Q1 | Q2);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1364 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1382 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 2092 .Case("v2", AArch64::Q2)
|