Searched refs:Order (Results 1 - 25 of 75) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DAllocationOrder.h1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
31 ArrayRef<MCPhysReg> Order; member in class:llvm::AllocationOrder
49 ArrayRef<MCPhysReg> getOrder() const { return Order; }
60 Limit = Order.size();
62 unsigned Reg = Order[Pos++];
79 return Order[Pos++];
H A DAllocationOrder.cpp1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37 if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
51 assert(is_contained(Order, Hints[I]) &&
H A DRegisterClassInfo.cpp98 if (!RCI.Order)
99 RCI.Order.reset(new MCPhysReg[NumRegs]);
125 RCI.Order[N++] = PhysReg;
138 RCI.Order[N++] = PhysReg;
158 dbgs() << ' ' << printReg(RCI.Order[I], TRI);
H A DRegAllocGreedy.cpp455 const AllocationOrder &Order);
458 const AllocationOrder &Order);
460 const AllocationOrder &Order,
472 unsigned getCheapestEvicteeWeight(const AllocationOrder &Order,
492 AllocationOrder &Order,
502 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
763 AllocationOrder &Order,
766 Order.rewind();
768 while ((PhysReg = Order.next()))
771 if (!PhysReg || Order
762 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, const SmallVirtRegSet &FixedRegisters) argument
1022 getCheapestEvicteeWeight(const AllocationOrder &Order, LiveInterval &VirtReg, SlotIndex Start, SlotIndex End, float *BestEvictweight) argument
1106 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs, unsigned CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) argument
1483 splitCanCauseEvictionChain(unsigned Evictee, GlobalSplitCandidate &Cand, unsigned BBNumber, const AllocationOrder &Order) argument
1543 splitCanCauseLocalSpill(unsigned VirtRegToSplit, GlobalSplitCandidate &Cand, unsigned BBNumber, const AllocationOrder &Order) argument
1583 calcGlobalSplitCost(GlobalSplitCandidate &Cand, const AllocationOrder &Order, bool *CanCauseEvictionChain) argument
1829 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
1872 calculateRegionSplitCost(LiveInterval &VirtReg, AllocationOrder &Order, BlockFrequency &BestCost, unsigned &NumCands, bool IgnoreCSR, bool *CanCauseEvictionChain) argument
2019 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
2086 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
2229 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<unsigned> &NewVRegs) argument
[all...]
H A DLocalStackSlotAllocation.cpp56 // Order reference instruction appears in program. Used to ensure
59 unsigned Order; member in class:__anon1738::FrameRef
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {}
66 return std::tie(LocalOffset, FrameIdx, Order) <
67 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order);
302 unsigned Order = 0; local
330 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++));
H A DTargetRegisterInfo.cpp212 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
213 for (unsigned i = 0; i != Order.size(); ++i)
214 R.set(Order[i]);
384 ArrayRef<MCPhysReg> Order,
419 if (!is_contained(Order, Phys))
H A DRegAllocBasic.cpp262 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
263 while (unsigned PhysReg = Order.next()) {
H A DBreakFalseDeps.cpp144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); local
145 for (MCPhysReg Reg : Order) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h51 unsigned Order; member in class:llvm::SDDbgValue
61 : Var(Var), Expr(Expr), DL(std::move(dl)), Order(O), IsIndirect(indir) {
70 : Var(Var), Expr(Expr), DL(std::move(dl)), Order(O), IsIndirect(false) {
77 bool IsIndirect, DebugLoc DL, unsigned Order,
79 : Var(Var), Expr(Expr), DL(DL), Order(Order), IsIndirect(IsIndirect) {
121 unsigned getOrder() const { return Order; }
147 unsigned Order; member in class:llvm::SDDbgLabel
151 : Label(Label), DL(std::move(dl)), Order(O) {}
161 unsigned getOrder() const { return Order; }
76 SDDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VRegOrFrameIdx, bool IsIndirect, DebugLoc DL, unsigned Order, enum DbgValueKind Kind) argument
[all...]
H A DScheduleDAGSDNodes.cpp734 DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {
746 if (!Order || DVOrder == Order) {
764 unsigned Order = N->getIROrder();
765 if (!Order || Seen.count(Order)) {
772 // If a new instruction was generated for this Order number, record it.
777 Seen.insert(Order);
778 Orders.push_back({Order, NewInsn});
783 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Support/
H A DDynamicLibrary.cpp76 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { argument
77 if (Order & SO_LoadOrder) {
91 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { argument
92 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) &&
95 if (!Process || (Order & SO_LoadedFirst)) {
96 if (void *Ptr = LibLookup(Symbol, Order))
105 if (Order & SO_LoadedLast) {
106 if (void *Ptr = LibLookup(Symbol, Order))
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h37 std::unique_ptr<MCPhysReg[]> Order; member in struct:llvm::RegisterClassInfo::RCInfo
42 return makeArrayRef(Order.get(), NumRegs);
H A DSelectionDAGNodes.h750 void setIROrder(unsigned Order) { IROrder = Order; } argument
1096 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1098 IROrder(Order), debugLoc(std::move(dl)) {
1127 SDLoc(const Instruction *I, int Order) : IROrder(Order) { argument
1128 assert(Order >= 0 && "bad IROrder");
1274 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1296 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1428 AtomicSDNode(unsigned Opc, unsigned Order, cons argument
1482 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO) argument
1514 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M) argument
1765 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, int64_t Size, int64_t Offset) argument
2102 LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L) argument
2192 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument
2226 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument
2254 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument
2286 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument
2331 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, bool IsExpanding, EVT MemVT, MachineMemOperand *MMO) argument
2360 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing, EVT MemVT, MachineMemOperand *MMO) argument
2396 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) argument
2438 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) argument
2457 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexType IndexType) argument
2481 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs) argument
[all...]
H A DScheduleDAG.h56 Order ///< Any other ordering dependency. enumerator in enum:llvm::SDep::Kind
89 /// Additional information about Order dependencies.
124 : Dep(S, Order), Contents(), Latency(0) {
165 /// Tests if this is an Order dependence between two memory accesses
169 return getKind() == Order && (Contents.OrdKind == MayAliasMem
173 /// Tests if this is an Order dependence that is marked as a barrier.
175 return getKind() == Order && Contents.OrdKind == Barrier;
183 /// Tests if this is an Order dependence that is marked as
187 return getKind() == Order && Contents.OrdKind == MustAliasMem;
195 return getKind() == Order
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp59 static void addHints(ArrayRef<MCPhysReg> Order, argument
66 for (MCPhysReg Reg : Order)
70 for (MCPhysReg Reg : Order)
78 ArrayRef<MCPhysReg> Order,
88 VirtReg, Order, Hints, MF, VRM, Matrix);
131 for (MCPhysReg OrderReg : Order)
161 addHints(Order, Hints, RC, MRI);
182 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
77 getRegAllocationHints(unsigned VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const argument
H A DSystemZRegisterInfo.h62 ArrayRef<MCPhysReg> Order,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DStructurizeCFG.cpp197 SmallVector<RegionNode *, 8> Order; member in class:__anon2763::StructurizeCFG
353 if (is_contained(Order, *I))
365 Order.push_back(*LoopI);
375 Order.push_back(*I);
382 std::reverse(Order.begin(), Order.end());
520 for (RegionNode *RN : reverse(Order)) {
726 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() :
727 Order.back()->getEntry();
757 if (!Order
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1543 X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, argument
1546 :MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1561 X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, argument
1564 : MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1579 TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, argument
1581 : X86StoreSDNode(X86ISD::VTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1591 TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, argument
1593 : X86StoreSDNode(X86ISD::VTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1603 MaskedTruncSStoreSDNode(unsigned Order, argument
1606 : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTORES, Order, d
1616 MaskedTruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1631 X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1649 X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1663 X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterBankInfo.h69 ArrayRef<PartialMappingIdx> Order);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Bitcode/Writer/
H A DValueEnumerator.cpp229 // Order is already correct.
734 SmallVector<MDIndex, 64> Order;
735 Order.reserve(MetadataMap.size());
737 Order.push_back(MetadataMap.lookup(MD));
745 llvm::sort(Order, [this](MDIndex LHS, MDIndex RHS) {
755 for (unsigned I = 0, E = Order.size(); I != E && !Order[I].F; ++I) {
756 auto *MD = Order[I].get(OldMDs);
764 if (MDs.size() == Order.size())
771 for (unsigned I = MDs.size(), E = Order
[all...]
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCGOpenMPRuntime.h471 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, argument
473 : Flags(Flags), Order(Order), Kind(Kind) {}
477 bool isValid() const { return Order != ~0u; }
478 unsigned getOrder() const { return Order; }
498 /// Order this entry was emitted.
499 unsigned Order = ~0u; variable
532 explicit OffloadEntryInfoTargetRegion(unsigned Order, argument
536 : OffloadEntryInfo(OffloadingEntryInfoTargetRegion, Order, Flags),
554 unsigned Order);
592 OffloadEntryInfoDeviceGlobalVar(unsigned Order, OMPTargetGlobalVarEntryKind Flags) argument
595 OffloadEntryInfoDeviceGlobalVar( unsigned Order, llvm::Constant *Addr, CharUnits VarSize, OMPTargetGlobalVarEntryKind Flags, llvm::GlobalValue::LinkageTypes Linkage) argument
[all...]
H A DCGAtomic.cpp516 uint64_t Size, llvm::AtomicOrdering Order,
530 FailureOrder, Size, Order, Scope);
535 FailureOrder, Size, Order, Scope);
541 Val1, Val2, FailureOrder, Size, Order, Scope);
555 FailureOrder, Size, Order, Scope);
560 FailureOrder, Size, Order, Scope);
572 Load->setAtomic(Order, Scope);
584 Store->setAtomic(Order, Scope);
671 CGF.Builder.CreateAtomicRMW(Op, Ptr.getPointer(), LoadVal1, Order, Scope);
702 uint64_t Size, llvm::AtomicOrdering Order,
513 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, Address Dest, Address Ptr, Address Val1, Address Val2, llvm::Value *IsWeak, llvm::Value *FailureOrder, uint64_t Size, llvm::AtomicOrdering Order, llvm::SyncScope::ID Scope) argument
699 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *Expr, Address Dest, Address Ptr, Address Val1, Address Val2, llvm::Value *IsWeak, llvm::Value *FailureOrder, uint64_t Size, llvm::AtomicOrdering Order, llvm::Value *Scope) argument
815 llvm::Value *Order = EmitScalarExpr(E->getOrder()); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.h294 // Allocation orders. Order[0] always contains all registers in Members.
511 unsigned Order = 0; // Cache the sort key. member in struct:llvm::RegUnitSet
734 unsigned getRegSetIDAt(unsigned Order) const {
735 return RegUnitSetOrder[Order];
738 const RegUnitSet &getRegSetAt(unsigned Order) const {
739 return RegUnitSets[RegUnitSetOrder[Order]];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp107 Coloring(ArrayRef<Node> Ord) : Order(Ord) {
126 ArrayRef<Node> Order; member in struct:__anon2255::Coloring
134 Node Num = Order.size();
165 // Add Order[P] and Order[conj(P)] to Edges.
166 for (unsigned P = 0; P != Order.size(); ++P) {
167 Node I = Order[P];
170 Node PC = Order[conj(P)];
176 for (unsigned I = 0; I != Order.size(); ++I) {
263 for (unsigned I = 0; I != Order
375 std::vector<ElemType> Order; member in namespace:__anon2256
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h153 ArrayRef<MCPhysReg> Order,

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