| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 122 AtomicOrdering Ord) const override;
124 AtomicOrdering Ord) const override;
212 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override;
219 AtomicOrdering Ord) const override;
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| H A D | RISCVISelLowering.cpp | 2765 AtomicOrdering Ord) const {
2766 if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
2767 return Builder.CreateFence(Ord);
2768 if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord))
2775 AtomicOrdering Ord) const {
2776 if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
2848 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
2900 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
2902 Value *Ordering = Builder.getIntN(XLen, static_cast<uint64_t>(Ord));
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 62 FrameRef(MachineInstr *I, int64_t Offset, int Idx, unsigned Ord) : argument
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {}
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 107 Coloring(ArrayRef<Node> Ord) : Order(Ord) { argument
333 PermNetwork(ArrayRef<ElemType> Ord, unsigned Mult = 1) { argument
334 Order.assign(Ord.data(), Ord.data()+Ord.size());
381 ForwardDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {} argument
395 ReverseDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {} argument
409 BenesNetwork(ArrayRef<ElemType> Ord) argument
[all...] |
| H A D | HexagonISelLowering.h | 321 AtomicOrdering Ord) const override;
323 Value *Addr, AtomicOrdering Ord) const override;
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| H A D | HexagonGenInsert.cpp | 388 : MaxSize(MaxORLSize), Ord(RO) {}
415 const RegisterOrdering &Ord;
444 iterator L = llvm::lower_bound(Seq, VR, Ord);
457 iterator L = llvm::lower_bound(Seq, VR, Ord);
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| H A D | HexagonISelLowering.cpp | 3299 AtomicOrdering Ord) const {
3322 Value *Val, Value *Addr, AtomicOrdering Ord) const {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 542 AtomicOrdering Ord) const override;
544 Value *Addr, AtomicOrdering Ord) const override;
549 AtomicOrdering Ord) const override;
551 AtomicOrdering Ord) const override;
|
| H A D | ARMISelLowering.cpp | 3808 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue()); local
3814 Ord == AtomicOrdering::Release) {
16726 AtomicOrdering Ord) const {
16727 switch (Ord) {
16751 AtomicOrdering Ord) const {
16752 switch (Ord) {
16900 AtomicOrdering Ord) const {
16903 bool IsAcquire = isAcquireOrStronger(Ord);
16945 AtomicOrdering Ord) const {
16947 bool IsRelease = isReleaseOrStronger(Ord);
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1716 AtomicOrdering Ord) const {
1723 Value *Addr, AtomicOrdering Ord) const {
1734 AtomicOrdering Ord) const {
1743 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1781 AtomicOrdering Ord) const {
1782 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1783 return Builder.CreateFence(Ord);
1790 AtomicOrdering Ord) const {
1791 if (isAcquireOrStronger(Ord))
1792 return Builder.CreateFence(Ord);
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); local
520 for (auto Reg : Ord) {
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| H A D | AArch64ISelLowering.h | 471 AtomicOrdering Ord) const override;
473 Value *Addr, AtomicOrdering Ord) const override;
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| H A D | AArch64FastISel.cpp | 2226 AtomicOrdering Ord = SI->getOrdering(); local
2228 if (isReleaseOrStronger(Ord)) {
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| H A D | AArch64ISelLowering.cpp | 13103 AtomicOrdering Ord) const {
13106 bool IsAcquire = isAcquireOrStronger(Ord);
13149 AtomicOrdering Ord) const {
13151 bool IsRelease = isReleaseOrStronger(Ord);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/ObjectYAML/ |
| H A D | CodeViewYAMLSymbols.cpp | 167 ThunkOrdinal &Ord) {
170 io.enumCase(Ord, E.Name.str().c_str(), static_cast<ThunkOrdinal>(E.Value));
166 enumeration(IO &io, ThunkOrdinal &Ord) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 771 AtomicOrdering Ord) const override;
773 AtomicOrdering Ord) const override;
|
| H A D | PPCISelLowering.cpp | 10618 AtomicOrdering Ord) const {
10619 if (Ord == AtomicOrdering::SequentiallyConsistent)
10621 if (isReleaseOrStronger(Ord))
10628 AtomicOrdering Ord) const {
10629 if (Inst->hasAtomicLoad() && isAcquireOrStronger(Ord)) {
|