Searched refs:OUT_RING (Results 1 - 14 of 14) sorted by relevance

/freebsd-11-stable/sys/dev/drm/
H A Dr128_state.c53 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
54 OUT_RING(boxes[0].x1);
55 OUT_RING(boxes[0].x2 - 1);
56 OUT_RING(boxes[0].y1);
57 OUT_RING(boxes[0].y2 - 1);
62 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
63 OUT_RING(boxes[1].x1);
64 OUT_RING(boxes[1].x2 - 1);
65 OUT_RING(boxes[1].y1);
66 OUT_RING(boxe
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H A Dr600_blit.c1220 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1221 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1222 OUT_RING(gpu_addr >> 8);
1223 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
1224 OUT_RING(2 << 0);
1227 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1228 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
1229 OUT_RING(gpu_addr >> 8);
1232 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
1233 OUT_RING((R600_CB_COLOR0_SIZ
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H A Dradeon_state.c437 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
438 OUT_RING((box->y1 << 16) | box->x1);
439 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
440 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
469 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
470 OUT_RING(ctx->pp_misc);
471 OUT_RING(ctx->pp_fog_color);
472 OUT_RING(ctx->re_solid_color);
473 OUT_RING(ctx->rb3d_blendcntl);
474 OUT_RING(ct
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H A Dr300_cmdbuf.c74 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
106 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
108 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
120 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
121 OUT_RING(0);
122 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
147 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
148 OUT_RING(R300_RB3D_DC_FLUSH);
151 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
152 OUT_RING(RADEON_WAIT_3D_IDLECLEA
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H A Di915_dma.c375 OUT_RING(cmd);
382 OUT_RING(cmd);
387 OUT_RING(0);
414 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
415 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
416 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
417 OUT_RING(DR4);
421 OUT_RING(GFX_OP_DRAWRECT_INFO);
422 OUT_RING(DR1);
423 OUT_RING((bo
[all...]
H A Dradeon_drv.h1908 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1910 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1911 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1917 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1919 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1920 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1926 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
1928 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1929 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1936 OUT_RING( CP_PACKET
2091 #define OUT_RING macro
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H A Dmach64_dma.c638 #define OUT_RING( x ) \ macro
641 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
681 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR );
682 OUT_RING( page );
683 OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET );
684 OUT_RING( 0 );
696 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR );
697 OUT_RING( page );
698 OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL );
699 OUT_RING(
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H A Di915_irq.c287 OUT_RING(MI_STORE_DWORD_INDEX);
288 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
289 OUT_RING(dev_priv->counter);
290 OUT_RING(MI_USER_INTERRUPT);
H A Dr128_drv.h457 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
458 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
520 #define OUT_RING( x ) do { \ macro
522 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
H A Dr600_cp.c2133 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2134 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2136 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2137 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2138 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2155 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2156 OUT_RING(0x00000001);
2158 OUT_RING(0x00000003);
2160 OUT_RING(0x00000000);
2161 OUT_RING((dev_pri
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H A Di915_drv.h590 #define OUT_RING(n) do { \ macro
591 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
H A Dradeon_cp.c584 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
585 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
/freebsd-11-stable/sys/dev/drm2/i915/
H A Di915_dma.c46 #define OUT_RING(x) \ macro
364 OUT_RING(buffer[i]);
366 OUT_RING(0);
393 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
394 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
395 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
396 OUT_RING(DR4);
402 OUT_RING(GFX_OP_DRAWRECT_INFO);
403 OUT_RING(DR1);
404 OUT_RING((bo
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/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_drv.h1932 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1933 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1938 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1939 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1944 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1945 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1951 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1952 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1957 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1958 OUT_RING(RADEON_RB3D_DC_FLUS
2105 #define OUT_RING macro
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