drm2/i915/i915_dma.c

46 #define OUT_RING(x) \
364 		OUT_RING(buffer[i]);
366 		OUT_RING(0);
393 		OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
394 		OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
395 		OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
396 		OUT_RING(DR4);
402 		OUT_RING(GFX_OP_DRAWRECT_INFO);
403 		OUT_RING(DR1);
404 		OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
405 		OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
406 		OUT_RING(DR4);
407 		OUT_RING(0);
430 		OUT_RING(MI_STORE_DWORD_INDEX);
431 		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
432 		OUT_RING(dev_priv->dri1.counter);
433 		OUT_RING(0);
502 				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
503 				OUT_RING(batch->start);
505 				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
506 				OUT_RING(batch->start | MI_BATCH_NON_SECURE);
513 			OUT_RING(MI_BATCH_BUFFER);
514 			OUT_RING(batch->start | MI_BATCH_NON_SECURE);
515 			OUT_RING(batch->start + batch->used - 4);
516 			OUT_RING(0);
524 			OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
525 			OUT_RING(MI_NOOP);
555 	OUT_RING(MI_FLUSH | MI_READ_FLUSH);
556 	OUT_RING(0);
558 	OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
559 	OUT_RING(0);
561 		OUT_RING(dev_priv->dri1.back_offset);
564 		OUT_RING(dev_priv->dri1.front_offset);
567 	OUT_RING(0);
569 	OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
570 	OUT_RING(0);
577 		OUT_RING(MI_STORE_DWORD_INDEX);
578 		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
579 		OUT_RING(dev_priv->dri1.counter);
580 		OUT_RING(0);
752 		OUT_RING(MI_STORE_DWORD_INDEX);
753 		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
754 		OUT_RING(dev_priv->dri1.counter);
755 		OUT_RING(MI_USER_INTERRUPT);