1142425Snectar/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2142425Snectar */ 3142425Snectar/*- 4142425Snectar * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5142425Snectar * All Rights Reserved. 6142425Snectar * 7142425Snectar * Permission is hereby granted, free of charge, to any person obtaining a 8142425Snectar * copy of this software and associated documentation files (the 9142425Snectar * "Software"), to deal in the Software without restriction, including 10142425Snectar * without limitation the rights to use, copy, modify, merge, publish, 11142425Snectar * distribute, sub license, and/or sell copies of the Software, and to 12142425Snectar * permit persons to whom the Software is furnished to do so, subject to 13142425Snectar * the following conditions: 14142425Snectar * 15142425Snectar * The above copyright notice and this permission notice (including the 16142425Snectar * next paragraph) shall be included in all copies or substantial portions 17142425Snectar * of the Software. 18142425Snectar * 19142425Snectar * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20142425Snectar * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21142425Snectar * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22142425Snectar * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23142425Snectar * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24142425Snectar * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25142425Snectar * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26142425Snectar * 27142425Snectar */ 28142425Snectar 29142425Snectar#include <sys/cdefs.h> 30142425Snectar__FBSDID("$FreeBSD$"); 31142425Snectar 32142425Snectar#include "dev/drm/drmP.h" 33142425Snectar#include "dev/drm/drm.h" 34238405Sjkim#include "dev/drm/i915_drm.h" 35142425Snectar#include "dev/drm/i915_drv.h" 36142425Snectar 37142425Snectar#define MAX_NOPID ((u32)~0) 38142425Snectar 39160814Ssimon/** 40238405Sjkim * Interrupts that are always left unmasked. 41194206Ssimon * 42238405Sjkim * Since pipe events are edge-triggered from the PIPESTAT register to IIR, 43142425Snectar * we leave them always unmasked in IMR and then control enabling them through 44142425Snectar * PIPESTAT alone. 45142425Snectar */ 46142425Snectar#define I915_INTERRUPT_ENABLE_FIX (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ 47142425Snectar I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) 48142425Snectar 49142425Snectar/** Interrupts that we mask and unmask at runtime. */ 50142425Snectar#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) 51142425Snectar 52142425Snectar/** These are all of the interrupts used by the driver */ 53142425Snectar#define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \ 54142425Snectar I915_INTERRUPT_ENABLE_VAR) 55160814Ssimon 56238405Sjkim#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ 57142425Snectar DRM_I915_VBLANK_PIPE_B) 58238405Sjkim 59238405Sjkimstatic inline void 60142425Snectari915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) 61142425Snectar{ 62142425Snectar mask &= I915_INTERRUPT_ENABLE_VAR; 63160814Ssimon if ((dev_priv->irq_mask_reg & mask) != 0) { 64238405Sjkim dev_priv->irq_mask_reg &= ~mask; 65142425Snectar I915_WRITE(IMR, dev_priv->irq_mask_reg); 66238405Sjkim (void) I915_READ(IMR); 67238405Sjkim } 68142425Snectar} 69142425Snectar 70142425Snectarstatic inline void 71142425Snectari915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) 72142425Snectar{ 73142425Snectar mask &= I915_INTERRUPT_ENABLE_VAR; 74142425Snectar if ((dev_priv->irq_mask_reg & mask) != mask) { 75142425Snectar dev_priv->irq_mask_reg |= mask; 76142425Snectar I915_WRITE(IMR, dev_priv->irq_mask_reg); 77142425Snectar (void) I915_READ(IMR); 78142425Snectar } 79142425Snectar} 80142425Snectar 81142425Snectarstatic inline u32 82142425Snectari915_pipestat(int pipe) 83142425Snectar{ 84142425Snectar if (pipe == 0) 85142425Snectar return PIPEASTAT; 86160814Ssimon if (pipe == 1) 87160814Ssimon return PIPEBSTAT; 88160814Ssimon return -EINVAL; 89160814Ssimon} 90160814Ssimon 91160814Ssimonvoid 92160814Ssimoni915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 93142425Snectar{ 94142425Snectar if ((dev_priv->pipestat[pipe] & mask) != mask) { 95142425Snectar u32 reg = i915_pipestat(pipe); 96142425Snectar 97284283Sjkim dev_priv->pipestat[pipe] |= mask; 98284283Sjkim /* Enable the interrupt, clear any pending status */ 99284283Sjkim I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 100142425Snectar (void) I915_READ(reg); 101142425Snectar } 102142425Snectar} 103142425Snectar 104160814Ssimonvoid 105160814Ssimoni915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 106142425Snectar{ 107142425Snectar if ((dev_priv->pipestat[pipe] & mask) != 0) { 108142425Snectar u32 reg = i915_pipestat(pipe); 109142425Snectar 110142425Snectar dev_priv->pipestat[pipe] &= ~mask; 111142425Snectar I915_WRITE(reg, dev_priv->pipestat[pipe]); 112160814Ssimon (void) I915_READ(reg); 113142425Snectar } 114142425Snectar} 115142425Snectar 116142425Snectar/** 117142425Snectar * i915_pipe_enabled - check if a pipe is enabled 118142425Snectar * @dev: DRM device 119142425Snectar * @pipe: pipe to check 120142425Snectar * 121142425Snectar * Reading certain registers when the pipe is disabled can hang the chip. 122142425Snectar * Use this routine to make sure the PLL is running and the pipe is active 123142425Snectar * before reading such registers if unsure. 124142425Snectar */ 125142425Snectarstatic int 126142425Snectari915_pipe_enabled(struct drm_device *dev, int pipe) 127142425Snectar{ 128142425Snectar drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 129142425Snectar unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; 130142425Snectar 131142425Snectar if (I915_READ(pipeconf) & PIPEACONF_ENABLE) 132142425Snectar return 1; 133284283Sjkim 134142425Snectar return 0; 135284283Sjkim} 136284283Sjkim 137284283Sjkim/* Called from drm generic code, passed a 'crtc', which 138291719Sjkim * we use as a pipe index 139284283Sjkim */ 140142425Snectaru32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 141142425Snectar{ 142142425Snectar drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 143238405Sjkim unsigned long high_frame; 144142425Snectar unsigned long low_frame; 145142425Snectar u32 high1, high2, low, count; 146238405Sjkim 147142425Snectar high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; 148142425Snectar low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; 149142425Snectar 150284283Sjkim if (!i915_pipe_enabled(dev, pipe)) { 151142425Snectar DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); 152142425Snectar return 0; 153284283Sjkim } 154142425Snectar 155142425Snectar /* 156142425Snectar * High & low register fields aren't synchronized, so make sure 157160814Ssimon * we get a low value that's stable across two reads of the high 158160814Ssimon * register. 159194206Ssimon */ 160238405Sjkim do { 161160814Ssimon high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 162194206Ssimon PIPE_FRAME_HIGH_SHIFT); 163160814Ssimon low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> 164238405Sjkim PIPE_FRAME_LOW_SHIFT); 165160814Ssimon high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 166160814Ssimon PIPE_FRAME_HIGH_SHIFT); 167238405Sjkim } while (high1 != high2); 168142425Snectar 169142425Snectar count = (high1 << 8) | low; 170142425Snectar 171142425Snectar return count; 172142425Snectar} 173142425Snectar 174142425Snectaru32 g45_get_vblank_counter(struct drm_device *dev, int pipe) 175160814Ssimon{ 176160814Ssimon drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 177160814Ssimon int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; 178238405Sjkim 179238405Sjkim if (!i915_pipe_enabled(dev, pipe)) { 180238405Sjkim DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); 181237657Sjkim return 0; 182237657Sjkim } 183237657Sjkim 184237657Sjkim return I915_READ(reg); 185237657Sjkim} 186237657Sjkim 187237657Sjkimirqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 188237657Sjkim{ 189237657Sjkim struct drm_device *dev = (struct drm_device *) arg; 190160814Ssimon drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 191142425Snectar u32 iir, new_iir; 192160814Ssimon u32 pipea_stats, pipeb_stats; 193160814Ssimon u32 vblank_status; 194238405Sjkim u32 vblank_enable; 195238405Sjkim int irq_received; 196238405Sjkim 197237657Sjkim iir = I915_READ(IIR); 198237657Sjkim 199237657Sjkim if (IS_I965G(dev)) { 200237657Sjkim vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; 201237657Sjkim vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; 202237657Sjkim } else { 203237657Sjkim vblank_status = I915_VBLANK_INTERRUPT_STATUS; 204237657Sjkim vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; 205237657Sjkim } 206237657Sjkim 207160814Ssimon for (;;) { 208160814Ssimon irq_received = iir != 0; 209160814Ssimon 210238405Sjkim /* Can't rely on pipestat interrupt bit in iir as it might 211238405Sjkim * have been cleared after the pipestat interrupt was received. 212238405Sjkim * It doesn't set the bit in iir again, but it still produces 213237657Sjkim * interrupts (for non-MSI). 214237657Sjkim */ 215237657Sjkim DRM_SPINLOCK(&dev_priv->user_irq_lock); 216237657Sjkim pipea_stats = I915_READ(PIPEASTAT); 217237657Sjkim pipeb_stats = I915_READ(PIPEBSTAT); 218237657Sjkim 219237657Sjkim /* 220237657Sjkim * Clear the PIPE(A|B)STAT regs before the IIR 221237657Sjkim */ 222237657Sjkim if (pipea_stats & 0x8000ffff) { 223160814Ssimon I915_WRITE(PIPEASTAT, pipea_stats); 224142425Snectar irq_received = 1; 225160814Ssimon } 226160814Ssimon 227238405Sjkim if (pipeb_stats & 0x8000ffff) { 228238405Sjkim I915_WRITE(PIPEBSTAT, pipeb_stats); 229238405Sjkim irq_received = 1; 230237657Sjkim } 231237657Sjkim DRM_SPINUNLOCK(&dev_priv->user_irq_lock); 232237657Sjkim 233237657Sjkim if (!irq_received) 234237657Sjkim break; 235237657Sjkim 236237657Sjkim I915_WRITE(IIR, iir); 237237657Sjkim new_iir = I915_READ(IIR); /* Flush posted writes */ 238237657Sjkim 239160814Ssimon if (dev_priv->sarea_priv) 240238405Sjkim dev_priv->sarea_priv->last_dispatch = 241238405Sjkim READ_BREADCRUMB(dev_priv); 242238405Sjkim 243238405Sjkim if (iir & I915_USER_INTERRUPT) { 244237657Sjkim DRM_WAKEUP(&dev_priv->irq_queue); 245237657Sjkim } 246238405Sjkim 247238405Sjkim if (pipea_stats & vblank_status) 248238405Sjkim drm_handle_vblank(dev, 0); 249238405Sjkim 250238405Sjkim if (pipeb_stats & vblank_status) 251238405Sjkim drm_handle_vblank(dev, 1); 252237657Sjkim 253238405Sjkim /* With MSI, interrupts are only generated when iir 254238405Sjkim * transitions from zero to nonzero. If another bit got 255238405Sjkim * set while we were handling the existing iir bits, then 256238405Sjkim * we would never get another interrupt. 257238405Sjkim * 258238405Sjkim * This is fine on non-MSI as well, as if we hit this path 259238405Sjkim * we avoid exiting the interrupt handler only to generate 260194206Ssimon * another one. 261238405Sjkim * 262238405Sjkim * Note that for MSI this could cause a stray interrupt report 263238405Sjkim * if an interrupt landed in the time between writing IIR and 264238405Sjkim * the posting read. This should be rare enough to never 265238405Sjkim * trigger the 99% of 100,000 interrupts test for disabling 266238405Sjkim * stray interrupts. 267237657Sjkim */ 268237657Sjkim iir = new_iir; 269237657Sjkim } 270238405Sjkim} 271237657Sjkim 272237657Sjkimstatic int i915_emit_irq(struct drm_device * dev) 273237657Sjkim{ 274237657Sjkim drm_i915_private_t *dev_priv = dev->dev_private; 275237657Sjkim RING_LOCALS; 276160814Ssimon 277160814Ssimon i915_kernel_lost_context(dev); 278160814Ssimon 279238405Sjkim if (++dev_priv->counter > 0x7FFFFFFFUL) 280238405Sjkim dev_priv->counter = 0; 281238405Sjkim if (dev_priv->sarea_priv) 282237657Sjkim dev_priv->sarea_priv->last_enqueue = dev_priv->counter; 283237657Sjkim 284237657Sjkim DRM_DEBUG("emitting: %d\n", dev_priv->counter); 285237657Sjkim 286237657Sjkim BEGIN_LP_RING(4); 287237657Sjkim OUT_RING(MI_STORE_DWORD_INDEX); 288237657Sjkim OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 289237657Sjkim OUT_RING(dev_priv->counter); 290237657Sjkim OUT_RING(MI_USER_INTERRUPT); 291160814Ssimon ADVANCE_LP_RING(); 292160814Ssimon 293160814Ssimon return dev_priv->counter; 294238405Sjkim} 295238405Sjkim 296238405Sjkimvoid i915_user_irq_get(struct drm_device *dev) 297237657Sjkim{ 298237657Sjkim drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 299237657Sjkim 300237657Sjkim if (dev->irq_enabled == 0) 301237657Sjkim return; 302237657Sjkim 303237657Sjkim DRM_DEBUG("\n"); 304237657Sjkim DRM_SPINLOCK(&dev_priv->user_irq_lock); 305237657Sjkim if (++dev_priv->user_irq_refcount == 1) 306237657Sjkim i915_enable_irq(dev_priv, I915_USER_INTERRUPT); 307160814Ssimon DRM_SPINUNLOCK(&dev_priv->user_irq_lock); 308160814Ssimon} 309160814Ssimon 310238405Sjkimvoid i915_user_irq_put(struct drm_device *dev) 311238405Sjkim{ 312238405Sjkim drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 313237657Sjkim 314237657Sjkim if (dev->irq_enabled == 0) 315237657Sjkim return; 316237657Sjkim 317237657Sjkim DRM_SPINLOCK(&dev_priv->user_irq_lock); 318237657Sjkim KASSERT(dev_priv->user_irq_refcount > 0, ("invalid refcount")); 319237657Sjkim if (--dev_priv->user_irq_refcount == 0) 320237657Sjkim i915_disable_irq(dev_priv, I915_USER_INTERRUPT); 321237657Sjkim DRM_SPINUNLOCK(&dev_priv->user_irq_lock); 322237657Sjkim} 323160814Ssimon 324142425Snectarstatic int i915_wait_irq(struct drm_device * dev, int irq_nr) 325160814Ssimon{ 326160814Ssimon drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 327238405Sjkim int ret = 0; 328238405Sjkim 329238405Sjkim if (READ_BREADCRUMB(dev_priv) >= irq_nr) { 330237657Sjkim if (dev_priv->sarea_priv) { 331237657Sjkim dev_priv->sarea_priv->last_dispatch = 332237657Sjkim READ_BREADCRUMB(dev_priv); 333237657Sjkim } 334237657Sjkim return 0; 335237657Sjkim } 336237657Sjkim 337237657Sjkim if (dev_priv->sarea_priv) 338237657Sjkim dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 339160814Ssimon 340142425Snectar DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, 341160814Ssimon READ_BREADCRUMB(dev_priv)); 342142425Snectar 343238405Sjkim i915_user_irq_get(dev); 344238405Sjkim DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, 345238405Sjkim READ_BREADCRUMB(dev_priv) >= irq_nr); 346237657Sjkim i915_user_irq_put(dev); 347237657Sjkim 348237657Sjkim if (ret == -ERESTART) 349237657Sjkim DRM_DEBUG("restarting syscall\n"); 350237657Sjkim 351237657Sjkim if (ret == -EBUSY) { 352237657Sjkim DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", 353237657Sjkim READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); 354237657Sjkim } 355160814Ssimon 356142425Snectar return ret; 357160814Ssimon} 358160814Ssimon 359160814Ssimon/* Needs the lock as it touches the ring. 360238405Sjkim */ 361238405Sjkimint i915_irq_emit(struct drm_device *dev, void *data, 362238405Sjkim struct drm_file *file_priv) 363237657Sjkim{ 364237657Sjkim drm_i915_private_t *dev_priv = dev->dev_private; 365237657Sjkim drm_i915_irq_emit_t *emit = data; 366237657Sjkim int result; 367237657Sjkim 368237657Sjkim if (!dev_priv) { 369237657Sjkim DRM_ERROR("called with no initialization\n"); 370238405Sjkim return -EINVAL; 371238405Sjkim } 372238405Sjkim 373238405Sjkim RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 374160814Ssimon 375160814Ssimon result = i915_emit_irq(dev); 376160814Ssimon 377238405Sjkim if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { 378238405Sjkim DRM_ERROR("copy_to_user\n"); 379238405Sjkim return -EFAULT; 380237657Sjkim } 381237657Sjkim 382237657Sjkim return 0; 383237657Sjkim} 384237657Sjkim 385237657Sjkim/* Doesn't need the hardware lock. 386237657Sjkim */ 387237657Sjkimint i915_irq_wait(struct drm_device *dev, void *data, 388237657Sjkim struct drm_file *file_priv) 389160814Ssimon{ 390160814Ssimon drm_i915_private_t *dev_priv = dev->dev_private; 391160814Ssimon drm_i915_irq_wait_t *irqwait = data; 392160814Ssimon 393238405Sjkim if (!dev_priv) { 394238405Sjkim DRM_ERROR("called with no initialization\n"); 395238405Sjkim return -EINVAL; 396237657Sjkim } 397237657Sjkim 398237657Sjkim return i915_wait_irq(dev, irqwait->irq_seq); 399237657Sjkim} 400237657Sjkim 401237657Sjkim/* Called from drm generic code, passed 'crtc' which 402237657Sjkim * we use as a pipe index 403237657Sjkim */ 404237657Sjkimint i915_enable_vblank(struct drm_device *dev, int pipe) 405160814Ssimon{ 406238405Sjkim drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 407238405Sjkim 408238405Sjkim if (!i915_pipe_enabled(dev, pipe)) 409238405Sjkim return -EINVAL; 410237657Sjkim 411238405Sjkim DRM_SPINLOCK(&dev_priv->user_irq_lock); 412238405Sjkim if (IS_I965G(dev)) 413238405Sjkim i915_enable_pipestat(dev_priv, pipe, 414238405Sjkim PIPE_START_VBLANK_INTERRUPT_ENABLE); 415238405Sjkim else 416238405Sjkim i915_enable_pipestat(dev_priv, pipe, 417238405Sjkim PIPE_VBLANK_INTERRUPT_ENABLE); 418238405Sjkim DRM_SPINUNLOCK(&dev_priv->user_irq_lock); 419238405Sjkim return 0; 420238405Sjkim} 421160814Ssimon 422238405Sjkim/* Called from drm generic code, passed 'crtc' which 423238405Sjkim * we use as a pipe index 424238405Sjkim */ 425238405Sjkimvoid i915_disable_vblank(struct drm_device *dev, int pipe) 426237657Sjkim{ 427237657Sjkim drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 428238405Sjkim 429238405Sjkim DRM_SPINLOCK(&dev_priv->user_irq_lock); 430238405Sjkim i915_disable_pipestat(dev_priv, pipe, 431238405Sjkim PIPE_VBLANK_INTERRUPT_ENABLE | 432238405Sjkim PIPE_START_VBLANK_INTERRUPT_ENABLE); 433238405Sjkim DRM_SPINUNLOCK(&dev_priv->user_irq_lock); 434237657Sjkim} 435238405Sjkim 436238405Sjkim/* Set the vblank monitor pipe 437238405Sjkim */ 438238405Sjkimint i915_vblank_pipe_set(struct drm_device *dev, void *data, 439238405Sjkim struct drm_file *file_priv) 440238405Sjkim{ 441238405Sjkim drm_i915_private_t *dev_priv = dev->dev_private; 442160814Ssimon 443238405Sjkim if (!dev_priv) { 444238405Sjkim DRM_ERROR("called with no initialization\n"); 445238405Sjkim return -EINVAL; 446238405Sjkim } 447237657Sjkim 448237657Sjkim return 0; 449238405Sjkim} 450238405Sjkim 451238405Sjkimint i915_vblank_pipe_get(struct drm_device *dev, void *data, 452238405Sjkim struct drm_file *file_priv) 453238405Sjkim{ 454238405Sjkim drm_i915_private_t *dev_priv = dev->dev_private; 455237657Sjkim drm_i915_vblank_pipe_t *pipe = data; 456238405Sjkim 457238405Sjkim if (!dev_priv) { 458238405Sjkim DRM_ERROR("called with no initialization\n"); 459238405Sjkim return -EINVAL; 460238405Sjkim } 461238405Sjkim 462238405Sjkim pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 463160814Ssimon 464142425Snectar return 0; 465160814Ssimon} 466160814Ssimon 467160814Ssimon/** 468238405Sjkim * Schedule buffer swap at given vertical blank. 469238405Sjkim */ 470238405Sjkimint i915_vblank_swap(struct drm_device *dev, void *data, 471237657Sjkim struct drm_file *file_priv) 472237657Sjkim{ 473237657Sjkim /* The delayed swap mechanism was fundamentally racy, and has been 474237657Sjkim * removed. The model was that the client requested a delayed flip/swap 475237657Sjkim * from the kernel, then waited for vblank before continuing to perform 476237657Sjkim * rendering. The problem was that the kernel might wake the client 477237657Sjkim * up before it dispatched the vblank swap (since the lock has to be 478238405Sjkim * held while touching the ringbuffer), in which case the client would 479238405Sjkim * clear and start the next frame before the swap occurred, and 480238405Sjkim * flicker would occur in addition to likely missing the vblank. 481238405Sjkim * 482160814Ssimon * In the absence of this ioctl, userland falls back to a correct path 483142425Snectar * of waiting for a vblank, then dispatching the swap on its own. 484160814Ssimon * Context switching to userland and back is plenty fast enough for 485142425Snectar * meeting the requirements of vblank swapping. 486238405Sjkim */ 487238405Sjkim return -EINVAL; 488238405Sjkim} 489237657Sjkim 490237657Sjkim/* drm_dma.h hooks 491237657Sjkim*/ 492237657Sjkimvoid i915_driver_irq_preinstall(struct drm_device * dev) 493237657Sjkim{ 494237657Sjkim drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 495237657Sjkim 496237657Sjkim I915_WRITE(HWSTAM, 0xeffe); 497237657Sjkim I915_WRITE(PIPEASTAT, 0); 498237657Sjkim I915_WRITE(PIPEBSTAT, 0); 499238405Sjkim I915_WRITE(IMR, 0xffffffff); 500238405Sjkim I915_WRITE(IER, 0x0); 501238405Sjkim (void) I915_READ(IER); 502238405Sjkim} 503238405Sjkim 504238405Sjkimint i915_driver_irq_postinstall(struct drm_device *dev) 505238405Sjkim{ 506238405Sjkim drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 507238405Sjkim 508238405Sjkim dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 509238405Sjkim 510238405Sjkim /* Unmask the interrupts that we always want on. */ 511238405Sjkim dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; 512238405Sjkim 513238405Sjkim /* Disable pipe interrupt enables, clear pending pipe status */ 514238405Sjkim I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); 515160814Ssimon I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); 516142425Snectar 517160814Ssimon /* Clear pending interrupt status */ 518160814Ssimon I915_WRITE(IIR, I915_READ(IIR)); 519160814Ssimon 520238405Sjkim I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); 521238405Sjkim I915_WRITE(IMR, dev_priv->irq_mask_reg); 522238405Sjkim I915_WRITE(PIPEASTAT, dev_priv->pipestat[0] | 523237657Sjkim (dev_priv->pipestat[0] >> 16)); 524237657Sjkim I915_WRITE(PIPEBSTAT, dev_priv->pipestat[1] | 525237657Sjkim (dev_priv->pipestat[1] >> 16)); 526237657Sjkim (void) I915_READ(IER); 527237657Sjkim 528237657Sjkim return 0; 529237657Sjkim} 530238405Sjkim 531238405Sjkimvoid i915_driver_irq_uninstall(struct drm_device * dev) 532238405Sjkim{ 533238405Sjkim drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 534160814Ssimon 535160814Ssimon if (!dev_priv) 536160814Ssimon return; 537238405Sjkim 538238405Sjkim dev_priv->vblank_pipe = 0; 539238405Sjkim 540237657Sjkim I915_WRITE(HWSTAM, 0xffffffff); 541237657Sjkim I915_WRITE(PIPEASTAT, 0); 542237657Sjkim I915_WRITE(PIPEBSTAT, 0); 543237657Sjkim I915_WRITE(IMR, 0xffffffff); 544237657Sjkim I915_WRITE(IER, 0x0); 545237657Sjkim 546237657Sjkim I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); 547237657Sjkim I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); 548237657Sjkim I915_WRITE(IIR, I915_READ(IIR)); 549160814Ssimon} 550142425Snectar