/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 194 /// MERGE_VALUES - This node takes multiple discrete operands and returns 199 MERGE_VALUES, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 173 case ISD::MERGE_VALUES: return "merge_values";
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H A D | LegalizeVectorOps.cpp | 335 case ISD::MERGE_VALUES: 844 case ISD::MERGE_VALUES:
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H A D | InstrEmitter.cpp | 991 case ISD::MERGE_VALUES:
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H A D | SelectionDAGBuilder.cpp | 887 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); 2933 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 3412 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3828 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3868 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 4162 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, 8540 if (Val.getOpcode() == ISD::MERGE_VALUES) { 8556 SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 9406 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
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H A D | LegalizeFloatTypes.cpp | 61 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; 1121 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
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H A D | LegalizeVectorTypes.cpp | 50 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 825 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 2687 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
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H A D | ScheduleDAGRRList.cpp | 706 case ISD::MERGE_VALUES:
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H A D | LegalizeDAG.cpp | 1073 case ISD::MERGE_VALUES: 2862 case ISD::MERGE_VALUES:
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H A D | LegalizeIntegerTypes.cpp | 55 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; 1803 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
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H A D | SelectionDAG.cpp | 4557 case ISD::MERGE_VALUES: 6651 /// getMergeValues - Create a MERGE_VALUES node from the given operands. 6660 return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops);
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H A D | TargetLowering.cpp | 6770 // Callers expect a MERGE_VALUES node. 7575 assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
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H A D | DAGCombiner.cpp | 1507 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1904 /// MERGE_VALUES can always be eliminated. 1907 // Replacing results may cause a different MERGE_VALUES to suddenly 11048 if (Elt.getOpcode() != ISD::MERGE_VALUES)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1644 case ExtractValue: return ISD::MERGE_VALUES; 1645 case InsertValue: return ISD::MERGE_VALUES;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 824 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); 862 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); 880 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
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H A D | SIISelLowering.cpp | 4329 if (Res.getOpcode() == ISD::MERGE_VALUES) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 3635 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); 3701 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); 4107 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), 5983 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0), 6049 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 4486 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); 4547 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); 8869 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry); 8943 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, 16262 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VT, VT), Values);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 22020 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC); 24868 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, 24889 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, 24914 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid, 24989 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 2482 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 13524 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other),
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