Searched refs:Insn (Results 1 - 25 of 32) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp45 uint64_t &Size, uint16_t &Insn) {
52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
57 uint64_t &Size, uint32_t &Insn) {
64 Insn =
92 unsigned Insn,
97 unsigned Insn,
102 unsigned Insn,
107 unsigned Insn,
112 unsigned Insn,
117 unsigned Insn,
44 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint16_t &Insn) argument
56 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) argument
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, unsigned &Op3) argument
274 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
344 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
357 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
370 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
383 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
397 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
410 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
423 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
437 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
508 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
522 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
536 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
549 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
562 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
575 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
588 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
602 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
617 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
631 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
645 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
665 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
679 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
699 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
718 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionPrecedenceTracking.cpp59 const Instruction *Insn) {
61 getFirstSpecialInstruction(Insn->getParent());
62 return MaybeFirstSpecial && OI.dominates(MaybeFirstSpecial, Insn);
84 for (const Instruction &Insn : *BB)
85 if (isSpecialInstruction(&Insn)) {
86 assert(It->second == &Insn &&
127 const Instruction *Insn) const {
140 if (isGuaranteedToTransferExecutionToSuccessor(Insn))
142 if (isa<LoadInst>(Insn)) {
143 assert(cast<LoadInst>(Insn)
58 isPreceededBySpecialInstruction( const Instruction *Insn) argument
[all...]
H A DGuardUtils.cpp35 for (auto &Insn : *DeoptBB) {
36 if (match(&Insn, m_Intrinsic<Intrinsic::experimental_deoptimize>()))
38 if (Insn.mayHaveSideEffects())
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DInstructionPrecedenceTracking.h63 /// Returns true iff the first special instruction of \p Insn's block exists
64 /// and dominates \p Insn.
65 bool isPreceededBySpecialInstruction(const Instruction *Insn);
67 /// A predicate that defines whether or not the instruction \p Insn is
72 virtual bool isSpecialInstruction(const Instruction *Insn) const = 0;
114 /// Returns true if the first ICFI of Insn's block exists and dominates Insn.
115 bool isDominatedByICFIFromSameBlock(const Instruction *Insn) { argument
116 return isPreceededBySpecialInstruction(Insn);
119 virtual bool isSpecialInstruction(const Instruction *Insn) cons
140 isDominatedByMemoryWriteFromSameBlock(const Instruction *Insn) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp54 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
57 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
60 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
63 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
70 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
76 uint32_t &Insn) {
84 Insn =
90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { argument
101 AluOp = (Insn >> 8) & 0x7;
105 AluOp |= 0x20 | (((Insn >>
75 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t &Size, uint32_t &Insn) argument
135 uint32_t Insn; local
174 decodeRiMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
186 decodeRrMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
198 decodeSplsValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
219 decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address, const void *Decoder) argument
227 decodeShiftImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.h29 SmallVectorImpl<ImmInsnModel> &Insn);
H A DAArch64ExpandImm.cpp45 SmallVectorImpl<ImmInsnModel> &Insn) {
69 Insn.push_back({ AArch64::ORRXri, 0, Encoding });
82 Insn.push_back({ AArch64::MOVKXi, Imm16,
97 Insn.push_back({ AArch64::MOVKXi, Imm16,
153 SmallVectorImpl<ImmInsnModel> &Insn) {
225 Insn.push_back({ AArch64::ORRXri, 0, Encoding });
228 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx),
237 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx),
248 SmallVectorImpl<ImmInsnModel> &Insn) {
280 Insn
44 tryToreplicateChunks(uint64_t UImm, SmallVectorImpl<ImmInsnModel> &Insn) argument
152 trySequenceOfOnes(uint64_t UImm, SmallVectorImpl<ImmInsnModel> &Insn) argument
246 expandMOVImmSimple(uint64_t Imm, unsigned BitSize, unsigned OneChunks, unsigned ZeroChunks, SmallVectorImpl<ImmInsnModel> &Insn) argument
305 expandMOVImm(uint64_t Imm, unsigned BitSize, SmallVectorImpl<ImmInsnModel> &Insn) argument
[all...]
H A DAArch64ExpandPseudoInsts.cpp124 SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn; local
125 AArch64_IMM::expandMOVImm(Imm, BitSize, Insn);
126 assert(Insn.size() != 0);
129 for (auto I = Insn.begin(), E = Insn.end(); I != E; ++I) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp51 uint64_t &Size, uint32_t &Insn) {
54 Insn =
60 uint64_t &Size, uint64_t &Insn) {
62 Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
70 uint64_t &Size, uint64_t &Insn) {
72 Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
79 uint64_t &Size, uint32_t &Insn) {
81 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
145 static unsigned decodeCField(unsigned Insn) { argument
146 return fieldFromInstruction(Insn,
50 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
59 readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn) argument
69 readInstruction48(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn) argument
78 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
149 decodeBField(unsigned Insn) argument
154 decodeAField(unsigned Insn) argument
158 DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Dec) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp113 unsigned Insn,
147 unsigned Insn,
217 unsigned Insn,
267 unsigned Insn,
274 unsigned Insn,
279 unsigned Insn,
284 unsigned Insn,
289 unsigned Insn,
293 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
297 unsigned Insn,
1066 DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) argument
1108 DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) argument
1150 DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) argument
1165 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian) argument
1185 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips) argument
1223 uint32_t Insn; local
1532 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1554 DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1575 DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1593 DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1610 DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1627 DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1644 DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1661 DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1676 DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1689 DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1704 DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1750 DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1808 DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1824 DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1840 DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1865 DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1886 DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1921 DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1939 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1957 DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1975 DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1993 DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2011 DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2029 DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2045 DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2228 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2304 DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2313 DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2373 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2386 DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2392 DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2398 DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2412 DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2451 DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2475 DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2543 DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp78 uint64_t &Size, uint32_t &Insn) {
85 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
91 uint64_t &Size, uint32_t &Insn) {
99 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
117 uint32_t Insn; local
123 Result = readInstruction16(Bytes, Address, Size, Insn);
129 Insn, Address, this, STI);
137 Result = readInstruction32(Bytes, Address, Size, Insn);
141 Result = decodeInstruction(getDecoderTable(Size), Instr, Insn,
77 readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
90 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp246 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
248 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
251 unsigned Insn,
254 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
256 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
258 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
260 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
264 unsigned Insn,
267 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
269 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
581 checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &CS, uint32_t Insn, DecodeStatus Result) argument
638 uint32_t Insn = local
1644 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1823 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1972 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2163 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2192 DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2215 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2307 DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2329 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2376 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2418 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2442 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2469 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2497 DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2518 DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2612 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2639 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2681 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2957 DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2970 DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2985 DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2998 DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3008 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3278 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3325 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3373 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3408 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3461 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3507 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3535 DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3560 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3603 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3639 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3763 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3846 DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3930 DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
4010 DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
4049 DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
4286 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4373 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
4384 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
4409 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
4420 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4433 DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4448 DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4510 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4526 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4747 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4768 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4794 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4819 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4846 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4871 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4896 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4963 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5028 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5095 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5158 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5228 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5291 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5372 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5444 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5470 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5496 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5526 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5563 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5597 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument
5634 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5661 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5720 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5779 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5976 DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
6071 DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
6419 DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
6442 DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
6467 DecodeMVEOverlappingLongShift( MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
6546 DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
6566 DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
6603 DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
6613 DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
6621 DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp240 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
243 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
246 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
250 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
253 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
259 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, argument
262 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
269 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, argument
274 fieldFromInstruction(Insn, 1
281 decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
294 decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
303 decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
320 uint32_t Insn; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp55 CodeGenInstruction &Insn,
73 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, argument
92 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
96 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
100 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
102 OpsAdded += Insn.Operands[i].MINumOperands;
111 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
139 CodeGenInstruction Insn(Operator);
141 if (Insn.isCodeGenOnly || Insn
[all...]
H A DFixedLenDecoderEmitter.cpp420 void insnWithID(insn_t &Insn, unsigned Opcode) const { argument
433 Insn.push_back(BIT_UNSET);
435 Insn.push_back(bitFromBits(Bits, i));
453 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit,
481 const insn_t &Insn) const;
562 insn_t Insn; local
565 Owner->insnWithID(Insn, Owner->Opcodes[i].EncodingID);
569 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits);
994 bool FilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn,
999 if (Insn[StartBi
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp181 static AddrMode DecodeSrcAddrModeI(unsigned Insn) { argument
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4);
183 unsigned As = fieldFromInstruction(Insn, 4, 2);
187 static AddrMode DecodeSrcAddrModeII(unsigned Insn) { argument
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4);
189 unsigned As = fieldFromInstruction(Insn, 4, 2);
193 static AddrMode DecodeDstAddrMode(unsigned Insn) { argument
194 unsigned Rd = fieldFromInstruction(Insn, 0, 4);
195 unsigned Ad = fieldFromInstruction(Insn, 7, 1);
233 uint64_t Insn
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp126 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, argument
128 unsigned Register = (Insn >> 16) & 0xf;
130 unsigned Offset = (Insn & 0xffff);
138 uint64_t &Size, uint64_t &Insn,
156 Insn = Make_64(Hi, Lo);
166 uint64_t Insn, Hi; local
169 Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian);
172 uint8_t InstClass = getInstClass(Insn);
173 uint8_t InstMode = getInstMode(Insn);
175 getInstSize(Insn) !
137 readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn, bool IsLittleEndian) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldELFMips.cpp215 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); local
233 Insn = (Insn & 0xffff0000) | (Value & 0x0000ffff);
234 writeBytesUnaligned(Insn, TargetPtr, 4);
237 Insn = (Insn & 0xfffc0000) | (Value & 0x0003ffff);
238 writeBytesUnaligned(Insn, TargetPtr, 4);
241 Insn = (Insn & 0xfff80000) | (Value & 0x0007ffff);
242 writeBytesUnaligned(Insn, TargetPt
[all...]
H A DRuntimeDyldMachOARM.h272 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); variable
275 Insn = (Insn & 0x8f00fbf0) | ((Value & 0xf000) >> 12) |
279 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff);
280 writeBytesUnaligned(Insn, LocalAddress, 4);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp1705 InternalInstruction Insn; local
1706 memset(&Insn, 0, sizeof(InternalInstruction));
1707 Insn.bytes = Bytes;
1708 Insn.startLocation = Address;
1709 Insn.readerCursor = Address;
1710 Insn.mode = fMode;
1712 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) ||
1713 getInstructionID(&Insn, MII.get()) || Insn
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp336 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); variable
339 if (Insn == 0xd503245f) {
341 Insn = support::endian::read32le(PltContents.data() + Byte + Off);
344 if ((Insn & 0x9f000000) != 0x90000000)
348 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DGVNHoist.cpp398 Instruction *Insn = MU->getMemoryInst(); local
401 if (BB == OldBB && firstInBB(OldPt, Insn))
407 if (firstInBB(Insn, NewPt))
601 Instruction *Insn = CHI.I; local
602 if (!Insn) // No instruction was inserted in this CHI.
605 if (safeToHoistScalar(BB, Insn->getParent(), NumBBsOnAllPaths))
608 MemoryUseOrDef *UD = MSSA->getMemoryAccess(Insn);
609 if (safeToHoistLdSt(BB->getTerminator(), Insn, UD, K, NumBBsOnAllPaths))
801 << ", for Insn: " << *V[i]);
H A DGuardWidening.cpp284 static bool isSupportedGuardInstruction(const Instruction *Insn) { argument
285 if (isGuard(Insn))
287 if (WidenBranchGuards && isGuardAsWidenableBranch(Insn))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp314 uint64_t &Size, uint32_t &Insn,
322 Insn = IsLittleEndian
335 uint32_t Insn; local
338 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
346 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
350 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
356 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
313 readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp174 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
264 uint32_t Insn = local
268 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
840 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, argument
845 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
846 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
847 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);

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