1224133Sdim//===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===// 2224133Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6224133Sdim// 7224133Sdim//===----------------------------------------------------------------------===// 8224133Sdim 9224133Sdim#include "CodeGenInstruction.h" 10239462Sdim#include "CodeGenTarget.h" 11224133Sdim#include "llvm/ADT/IndexedMap.h" 12239462Sdim#include "llvm/ADT/SmallVector.h" 13224133Sdim#include "llvm/ADT/StringMap.h" 14239462Sdim#include "llvm/Support/Debug.h" 15224133Sdim#include "llvm/Support/ErrorHandling.h" 16239462Sdim#include "llvm/TableGen/Error.h" 17239462Sdim#include "llvm/TableGen/Record.h" 18239462Sdim#include "llvm/TableGen/TableGenBackend.h" 19224133Sdim#include <vector> 20224133Sdimusing namespace llvm; 21224133Sdim 22276479Sdim#define DEBUG_TYPE "pseudo-lowering" 23276479Sdim 24239462Sdimnamespace { 25239462Sdimclass PseudoLoweringEmitter { 26239462Sdim struct OpData { 27239462Sdim enum MapKind { Operand, Imm, Reg }; 28239462Sdim MapKind Kind; 29239462Sdim union { 30239462Sdim unsigned Operand; // Operand number mapped to. 31239462Sdim uint64_t Imm; // Integer immedate value. 32239462Sdim Record *Reg; // Physical register. 33239462Sdim } Data; 34239462Sdim }; 35239462Sdim struct PseudoExpansion { 36239462Sdim CodeGenInstruction Source; // The source pseudo instruction definition. 37239462Sdim CodeGenInstruction Dest; // The destination instruction to lower to. 38239462Sdim IndexedMap<OpData> OperandMap; 39239462Sdim 40239462Sdim PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d, 41239462Sdim IndexedMap<OpData> &m) : 42239462Sdim Source(s), Dest(d), OperandMap(m) {} 43239462Sdim }; 44239462Sdim 45239462Sdim RecordKeeper &Records; 46239462Sdim 47239462Sdim // It's overkill to have an instance of the full CodeGenTarget object, 48239462Sdim // but it loads everything on demand, not in the constructor, so it's 49239462Sdim // lightweight in performance, so it works out OK. 50239462Sdim CodeGenTarget Target; 51239462Sdim 52239462Sdim SmallVector<PseudoExpansion, 64> Expansions; 53239462Sdim 54239462Sdim unsigned addDagOperandMapping(Record *Rec, DagInit *Dag, 55239462Sdim CodeGenInstruction &Insn, 56239462Sdim IndexedMap<OpData> &OperandMap, 57239462Sdim unsigned BaseIdx); 58239462Sdim void evaluateExpansion(Record *Pseudo); 59239462Sdim void emitLoweringEmitter(raw_ostream &o); 60239462Sdimpublic: 61239462Sdim PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {} 62239462Sdim 63239462Sdim /// run - Output the pseudo-lowerings. 64239462Sdim void run(raw_ostream &o); 65239462Sdim}; 66239462Sdim} // End anonymous namespace 67239462Sdim 68224133Sdim// FIXME: This pass currently can only expand a pseudo to a single instruction. 69224133Sdim// The pseudo expansion really should take a list of dags, not just 70224133Sdim// a single dag, so we can do fancier things. 71224133Sdim 72224133Sdimunsigned PseudoLoweringEmitter:: 73224133SdimaddDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, 74224133Sdim IndexedMap<OpData> &OperandMap, unsigned BaseIdx) { 75224133Sdim unsigned OpsAdded = 0; 76224133Sdim for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) { 77243830Sdim if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) { 78224133Sdim // Physical register reference. Explicit check for the special case 79224133Sdim // "zero_reg" definition. 80224133Sdim if (DI->getDef()->isSubClassOf("Register") || 81224133Sdim DI->getDef()->getName() == "zero_reg") { 82224133Sdim OperandMap[BaseIdx + i].Kind = OpData::Reg; 83224133Sdim OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); 84224133Sdim ++OpsAdded; 85224133Sdim continue; 86224133Sdim } 87224133Sdim 88224133Sdim // Normal operands should always have the same type, or we have a 89224133Sdim // problem. 90224133Sdim // FIXME: We probably shouldn't ever get a non-zero BaseIdx here. 91224133Sdim assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!"); 92224133Sdim if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) 93243830Sdim PrintFatalError(Rec->getLoc(), 94224133Sdim "Pseudo operand type '" + DI->getDef()->getName() + 95224133Sdim "' does not match expansion operand type '" + 96224133Sdim Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 97224133Sdim // Source operand maps to destination operand. The Data element 98224133Sdim // will be filled in later, just set the Kind for now. Do it 99224133Sdim // for each corresponding MachineInstr operand, not just the first. 100224133Sdim for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 101224133Sdim OperandMap[BaseIdx + i + I].Kind = OpData::Operand; 102224133Sdim OpsAdded += Insn.Operands[i].MINumOperands; 103243830Sdim } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) { 104224133Sdim OperandMap[BaseIdx + i].Kind = OpData::Imm; 105224133Sdim OperandMap[BaseIdx + i].Data.Imm = II->getValue(); 106224133Sdim ++OpsAdded; 107243830Sdim } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) { 108224133Sdim // Just add the operands recursively. This is almost certainly 109224133Sdim // a constant value for a complex operand (> 1 MI operand). 110224133Sdim unsigned NewOps = 111224133Sdim addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); 112224133Sdim OpsAdded += NewOps; 113224133Sdim // Since we added more than one, we also need to adjust the base. 114224133Sdim BaseIdx += NewOps - 1; 115224133Sdim } else 116234353Sdim llvm_unreachable("Unhandled pseudo-expansion argument type!"); 117224133Sdim } 118224133Sdim return OpsAdded; 119224133Sdim} 120224133Sdim 121224133Sdimvoid PseudoLoweringEmitter::evaluateExpansion(Record *Rec) { 122341825Sdim LLVM_DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n"); 123224133Sdim 124224133Sdim // Validate that the result pattern has the corrent number and types 125224133Sdim // of arguments for the instruction it references. 126224133Sdim DagInit *Dag = Rec->getValueAsDag("ResultInst"); 127224133Sdim assert(Dag && "Missing result instruction in pseudo expansion!"); 128341825Sdim LLVM_DEBUG(dbgs() << " Result: " << *Dag << "\n"); 129224133Sdim 130243830Sdim DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator()); 131224133Sdim if (!OpDef) 132243830Sdim PrintFatalError(Rec->getLoc(), Rec->getName() + 133224133Sdim " has unexpected operator type!"); 134224133Sdim Record *Operator = OpDef->getDef(); 135224133Sdim if (!Operator->isSubClassOf("Instruction")) 136243830Sdim PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 137243830Sdim "' is not an instruction!"); 138224133Sdim 139224133Sdim CodeGenInstruction Insn(Operator); 140224133Sdim 141224133Sdim if (Insn.isCodeGenOnly || Insn.isPseudo) 142243830Sdim PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 143243830Sdim "' cannot be another pseudo instruction!"); 144224133Sdim 145224133Sdim if (Insn.Operands.size() != Dag->getNumArgs()) 146243830Sdim PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 147243830Sdim "' operand count mismatch"); 148224133Sdim 149234353Sdim unsigned NumMIOperands = 0; 150234353Sdim for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) 151234353Sdim NumMIOperands += Insn.Operands[i].MINumOperands; 152224133Sdim IndexedMap<OpData> OperandMap; 153234353Sdim OperandMap.grow(NumMIOperands); 154224133Sdim 155224133Sdim addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0); 156224133Sdim 157224133Sdim // If there are more operands that weren't in the DAG, they have to 158224133Sdim // be operands that have default values, or we have an error. Currently, 159276479Sdim // Operands that are a subclass of OperandWithDefaultOp have default values. 160224133Sdim 161224133Sdim // Validate that each result pattern argument has a matching (by name) 162224133Sdim // argument in the source instruction, in either the (outs) or (ins) list. 163224133Sdim // Also check that the type of the arguments match. 164224133Sdim // 165224133Sdim // Record the mapping of the source to result arguments for use by 166224133Sdim // the lowering emitter. 167224133Sdim CodeGenInstruction SourceInsn(Rec); 168224133Sdim StringMap<unsigned> SourceOperands; 169224133Sdim for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i) 170224133Sdim SourceOperands[SourceInsn.Operands[i].Name] = i; 171224133Sdim 172341825Sdim LLVM_DEBUG(dbgs() << " Operand mapping:\n"); 173224133Sdim for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) { 174224133Sdim // We've already handled constant values. Just map instruction operands 175224133Sdim // here. 176224133Sdim if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand) 177224133Sdim continue; 178224133Sdim StringMap<unsigned>::iterator SourceOp = 179314564Sdim SourceOperands.find(Dag->getArgNameStr(i)); 180224133Sdim if (SourceOp == SourceOperands.end()) 181243830Sdim PrintFatalError(Rec->getLoc(), 182314564Sdim "Pseudo output operand '" + Dag->getArgNameStr(i) + 183243830Sdim "' has no matching source operand."); 184224133Sdim // Map the source operand to the destination operand index for each 185224133Sdim // MachineInstr operand. 186224133Sdim for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 187224133Sdim OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand = 188224133Sdim SourceOp->getValue(); 189224133Sdim 190341825Sdim LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << i 191341825Sdim << "\n"); 192224133Sdim } 193224133Sdim 194224133Sdim Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap)); 195224133Sdim} 196224133Sdim 197224133Sdimvoid PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) { 198224133Sdim // Emit file header. 199239462Sdim emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o); 200224133Sdim 201224133Sdim o << "bool " << Target.getName() + "AsmPrinter" << "::\n" 202224133Sdim << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n" 203276479Sdim << " const MachineInstr *MI) {\n"; 204224133Sdim 205276479Sdim if (!Expansions.empty()) { 206276479Sdim o << " switch (MI->getOpcode()) {\n" 207276479Sdim << " default: return false;\n"; 208276479Sdim for (auto &Expansion : Expansions) { 209276479Sdim CodeGenInstruction &Source = Expansion.Source; 210276479Sdim CodeGenInstruction &Dest = Expansion.Dest; 211276479Sdim o << " case " << Source.Namespace << "::" 212276479Sdim << Source.TheDef->getName() << ": {\n" 213276479Sdim << " MCInst TmpInst;\n" 214276479Sdim << " MCOperand MCOp;\n" 215276479Sdim << " TmpInst.setOpcode(" << Dest.Namespace << "::" 216276479Sdim << Dest.TheDef->getName() << ");\n"; 217276479Sdim 218276479Sdim // Copy the operands from the source instruction. 219276479Sdim // FIXME: Instruction operands with defaults values (predicates and cc_out 220276479Sdim // in ARM, for example shouldn't need explicit values in the 221276479Sdim // expansion DAG. 222276479Sdim unsigned MIOpNo = 0; 223276479Sdim for (const auto &DestOperand : Dest.Operands) { 224276479Sdim o << " // Operand: " << DestOperand.Name << "\n"; 225276479Sdim for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) { 226276479Sdim switch (Expansion.OperandMap[MIOpNo + i].Kind) { 227276479Sdim case OpData::Operand: 228276479Sdim o << " lowerOperand(MI->getOperand(" 229276479Sdim << Source.Operands[Expansion.OperandMap[MIOpNo].Data 230276479Sdim .Operand].MIOperandNo + i 231276479Sdim << "), MCOp);\n" 232276479Sdim << " TmpInst.addOperand(MCOp);\n"; 233276479Sdim break; 234276479Sdim case OpData::Imm: 235288943Sdim o << " TmpInst.addOperand(MCOperand::createImm(" 236276479Sdim << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n"; 237276479Sdim break; 238276479Sdim case OpData::Reg: { 239276479Sdim Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; 240288943Sdim o << " TmpInst.addOperand(MCOperand::createReg("; 241276479Sdim // "zero_reg" is special. 242276479Sdim if (Reg->getName() == "zero_reg") 243276479Sdim o << "0"; 244276479Sdim else 245276479Sdim o << Reg->getValueAsString("Namespace") << "::" 246276479Sdim << Reg->getName(); 247276479Sdim o << "));\n"; 248276479Sdim break; 249276479Sdim } 250276479Sdim } 251224133Sdim } 252276479Sdim MIOpNo += DestOperand.MINumOperands; 253224133Sdim } 254276479Sdim if (Dest.Operands.isVariadic) { 255276479Sdim MIOpNo = Source.Operands.size() + 1; 256276479Sdim o << " // variable_ops\n"; 257276479Sdim o << " for (unsigned i = " << MIOpNo 258276479Sdim << ", e = MI->getNumOperands(); i != e; ++i)\n" 259276479Sdim << " if (lowerOperand(MI->getOperand(i), MCOp))\n" 260276479Sdim << " TmpInst.addOperand(MCOp);\n"; 261276479Sdim } 262276479Sdim o << " EmitToStreamer(OutStreamer, TmpInst);\n" 263276479Sdim << " break;\n" 264276479Sdim << " }\n"; 265224133Sdim } 266276479Sdim o << " }\n return true;"; 267276479Sdim } else 268276479Sdim o << " return false;"; 269276479Sdim 270276479Sdim o << "\n}\n\n"; 271224133Sdim} 272224133Sdim 273224133Sdimvoid PseudoLoweringEmitter::run(raw_ostream &o) { 274224133Sdim Record *ExpansionClass = Records.getClass("PseudoInstExpansion"); 275243830Sdim Record *InstructionClass = Records.getClass("Instruction"); 276224133Sdim assert(ExpansionClass && "PseudoInstExpansion class definition missing!"); 277224133Sdim assert(InstructionClass && "Instruction class definition missing!"); 278224133Sdim 279224133Sdim std::vector<Record*> Insts; 280280031Sdim for (const auto &D : Records.getDefs()) { 281280031Sdim if (D.second->isSubClassOf(ExpansionClass) && 282280031Sdim D.second->isSubClassOf(InstructionClass)) 283280031Sdim Insts.push_back(D.second.get()); 284224133Sdim } 285224133Sdim 286224133Sdim // Process the pseudo expansion definitions, validating them as we do so. 287224133Sdim for (unsigned i = 0, e = Insts.size(); i != e; ++i) 288224133Sdim evaluateExpansion(Insts[i]); 289224133Sdim 290224133Sdim // Generate expansion code to lower the pseudo to an MCInst of the real 291224133Sdim // instruction. 292224133Sdim emitLoweringEmitter(o); 293224133Sdim} 294224133Sdim 295239462Sdimnamespace llvm { 296239462Sdim 297239462Sdimvoid EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) { 298239462Sdim PseudoLoweringEmitter(RK).run(OS); 299239462Sdim} 300239462Sdim 301239462Sdim} // End llvm namespace 302