Searched refs:FSHL (Results 1 - 12 of 12) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2329 { ISD::FSHL, MVT::i64, 4 }
2338 { ISD::FSHL, MVT::i32, 4 },
2339 { ISD::FSHL, MVT::i16, 4 },
2340 { ISD::FSHL, MVT::i8, 4 }
2348 ISD = ISD::FSHL;
2354 ISD = ISD::FSHL;
H A DX86ISelLowering.cpp208 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
1638 setOperationAction(ISD::FSHL, VT, Custom);
1843 setOperationAction(ISD::FSHL, MVT::v32i16, Custom);
1899 setOperationAction(ISD::FSHL, VT, Custom);
18490 // ISD::FSHL and ISD::FSHR have defined overflow behavior but ISD::SHL and
18501 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt);
18531 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) &&
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp246 case ISD::FSHL: return "fshl";
H A DLegalizeVectorOps.cpp388 case ISD::FSHL:
913 case ISD::FSHL:
H A DTargetLowering.cpp1539 case ISD::FSHL:
1544 bool IsFSHL = (Op.getOpcode() == ISD::FSHL);
5953 bool IsFSHL = Node->getOpcode() == ISD::FSHL;
H A DLegalizeDAG.cpp1198 case ISD::FSHL:
3400 case ISD::FSHL:
H A DSelectionDAG.cpp2918 case ISD::FSHL:
2926 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1),
2935 if (Opcode == ISD::FSHL) {
H A DDAGCombiner.cpp1551 case ISD::FSHL:
8129 bool IsFSHL = N->getOpcode() == ISD::FSHL;
H A DSelectionDAGBuilder.cpp6353 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp651 setOperationAction(ISD::FSHL, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1422 setOperationAction(ISD::FSHL, MVT::i32, Legal);
1423 setOperationAction(ISD::FSHL, MVT::i64, Legal);

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